diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2565,14 +2565,15 @@ }; // This is an interim calling convention and it may be changed in the future. static const MCPhysReg ArgVRs[] = { - RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, - RISCV::V21, RISCV::V22, RISCV::V23 -}; -static const MCPhysReg ArgVRM2s[] = { - RISCV::V16M2, RISCV::V18M2, RISCV::V20M2, RISCV::V22M2 -}; -static const MCPhysReg ArgVRM4s[] = {RISCV::V16M4, RISCV::V20M4}; -static const MCPhysReg ArgVRM8s[] = {RISCV::V16M8}; + RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, + RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, + RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23}; +static const MCPhysReg ArgVRM2s[] = {RISCV::V8M2, RISCV::V10M2, RISCV::V12M2, + RISCV::V14M2, RISCV::V16M2, RISCV::V18M2, + RISCV::V20M2, RISCV::V22M2}; +static const MCPhysReg ArgVRM4s[] = {RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, + RISCV::V20M4}; +static const MCPhysReg ArgVRM8s[] = {RISCV::V8M8, RISCV::V16M8}; // Pass a 2*XLEN argument that has been split into two XLEN values through // registers or the stack as necessary. diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll @@ -6,7 +6,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -27,7 +27,7 @@ ; CHECK-LABEL: trunc_nxv1i8_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -39,7 +39,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -50,7 +50,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -60,7 +60,7 @@ ; CHECK-LABEL: trunc_nxv2i8_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -72,7 +72,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -83,7 +83,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -93,7 +93,7 @@ ; CHECK-LABEL: trunc_nxv4i8_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -105,7 +105,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -116,7 +116,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -126,7 +126,7 @@ ; CHECK-LABEL: trunc_nxv8i8_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -138,7 +138,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -149,7 +149,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -159,7 +159,7 @@ ; CHECK-LABEL: trunc_nxv16i8_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vi v26, v16, 1 +; CHECK-NEXT: vand.vi v26, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v26, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -171,7 +171,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -192,7 +192,7 @@ ; CHECK-LABEL: trunc_nxv32i8_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vi v28, v16, 1 +; CHECK-NEXT: vand.vi v28, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v28, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -204,7 +204,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -215,7 +215,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -225,7 +225,7 @@ ; CHECK-LABEL: trunc_nxv64i8_nxv64i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -237,7 +237,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -248,7 +248,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -258,7 +258,7 @@ ; CHECK-LABEL: trunc_nxv1i16_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -270,7 +270,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -281,7 +281,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -291,7 +291,7 @@ ; CHECK-LABEL: trunc_nxv2i16_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -303,7 +303,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -314,7 +314,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -324,7 +324,7 @@ ; CHECK-LABEL: trunc_nxv4i16_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -336,7 +336,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -347,7 +347,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -357,7 +357,7 @@ ; CHECK-LABEL: trunc_nxv8i16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vi v26, v16, 1 +; CHECK-NEXT: vand.vi v26, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v26, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -369,7 +369,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -380,7 +380,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -390,7 +390,7 @@ ; CHECK-LABEL: trunc_nxv16i16_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vi v28, v16, 1 +; CHECK-NEXT: vand.vi v28, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v28, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -402,7 +402,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -413,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -423,7 +423,7 @@ ; CHECK-LABEL: trunc_nxv32i16_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -435,7 +435,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -446,7 +446,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -456,7 +456,7 @@ ; CHECK-LABEL: trunc_nxv1i32_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -468,7 +468,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -479,7 +479,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -489,7 +489,7 @@ ; CHECK-LABEL: trunc_nxv2i32_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -501,7 +501,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -512,7 +512,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -522,7 +522,7 @@ ; CHECK-LABEL: trunc_nxv4i32_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vi v26, v16, 1 +; CHECK-NEXT: vand.vi v26, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v26, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -534,7 +534,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -545,7 +545,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -555,7 +555,7 @@ ; CHECK-LABEL: trunc_nxv8i32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vi v28, v16, 1 +; CHECK-NEXT: vand.vi v28, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v28, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -567,7 +567,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -578,7 +578,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -588,7 +588,7 @@ ; CHECK-LABEL: trunc_nxv16i32_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -600,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -611,7 +611,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -621,7 +621,7 @@ ; CHECK-LABEL: trunc_nxv1i64_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -633,7 +633,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -644,7 +644,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -654,7 +654,7 @@ ; CHECK-LABEL: trunc_nxv2i64_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vi v26, v16, 1 +; CHECK-NEXT: vand.vi v26, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v26, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -666,7 +666,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -677,7 +677,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -687,7 +687,7 @@ ; CHECK-LABEL: trunc_nxv4i64_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vi v28, v16, 1 +; CHECK-NEXT: vand.vi v28, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v28, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -699,7 +699,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -710,7 +710,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -720,7 +720,7 @@ ; CHECK-LABEL: trunc_nxv8i64_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to diff --git a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll @@ -6,7 +6,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -27,7 +27,7 @@ ; CHECK-LABEL: trunc_nxv1i8_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -39,7 +39,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -50,7 +50,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -60,7 +60,7 @@ ; CHECK-LABEL: trunc_nxv2i8_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -72,7 +72,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -83,7 +83,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -93,7 +93,7 @@ ; CHECK-LABEL: trunc_nxv4i8_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -105,7 +105,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -116,7 +116,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -126,7 +126,7 @@ ; CHECK-LABEL: trunc_nxv8i8_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -138,7 +138,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -149,7 +149,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -159,7 +159,7 @@ ; CHECK-LABEL: trunc_nxv16i8_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vi v26, v16, 1 +; CHECK-NEXT: vand.vi v26, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v26, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -171,7 +171,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -192,7 +192,7 @@ ; CHECK-LABEL: trunc_nxv32i8_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vi v28, v16, 1 +; CHECK-NEXT: vand.vi v28, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v28, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -204,7 +204,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -215,7 +215,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -225,7 +225,7 @@ ; CHECK-LABEL: trunc_nxv64i8_nxv64i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -237,7 +237,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -248,7 +248,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -258,7 +258,7 @@ ; CHECK-LABEL: trunc_nxv1i16_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -270,7 +270,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -281,7 +281,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -291,7 +291,7 @@ ; CHECK-LABEL: trunc_nxv2i16_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -303,7 +303,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -314,7 +314,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -324,7 +324,7 @@ ; CHECK-LABEL: trunc_nxv4i16_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -336,7 +336,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -347,7 +347,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -357,7 +357,7 @@ ; CHECK-LABEL: trunc_nxv8i16_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vi v26, v16, 1 +; CHECK-NEXT: vand.vi v26, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v26, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -369,7 +369,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -380,7 +380,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -390,7 +390,7 @@ ; CHECK-LABEL: trunc_nxv16i16_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vi v28, v16, 1 +; CHECK-NEXT: vand.vi v28, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v28, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -402,7 +402,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -413,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -423,7 +423,7 @@ ; CHECK-LABEL: trunc_nxv32i16_nxv32i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -435,7 +435,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -446,7 +446,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -456,7 +456,7 @@ ; CHECK-LABEL: trunc_nxv1i32_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -468,7 +468,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -479,7 +479,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -489,7 +489,7 @@ ; CHECK-LABEL: trunc_nxv2i32_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -501,7 +501,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -512,7 +512,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -522,7 +522,7 @@ ; CHECK-LABEL: trunc_nxv4i32_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vi v26, v16, 1 +; CHECK-NEXT: vand.vi v26, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v26, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -534,7 +534,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -545,7 +545,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -555,7 +555,7 @@ ; CHECK-LABEL: trunc_nxv8i32_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vi v28, v16, 1 +; CHECK-NEXT: vand.vi v28, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v28, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -567,7 +567,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -578,7 +578,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -588,7 +588,7 @@ ; CHECK-LABEL: trunc_nxv16i32_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -600,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -611,7 +611,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmerge.vim v16, v25, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v25, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -621,7 +621,7 @@ ; CHECK-LABEL: trunc_nxv1i64_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vi v25, v16, 1 +; CHECK-NEXT: vand.vi v25, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -633,7 +633,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -644,7 +644,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmerge.vim v16, v26, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v26, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -654,7 +654,7 @@ ; CHECK-LABEL: trunc_nxv2i64_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vi v26, v16, 1 +; CHECK-NEXT: vand.vi v26, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v26, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -666,7 +666,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -677,7 +677,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmerge.vim v16, v28, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v28, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -687,7 +687,7 @@ ; CHECK-LABEL: trunc_nxv4i64_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vi v28, v16, 1 +; CHECK-NEXT: vand.vi v28, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v28, 0 ; CHECK-NEXT: ret %r = trunc %v to @@ -699,7 +699,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, -1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret %r = sext %v to ret %r @@ -710,7 +710,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmerge.vim v16, v8, 1, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret %r = zext %v to ret %r @@ -720,7 +720,7 @@ ; CHECK-LABEL: trunc_nxv8i64_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vand.vi v8, v16, 1 +; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret %r = trunc %v to diff --git a/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll @@ -7,13 +7,13 @@ ; CHECK-LABEL: saddo_nvx2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmslt.vx v25, v17, zero -; CHECK-NEXT: vadd.vv v26, v16, v17 -; CHECK-NEXT: vmslt.vv v27, v26, v16 +; CHECK-NEXT: vmslt.vx v25, v9, zero +; CHECK-NEXT: vadd.vv v26, v8, v9 +; CHECK-NEXT: vmslt.vv v27, v26, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu ; CHECK-NEXT: vmxor.mm v0, v25, v27 ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmerge.vim v16, v26, 0, v0 +; CHECK-NEXT: vmerge.vim v8, v26, 0, v0 ; CHECK-NEXT: ret %a = call { , } @llvm.sadd.with.overflow.nxv2i32( %x, %y) %b = extractvalue { , } %a, 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: fcmp_oeq_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v18 +; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -20,7 +20,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -33,7 +33,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -45,7 +45,7 @@ ; CHECK-LABEL: fcmp_oeq_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v18 +; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -56,7 +56,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK-LABEL: fcmp_ogt_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v18, v16 +; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -79,7 +79,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -92,7 +92,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -104,7 +104,7 @@ ; CHECK-LABEL: fcmp_ogt_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v18, v16 +; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -115,7 +115,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -127,7 +127,7 @@ ; CHECK-LABEL: fcmp_oge_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v18, v16 +; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -138,7 +138,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -151,7 +151,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -163,7 +163,7 @@ ; CHECK-LABEL: fcmp_oge_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v18, v16 +; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -174,7 +174,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -186,7 +186,7 @@ ; CHECK-LABEL: fcmp_olt_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v18 +; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -197,7 +197,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -210,7 +210,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -222,7 +222,7 @@ ; CHECK-LABEL: fcmp_olt_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v18 +; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -233,7 +233,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +245,7 @@ ; CHECK-LABEL: fcmp_ole_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v18 +; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -256,7 +256,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -269,7 +269,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +281,7 @@ ; CHECK-LABEL: fcmp_ole_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v18 +; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -292,7 +292,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -304,8 +304,8 @@ ; CHECK-LABEL: fcmp_one_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v18 -; CHECK-NEXT: vmflt.vv v26, v18, v16 +; CHECK-NEXT: vmflt.vv v25, v8, v10 +; CHECK-NEXT: vmflt.vv v26, v10, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -318,8 +318,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -334,8 +334,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -349,7 +349,7 @@ ; CHECK-LABEL: fcmp_one_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v18 +; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp one %va, %vb ret %vc @@ -360,7 +360,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -372,8 +372,8 @@ ; CHECK-LABEL: fcmp_ord_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v25, v18, v18 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v25, v10, v10 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -388,7 +388,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -405,7 +405,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -419,8 +419,8 @@ ; CHECK-LABEL: fcmp_ord_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v25, v18, v18 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v25, v10, v10 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -435,7 +435,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -449,8 +449,8 @@ ; CHECK-LABEL: fcmp_ueq_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v18 -; CHECK-NEXT: vmflt.vv v26, v18, v16 +; CHECK-NEXT: vmflt.vv v25, v8, v10 +; CHECK-NEXT: vmflt.vv v26, v10, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -463,8 +463,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -479,8 +479,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -494,7 +494,7 @@ ; CHECK-LABEL: fcmp_ueq_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v18 +; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ueq %va, %vb ret %vc @@ -505,7 +505,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -517,7 +517,7 @@ ; CHECK-LABEL: fcmp_ugt_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v25, v16, v18 +; CHECK-NEXT: vmfle.vv v25, v8, v10 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -531,7 +531,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -547,7 +547,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -562,7 +562,7 @@ ; CHECK-LABEL: fcmp_ugt_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v18, v16 +; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp ugt %va, %vb ret %vc @@ -573,7 +573,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -585,7 +585,7 @@ ; CHECK-LABEL: fcmp_uge_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v18 +; CHECK-NEXT: vmflt.vv v25, v8, v10 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -599,7 +599,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -615,7 +615,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -630,7 +630,7 @@ ; CHECK-LABEL: fcmp_uge_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v18, v16 +; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp uge %va, %vb ret %vc @@ -641,7 +641,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -653,7 +653,7 @@ ; CHECK-LABEL: fcmp_ult_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v25, v18, v16 +; CHECK-NEXT: vmfle.vv v25, v10, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -667,7 +667,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -683,7 +683,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -698,7 +698,7 @@ ; CHECK-LABEL: fcmp_ult_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v18 +; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ult %va, %vb ret %vc @@ -709,7 +709,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -721,7 +721,7 @@ ; CHECK-LABEL: fcmp_ule_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v25, v18, v16 +; CHECK-NEXT: vmflt.vv v25, v10, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -735,7 +735,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -751,7 +751,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -766,7 +766,7 @@ ; CHECK-LABEL: fcmp_ule_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v18 +; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ule %va, %vb ret %vc @@ -777,7 +777,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -789,7 +789,7 @@ ; CHECK-LABEL: fcmp_une_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v18 +; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -800,7 +800,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -813,7 +813,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -825,7 +825,7 @@ ; CHECK-LABEL: fcmp_une_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v18 +; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -836,7 +836,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -848,8 +848,8 @@ ; CHECK-LABEL: fcmp_uno_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v25, v18, v18 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v25, v10, v10 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -864,7 +864,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -881,7 +881,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -895,8 +895,8 @@ ; CHECK-LABEL: fcmp_uno_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v25, v18, v18 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v25, v10, v10 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -911,7 +911,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -925,7 +925,7 @@ ; CHECK-LABEL: fcmp_oeq_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v20 +; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -935,7 +935,7 @@ ; CHECK-LABEL: fcmp_oeq_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -947,7 +947,7 @@ ; CHECK-LABEL: fcmp_oeq_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -959,7 +959,7 @@ ; CHECK-LABEL: fcmp_oeq_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v20 +; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -969,7 +969,7 @@ ; CHECK-LABEL: fcmp_oeq_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -981,7 +981,7 @@ ; CHECK-LABEL: fcmp_ogt_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v20, v16 +; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -991,7 +991,7 @@ ; CHECK-LABEL: fcmp_ogt_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1003,7 +1003,7 @@ ; CHECK-LABEL: fcmp_ogt_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1015,7 +1015,7 @@ ; CHECK-LABEL: fcmp_ogt_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v20, v16 +; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -1025,7 +1025,7 @@ ; CHECK-LABEL: fcmp_ogt_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1037,7 +1037,7 @@ ; CHECK-LABEL: fcmp_oge_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v20, v16 +; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -1047,7 +1047,7 @@ ; CHECK-LABEL: fcmp_oge_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1059,7 +1059,7 @@ ; CHECK-LABEL: fcmp_oge_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1071,7 +1071,7 @@ ; CHECK-LABEL: fcmp_oge_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v20, v16 +; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -1081,7 +1081,7 @@ ; CHECK-LABEL: fcmp_oge_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1093,7 +1093,7 @@ ; CHECK-LABEL: fcmp_olt_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v20 +; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -1103,7 +1103,7 @@ ; CHECK-LABEL: fcmp_olt_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1115,7 +1115,7 @@ ; CHECK-LABEL: fcmp_olt_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1127,7 +1127,7 @@ ; CHECK-LABEL: fcmp_olt_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v20 +; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -1137,7 +1137,7 @@ ; CHECK-LABEL: fcmp_olt_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1149,7 +1149,7 @@ ; CHECK-LABEL: fcmp_ole_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v20 +; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -1159,7 +1159,7 @@ ; CHECK-LABEL: fcmp_ole_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1171,7 +1171,7 @@ ; CHECK-LABEL: fcmp_ole_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1183,7 +1183,7 @@ ; CHECK-LABEL: fcmp_ole_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v20 +; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -1193,7 +1193,7 @@ ; CHECK-LABEL: fcmp_ole_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1205,8 +1205,8 @@ ; CHECK-LABEL: fcmp_one_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v20 -; CHECK-NEXT: vmflt.vv v26, v20, v16 +; CHECK-NEXT: vmflt.vv v25, v8, v12 +; CHECK-NEXT: vmflt.vv v26, v12, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1218,8 +1218,8 @@ ; CHECK-LABEL: fcmp_one_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1233,8 +1233,8 @@ ; CHECK-LABEL: fcmp_one_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1248,7 +1248,7 @@ ; CHECK-LABEL: fcmp_one_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v20 +; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp one %va, %vb ret %vc @@ -1258,7 +1258,7 @@ ; CHECK-LABEL: fcmp_one_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1270,8 +1270,8 @@ ; CHECK-LABEL: fcmp_ord_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v25, v20, v20 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v25, v12, v12 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1285,7 +1285,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1301,7 +1301,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -1315,8 +1315,8 @@ ; CHECK-LABEL: fcmp_ord_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v25, v20, v20 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v25, v12, v12 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1330,7 +1330,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1344,8 +1344,8 @@ ; CHECK-LABEL: fcmp_ueq_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v20 -; CHECK-NEXT: vmflt.vv v26, v20, v16 +; CHECK-NEXT: vmflt.vv v25, v8, v12 +; CHECK-NEXT: vmflt.vv v26, v12, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1357,8 +1357,8 @@ ; CHECK-LABEL: fcmp_ueq_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1372,8 +1372,8 @@ ; CHECK-LABEL: fcmp_ueq_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1387,7 +1387,7 @@ ; CHECK-LABEL: fcmp_ueq_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v20 +; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ueq %va, %vb ret %vc @@ -1397,7 +1397,7 @@ ; CHECK-LABEL: fcmp_ueq_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1409,7 +1409,7 @@ ; CHECK-LABEL: fcmp_ugt_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v25, v16, v20 +; CHECK-NEXT: vmfle.vv v25, v8, v12 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1422,7 +1422,7 @@ ; CHECK-LABEL: fcmp_ugt_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1437,7 +1437,7 @@ ; CHECK-LABEL: fcmp_ugt_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1452,7 +1452,7 @@ ; CHECK-LABEL: fcmp_ugt_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v20, v16 +; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp ugt %va, %vb ret %vc @@ -1462,7 +1462,7 @@ ; CHECK-LABEL: fcmp_ugt_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1474,7 +1474,7 @@ ; CHECK-LABEL: fcmp_uge_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v20 +; CHECK-NEXT: vmflt.vv v25, v8, v12 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1487,7 +1487,7 @@ ; CHECK-LABEL: fcmp_uge_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1502,7 +1502,7 @@ ; CHECK-LABEL: fcmp_uge_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1517,7 +1517,7 @@ ; CHECK-LABEL: fcmp_uge_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v20, v16 +; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp uge %va, %vb ret %vc @@ -1527,7 +1527,7 @@ ; CHECK-LABEL: fcmp_uge_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1539,7 +1539,7 @@ ; CHECK-LABEL: fcmp_ult_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v25, v20, v16 +; CHECK-NEXT: vmfle.vv v25, v12, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1552,7 +1552,7 @@ ; CHECK-LABEL: fcmp_ult_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1567,7 +1567,7 @@ ; CHECK-LABEL: fcmp_ult_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1582,7 +1582,7 @@ ; CHECK-LABEL: fcmp_ult_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v20 +; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ult %va, %vb ret %vc @@ -1592,7 +1592,7 @@ ; CHECK-LABEL: fcmp_ult_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1604,7 +1604,7 @@ ; CHECK-LABEL: fcmp_ule_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v25, v20, v16 +; CHECK-NEXT: vmflt.vv v25, v12, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1617,7 +1617,7 @@ ; CHECK-LABEL: fcmp_ule_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1632,7 +1632,7 @@ ; CHECK-LABEL: fcmp_ule_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1647,7 +1647,7 @@ ; CHECK-LABEL: fcmp_ule_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v20 +; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ule %va, %vb ret %vc @@ -1657,7 +1657,7 @@ ; CHECK-LABEL: fcmp_ule_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1669,7 +1669,7 @@ ; CHECK-LABEL: fcmp_une_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v20 +; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -1679,7 +1679,7 @@ ; CHECK-LABEL: fcmp_une_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1691,7 +1691,7 @@ ; CHECK-LABEL: fcmp_une_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1703,7 +1703,7 @@ ; CHECK-LABEL: fcmp_une_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v20 +; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -1713,7 +1713,7 @@ ; CHECK-LABEL: fcmp_une_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1725,8 +1725,8 @@ ; CHECK-LABEL: fcmp_uno_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v25, v20, v20 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v25, v12, v12 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1740,7 +1740,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1756,7 +1756,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -1770,8 +1770,8 @@ ; CHECK-LABEL: fcmp_uno_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v25, v20, v20 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v25, v12, v12 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1785,7 +1785,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1798,9 +1798,8 @@ define @fcmp_oeq_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_oeq_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfeq.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -1810,7 +1809,7 @@ ; CHECK-LABEL: fcmp_oeq_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1822,7 +1821,7 @@ ; CHECK-LABEL: fcmp_oeq_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1833,9 +1832,8 @@ define @fcmp_oeq_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_oeq_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfeq.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -1845,7 +1843,7 @@ ; CHECK-LABEL: fcmp_oeq_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1856,9 +1854,8 @@ define @fcmp_ogt_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ogt_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -1868,7 +1865,7 @@ ; CHECK-LABEL: fcmp_ogt_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1880,7 +1877,7 @@ ; CHECK-LABEL: fcmp_ogt_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1891,9 +1888,8 @@ define @fcmp_ogt_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ogt_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -1903,7 +1899,7 @@ ; CHECK-LABEL: fcmp_ogt_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1914,9 +1910,8 @@ define @fcmp_oge_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_oge_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -1926,7 +1921,7 @@ ; CHECK-LABEL: fcmp_oge_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1938,7 +1933,7 @@ ; CHECK-LABEL: fcmp_oge_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1949,9 +1944,8 @@ define @fcmp_oge_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_oge_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -1961,7 +1955,7 @@ ; CHECK-LABEL: fcmp_oge_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1972,9 +1966,8 @@ define @fcmp_olt_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_olt_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -1984,7 +1977,7 @@ ; CHECK-LABEL: fcmp_olt_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1996,7 +1989,7 @@ ; CHECK-LABEL: fcmp_olt_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2007,9 +2000,8 @@ define @fcmp_olt_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_olt_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -2019,7 +2011,7 @@ ; CHECK-LABEL: fcmp_olt_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2030,9 +2022,8 @@ define @fcmp_ole_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ole_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -2042,7 +2033,7 @@ ; CHECK-LABEL: fcmp_ole_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2054,7 +2045,7 @@ ; CHECK-LABEL: fcmp_ole_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2065,9 +2056,8 @@ define @fcmp_ole_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ole_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -2077,7 +2067,7 @@ ; CHECK-LABEL: fcmp_ole_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2088,10 +2078,9 @@ define @fcmp_one_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_one_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v25, v16, v8 -; CHECK-NEXT: vmflt.vv v26, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v25, v8, v16 +; CHECK-NEXT: vmflt.vv v26, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2103,8 +2092,8 @@ ; CHECK-LABEL: fcmp_one_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2118,8 +2107,8 @@ ; CHECK-LABEL: fcmp_one_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2132,9 +2121,8 @@ define @fcmp_one_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_one_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfne.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp one %va, %vb ret %vc @@ -2144,7 +2132,7 @@ ; CHECK-LABEL: fcmp_one_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2155,12 +2143,11 @@ define @fcmp_ord_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ord_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmfeq.vv v25, v16, v16 ; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret %vc = fcmp ord %va, %vb ret %vc @@ -2170,9 +2157,9 @@ ; CHECK-LABEL: fcmp_ord_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfeq.vf v25, v8, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfeq.vf v25, v16, fa0 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2186,9 +2173,9 @@ ; CHECK-LABEL: fcmp_ord_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfeq.vf v25, v8, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfeq.vf v25, v16, fa0 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -2201,12 +2188,11 @@ define @fcmp_ord_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ord_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmfeq.vv v25, v16, v16 ; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret %vc = fcmp ord %va, %vb ret %vc @@ -2216,9 +2202,9 @@ ; CHECK-LABEL: fcmp_ord_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfeq.vf v25, v8, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfeq.vf v25, v16, fa0 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2231,10 +2217,9 @@ define @fcmp_ueq_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ueq_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v25, v16, v8 -; CHECK-NEXT: vmflt.vv v26, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v25, v8, v16 +; CHECK-NEXT: vmflt.vv v26, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2246,8 +2231,8 @@ ; CHECK-LABEL: fcmp_ueq_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2261,8 +2246,8 @@ ; CHECK-LABEL: fcmp_ueq_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2275,9 +2260,8 @@ define @fcmp_ueq_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ueq_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfeq.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ueq %va, %vb ret %vc @@ -2287,7 +2271,7 @@ ; CHECK-LABEL: fcmp_ueq_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2298,9 +2282,8 @@ define @fcmp_ugt_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ugt_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v25, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v25, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2313,7 +2296,7 @@ ; CHECK-LABEL: fcmp_ugt_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2328,7 +2311,7 @@ ; CHECK-LABEL: fcmp_ugt_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2342,9 +2325,8 @@ define @fcmp_ugt_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ugt_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp ugt %va, %vb ret %vc @@ -2354,7 +2336,7 @@ ; CHECK-LABEL: fcmp_ugt_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2365,9 +2347,8 @@ define @fcmp_uge_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_uge_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v25, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v25, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2380,7 +2361,7 @@ ; CHECK-LABEL: fcmp_uge_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2395,7 +2376,7 @@ ; CHECK-LABEL: fcmp_uge_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2409,9 +2390,8 @@ define @fcmp_uge_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_uge_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp uge %va, %vb ret %vc @@ -2421,7 +2401,7 @@ ; CHECK-LABEL: fcmp_uge_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2432,9 +2412,8 @@ define @fcmp_ult_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ult_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v25, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v25, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2447,7 +2426,7 @@ ; CHECK-LABEL: fcmp_ult_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2462,7 +2441,7 @@ ; CHECK-LABEL: fcmp_ult_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2476,9 +2455,8 @@ define @fcmp_ult_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ult_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ult %va, %vb ret %vc @@ -2488,7 +2466,7 @@ ; CHECK-LABEL: fcmp_ult_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2499,9 +2477,8 @@ define @fcmp_ule_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ule_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v25, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v25, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2514,7 +2491,7 @@ ; CHECK-LABEL: fcmp_ule_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2529,7 +2506,7 @@ ; CHECK-LABEL: fcmp_ule_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2543,9 +2520,8 @@ define @fcmp_ule_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ule_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ule %va, %vb ret %vc @@ -2555,7 +2531,7 @@ ; CHECK-LABEL: fcmp_ule_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2566,9 +2542,8 @@ define @fcmp_une_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_une_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfne.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -2578,7 +2553,7 @@ ; CHECK-LABEL: fcmp_une_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2590,7 +2565,7 @@ ; CHECK-LABEL: fcmp_une_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2601,9 +2576,8 @@ define @fcmp_une_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_une_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfne.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -2613,7 +2587,7 @@ ; CHECK-LABEL: fcmp_une_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2624,12 +2598,11 @@ define @fcmp_uno_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_uno_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmfne.vv v25, v16, v16 ; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret %vc = fcmp uno %va, %vb ret %vc @@ -2639,9 +2612,9 @@ ; CHECK-LABEL: fcmp_uno_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfne.vf v25, v8, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfne.vf v25, v16, fa0 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2655,9 +2628,9 @@ ; CHECK-LABEL: fcmp_uno_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfne.vf v25, v8, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfne.vf v25, v16, fa0 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -2670,12 +2643,11 @@ define @fcmp_uno_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_uno_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmfne.vv v25, v16, v16 ; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret %vc = fcmp uno %va, %vb ret %vc @@ -2685,9 +2657,9 @@ ; CHECK-LABEL: fcmp_uno_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfne.vf v25, v8, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfne.vf v25, v16, fa0 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: fcmp_oeq_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v18 +; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -20,7 +20,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -33,7 +33,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -45,7 +45,7 @@ ; CHECK-LABEL: fcmp_oeq_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v18 +; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -56,7 +56,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK-LABEL: fcmp_ogt_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v18, v16 +; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -79,7 +79,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -92,7 +92,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -104,7 +104,7 @@ ; CHECK-LABEL: fcmp_ogt_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v18, v16 +; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -115,7 +115,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -127,7 +127,7 @@ ; CHECK-LABEL: fcmp_oge_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v18, v16 +; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -138,7 +138,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -151,7 +151,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -163,7 +163,7 @@ ; CHECK-LABEL: fcmp_oge_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v18, v16 +; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -174,7 +174,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -186,7 +186,7 @@ ; CHECK-LABEL: fcmp_olt_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v18 +; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -197,7 +197,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -210,7 +210,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -222,7 +222,7 @@ ; CHECK-LABEL: fcmp_olt_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v18 +; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -233,7 +233,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +245,7 @@ ; CHECK-LABEL: fcmp_ole_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v18 +; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -256,7 +256,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -269,7 +269,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +281,7 @@ ; CHECK-LABEL: fcmp_ole_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v18 +; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -292,7 +292,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -304,8 +304,8 @@ ; CHECK-LABEL: fcmp_one_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v18 -; CHECK-NEXT: vmflt.vv v26, v18, v16 +; CHECK-NEXT: vmflt.vv v25, v8, v10 +; CHECK-NEXT: vmflt.vv v26, v10, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -318,8 +318,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -334,8 +334,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -349,7 +349,7 @@ ; CHECK-LABEL: fcmp_one_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v18 +; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp one %va, %vb ret %vc @@ -360,7 +360,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -372,8 +372,8 @@ ; CHECK-LABEL: fcmp_ord_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v25, v18, v18 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v25, v10, v10 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -388,7 +388,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -405,7 +405,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -419,8 +419,8 @@ ; CHECK-LABEL: fcmp_ord_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v25, v18, v18 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v25, v10, v10 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -435,7 +435,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfeq.vf v25, v26, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -449,8 +449,8 @@ ; CHECK-LABEL: fcmp_ueq_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v18 -; CHECK-NEXT: vmflt.vv v26, v18, v16 +; CHECK-NEXT: vmflt.vv v25, v8, v10 +; CHECK-NEXT: vmflt.vv v26, v10, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -463,8 +463,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -479,8 +479,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -494,7 +494,7 @@ ; CHECK-LABEL: fcmp_ueq_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v18 +; CHECK-NEXT: vmfeq.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ueq %va, %vb ret %vc @@ -505,7 +505,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -517,7 +517,7 @@ ; CHECK-LABEL: fcmp_ugt_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v25, v16, v18 +; CHECK-NEXT: vmfle.vv v25, v8, v10 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -531,7 +531,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -547,7 +547,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -562,7 +562,7 @@ ; CHECK-LABEL: fcmp_ugt_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v18, v16 +; CHECK-NEXT: vmflt.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp ugt %va, %vb ret %vc @@ -573,7 +573,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -585,7 +585,7 @@ ; CHECK-LABEL: fcmp_uge_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v18 +; CHECK-NEXT: vmflt.vv v25, v8, v10 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -599,7 +599,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -615,7 +615,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -630,7 +630,7 @@ ; CHECK-LABEL: fcmp_uge_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v18, v16 +; CHECK-NEXT: vmfle.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = fcmp uge %va, %vb ret %vc @@ -641,7 +641,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -653,7 +653,7 @@ ; CHECK-LABEL: fcmp_ult_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v25, v18, v16 +; CHECK-NEXT: vmfle.vv v25, v10, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -667,7 +667,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -683,7 +683,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -698,7 +698,7 @@ ; CHECK-LABEL: fcmp_ult_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v18 +; CHECK-NEXT: vmflt.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ult %va, %vb ret %vc @@ -709,7 +709,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -721,7 +721,7 @@ ; CHECK-LABEL: fcmp_ule_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vv v25, v18, v16 +; CHECK-NEXT: vmflt.vv v25, v10, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -735,7 +735,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -751,7 +751,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -766,7 +766,7 @@ ; CHECK-LABEL: fcmp_ule_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v18 +; CHECK-NEXT: vmfle.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp ule %va, %vb ret %vc @@ -777,7 +777,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -789,7 +789,7 @@ ; CHECK-LABEL: fcmp_une_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v18 +; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -800,7 +800,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -813,7 +813,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -825,7 +825,7 @@ ; CHECK-LABEL: fcmp_une_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v18 +; CHECK-NEXT: vmfne.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -836,7 +836,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -848,8 +848,8 @@ ; CHECK-LABEL: fcmp_uno_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v25, v18, v18 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v25, v10, v10 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -864,7 +864,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -881,7 +881,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -895,8 +895,8 @@ ; CHECK-LABEL: fcmp_uno_vv_nxv8f16_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmfne.vv v25, v18, v18 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v25, v10, v10 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -911,7 +911,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfne.vf v25, v26, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -925,7 +925,7 @@ ; CHECK-LABEL: fcmp_oeq_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v20 +; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -935,7 +935,7 @@ ; CHECK-LABEL: fcmp_oeq_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -947,7 +947,7 @@ ; CHECK-LABEL: fcmp_oeq_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -959,7 +959,7 @@ ; CHECK-LABEL: fcmp_oeq_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v20 +; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -969,7 +969,7 @@ ; CHECK-LABEL: fcmp_oeq_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -981,7 +981,7 @@ ; CHECK-LABEL: fcmp_ogt_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v20, v16 +; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -991,7 +991,7 @@ ; CHECK-LABEL: fcmp_ogt_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1003,7 +1003,7 @@ ; CHECK-LABEL: fcmp_ogt_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1015,7 +1015,7 @@ ; CHECK-LABEL: fcmp_ogt_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v20, v16 +; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -1025,7 +1025,7 @@ ; CHECK-LABEL: fcmp_ogt_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1037,7 +1037,7 @@ ; CHECK-LABEL: fcmp_oge_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v20, v16 +; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -1047,7 +1047,7 @@ ; CHECK-LABEL: fcmp_oge_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1059,7 +1059,7 @@ ; CHECK-LABEL: fcmp_oge_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1071,7 +1071,7 @@ ; CHECK-LABEL: fcmp_oge_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v20, v16 +; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -1081,7 +1081,7 @@ ; CHECK-LABEL: fcmp_oge_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1093,7 +1093,7 @@ ; CHECK-LABEL: fcmp_olt_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v20 +; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -1103,7 +1103,7 @@ ; CHECK-LABEL: fcmp_olt_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1115,7 +1115,7 @@ ; CHECK-LABEL: fcmp_olt_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1127,7 +1127,7 @@ ; CHECK-LABEL: fcmp_olt_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v20 +; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -1137,7 +1137,7 @@ ; CHECK-LABEL: fcmp_olt_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1149,7 +1149,7 @@ ; CHECK-LABEL: fcmp_ole_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v20 +; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -1159,7 +1159,7 @@ ; CHECK-LABEL: fcmp_ole_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1171,7 +1171,7 @@ ; CHECK-LABEL: fcmp_ole_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1183,7 +1183,7 @@ ; CHECK-LABEL: fcmp_ole_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v20 +; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -1193,7 +1193,7 @@ ; CHECK-LABEL: fcmp_ole_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1205,8 +1205,8 @@ ; CHECK-LABEL: fcmp_one_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v20 -; CHECK-NEXT: vmflt.vv v26, v20, v16 +; CHECK-NEXT: vmflt.vv v25, v8, v12 +; CHECK-NEXT: vmflt.vv v26, v12, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1218,8 +1218,8 @@ ; CHECK-LABEL: fcmp_one_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1233,8 +1233,8 @@ ; CHECK-LABEL: fcmp_one_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1248,7 +1248,7 @@ ; CHECK-LABEL: fcmp_one_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v20 +; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp one %va, %vb ret %vc @@ -1258,7 +1258,7 @@ ; CHECK-LABEL: fcmp_one_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1270,8 +1270,8 @@ ; CHECK-LABEL: fcmp_ord_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v25, v20, v20 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v25, v12, v12 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1285,7 +1285,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1301,7 +1301,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -1315,8 +1315,8 @@ ; CHECK-LABEL: fcmp_ord_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v25, v20, v20 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v25, v12, v12 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1330,7 +1330,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfeq.vf v25, v28, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1344,8 +1344,8 @@ ; CHECK-LABEL: fcmp_ueq_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v20 -; CHECK-NEXT: vmflt.vv v26, v20, v16 +; CHECK-NEXT: vmflt.vv v25, v8, v12 +; CHECK-NEXT: vmflt.vv v26, v12, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1357,8 +1357,8 @@ ; CHECK-LABEL: fcmp_ueq_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1372,8 +1372,8 @@ ; CHECK-LABEL: fcmp_ueq_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1387,7 +1387,7 @@ ; CHECK-LABEL: fcmp_ueq_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vv v0, v16, v20 +; CHECK-NEXT: vmfeq.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ueq %va, %vb ret %vc @@ -1397,7 +1397,7 @@ ; CHECK-LABEL: fcmp_ueq_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1409,7 +1409,7 @@ ; CHECK-LABEL: fcmp_ugt_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v25, v16, v20 +; CHECK-NEXT: vmfle.vv v25, v8, v12 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1422,7 +1422,7 @@ ; CHECK-LABEL: fcmp_ugt_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1437,7 +1437,7 @@ ; CHECK-LABEL: fcmp_ugt_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1452,7 +1452,7 @@ ; CHECK-LABEL: fcmp_ugt_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v20, v16 +; CHECK-NEXT: vmflt.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp ugt %va, %vb ret %vc @@ -1462,7 +1462,7 @@ ; CHECK-LABEL: fcmp_ugt_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1474,7 +1474,7 @@ ; CHECK-LABEL: fcmp_uge_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v25, v16, v20 +; CHECK-NEXT: vmflt.vv v25, v8, v12 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1487,7 +1487,7 @@ ; CHECK-LABEL: fcmp_uge_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1502,7 +1502,7 @@ ; CHECK-LABEL: fcmp_uge_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1517,7 +1517,7 @@ ; CHECK-LABEL: fcmp_uge_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v20, v16 +; CHECK-NEXT: vmfle.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = fcmp uge %va, %vb ret %vc @@ -1527,7 +1527,7 @@ ; CHECK-LABEL: fcmp_uge_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1539,7 +1539,7 @@ ; CHECK-LABEL: fcmp_ult_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v25, v20, v16 +; CHECK-NEXT: vmfle.vv v25, v12, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1552,7 +1552,7 @@ ; CHECK-LABEL: fcmp_ult_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1567,7 +1567,7 @@ ; CHECK-LABEL: fcmp_ult_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1582,7 +1582,7 @@ ; CHECK-LABEL: fcmp_ult_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v0, v16, v20 +; CHECK-NEXT: vmflt.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ult %va, %vb ret %vc @@ -1592,7 +1592,7 @@ ; CHECK-LABEL: fcmp_ult_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1604,7 +1604,7 @@ ; CHECK-LABEL: fcmp_ule_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vv v25, v20, v16 +; CHECK-NEXT: vmflt.vv v25, v12, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1617,7 +1617,7 @@ ; CHECK-LABEL: fcmp_ule_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1632,7 +1632,7 @@ ; CHECK-LABEL: fcmp_ule_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -1647,7 +1647,7 @@ ; CHECK-LABEL: fcmp_ule_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vv v0, v16, v20 +; CHECK-NEXT: vmfle.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp ule %va, %vb ret %vc @@ -1657,7 +1657,7 @@ ; CHECK-LABEL: fcmp_ule_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1669,7 +1669,7 @@ ; CHECK-LABEL: fcmp_une_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v20 +; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -1679,7 +1679,7 @@ ; CHECK-LABEL: fcmp_une_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1691,7 +1691,7 @@ ; CHECK-LABEL: fcmp_une_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1703,7 +1703,7 @@ ; CHECK-LABEL: fcmp_une_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v0, v16, v20 +; CHECK-NEXT: vmfne.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -1713,7 +1713,7 @@ ; CHECK-LABEL: fcmp_une_vf_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1725,8 +1725,8 @@ ; CHECK-LABEL: fcmp_uno_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v25, v20, v20 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v25, v12, v12 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1740,7 +1740,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1756,7 +1756,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -1770,8 +1770,8 @@ ; CHECK-LABEL: fcmp_uno_vv_nxv8f32_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmfne.vv v25, v20, v20 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v25, v12, v12 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1785,7 +1785,7 @@ ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfne.vf v25, v28, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -1798,9 +1798,8 @@ define @fcmp_oeq_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_oeq_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfeq.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -1810,7 +1809,7 @@ ; CHECK-LABEL: fcmp_oeq_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1822,7 +1821,7 @@ ; CHECK-LABEL: fcmp_oeq_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1833,9 +1832,8 @@ define @fcmp_oeq_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_oeq_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfeq.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp oeq %va, %vb ret %vc @@ -1845,7 +1843,7 @@ ; CHECK-LABEL: fcmp_oeq_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1856,9 +1854,8 @@ define @fcmp_ogt_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ogt_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -1868,7 +1865,7 @@ ; CHECK-LABEL: fcmp_ogt_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1880,7 +1877,7 @@ ; CHECK-LABEL: fcmp_ogt_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1891,9 +1888,8 @@ define @fcmp_ogt_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ogt_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp ogt %va, %vb ret %vc @@ -1903,7 +1899,7 @@ ; CHECK-LABEL: fcmp_ogt_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1914,9 +1910,8 @@ define @fcmp_oge_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_oge_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -1926,7 +1921,7 @@ ; CHECK-LABEL: fcmp_oge_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1938,7 +1933,7 @@ ; CHECK-LABEL: fcmp_oge_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1949,9 +1944,8 @@ define @fcmp_oge_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_oge_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp oge %va, %vb ret %vc @@ -1961,7 +1955,7 @@ ; CHECK-LABEL: fcmp_oge_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1972,9 +1966,8 @@ define @fcmp_olt_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_olt_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -1984,7 +1977,7 @@ ; CHECK-LABEL: fcmp_olt_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1996,7 +1989,7 @@ ; CHECK-LABEL: fcmp_olt_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2007,9 +2000,8 @@ define @fcmp_olt_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_olt_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp olt %va, %vb ret %vc @@ -2019,7 +2011,7 @@ ; CHECK-LABEL: fcmp_olt_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2030,9 +2022,8 @@ define @fcmp_ole_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ole_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -2042,7 +2033,7 @@ ; CHECK-LABEL: fcmp_ole_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2054,7 +2045,7 @@ ; CHECK-LABEL: fcmp_ole_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2065,9 +2056,8 @@ define @fcmp_ole_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ole_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ole %va, %vb ret %vc @@ -2077,7 +2067,7 @@ ; CHECK-LABEL: fcmp_ole_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2088,10 +2078,9 @@ define @fcmp_one_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_one_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v25, v16, v8 -; CHECK-NEXT: vmflt.vv v26, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v25, v8, v16 +; CHECK-NEXT: vmflt.vv v26, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2103,8 +2092,8 @@ ; CHECK-LABEL: fcmp_one_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2118,8 +2107,8 @@ ; CHECK-LABEL: fcmp_one_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2132,9 +2121,8 @@ define @fcmp_one_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_one_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfne.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp one %va, %vb ret %vc @@ -2144,7 +2132,7 @@ ; CHECK-LABEL: fcmp_one_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2155,12 +2143,11 @@ define @fcmp_ord_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ord_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmfeq.vv v25, v16, v16 ; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret %vc = fcmp ord %va, %vb ret %vc @@ -2170,9 +2157,9 @@ ; CHECK-LABEL: fcmp_ord_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfeq.vf v25, v8, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfeq.vf v25, v16, fa0 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2186,9 +2173,9 @@ ; CHECK-LABEL: fcmp_ord_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfeq.vf v25, v8, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfeq.vf v25, v16, fa0 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -2201,12 +2188,11 @@ define @fcmp_ord_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ord_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmfeq.vv v25, v16, v16 ; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmand.mm v0, v25, v26 +; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret %vc = fcmp ord %va, %vb ret %vc @@ -2216,9 +2202,9 @@ ; CHECK-LABEL: fcmp_ord_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfeq.vf v25, v8, fa0 -; CHECK-NEXT: vmfeq.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfeq.vf v25, v16, fa0 +; CHECK-NEXT: vmfeq.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmand.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2231,10 +2217,9 @@ define @fcmp_ueq_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ueq_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v25, v16, v8 -; CHECK-NEXT: vmflt.vv v26, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v25, v8, v16 +; CHECK-NEXT: vmflt.vv v26, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2246,8 +2231,8 @@ ; CHECK-LABEL: fcmp_ueq_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 -; CHECK-NEXT: vmfgt.vf v26, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 +; CHECK-NEXT: vmfgt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2261,8 +2246,8 @@ ; CHECK-LABEL: fcmp_ueq_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 -; CHECK-NEXT: vmflt.vf v26, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 +; CHECK-NEXT: vmflt.vf v26, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmnor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2275,9 +2260,8 @@ define @fcmp_ueq_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ueq_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfeq.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ueq %va, %vb ret %vc @@ -2287,7 +2271,7 @@ ; CHECK-LABEL: fcmp_ueq_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfeq.vf v0, v16, fa0 +; CHECK-NEXT: vmfeq.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2298,9 +2282,8 @@ define @fcmp_ugt_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ugt_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v25, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v25, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2313,7 +2296,7 @@ ; CHECK-LABEL: fcmp_ugt_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2328,7 +2311,7 @@ ; CHECK-LABEL: fcmp_ugt_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2342,9 +2325,8 @@ define @fcmp_ugt_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ugt_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp ugt %va, %vb ret %vc @@ -2354,7 +2336,7 @@ ; CHECK-LABEL: fcmp_ugt_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v0, v16, fa0 +; CHECK-NEXT: vmfgt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2365,9 +2347,8 @@ define @fcmp_uge_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_uge_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v25, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v25, v8, v16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2380,7 +2361,7 @@ ; CHECK-LABEL: fcmp_uge_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2395,7 +2376,7 @@ ; CHECK-LABEL: fcmp_uge_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2409,9 +2390,8 @@ define @fcmp_uge_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_uge_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = fcmp uge %va, %vb ret %vc @@ -2421,7 +2401,7 @@ ; CHECK-LABEL: fcmp_uge_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v0, v16, fa0 +; CHECK-NEXT: vmfge.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2432,9 +2412,8 @@ define @fcmp_ult_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ult_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v25, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v25, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2447,7 +2426,7 @@ ; CHECK-LABEL: fcmp_ult_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfge.vf v25, v16, fa0 +; CHECK-NEXT: vmfge.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2462,7 +2441,7 @@ ; CHECK-LABEL: fcmp_ult_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v25, v16, fa0 +; CHECK-NEXT: vmfle.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2476,9 +2455,8 @@ define @fcmp_ult_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ult_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ult %va, %vb ret %vc @@ -2488,7 +2466,7 @@ ; CHECK-LABEL: fcmp_ult_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v0, v16, fa0 +; CHECK-NEXT: vmflt.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2499,9 +2477,8 @@ define @fcmp_ule_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_ule_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmflt.vv v25, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmflt.vv v25, v16, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2514,7 +2491,7 @@ ; CHECK-LABEL: fcmp_ule_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfgt.vf v25, v16, fa0 +; CHECK-NEXT: vmfgt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2529,7 +2506,7 @@ ; CHECK-LABEL: fcmp_ule_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmflt.vf v25, v16, fa0 +; CHECK-NEXT: vmflt.vf v25, v8, fa0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmset.m v26 ; CHECK-NEXT: vmxor.mm v0, v25, v26 @@ -2543,9 +2520,8 @@ define @fcmp_ule_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_ule_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfle.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp ule %va, %vb ret %vc @@ -2555,7 +2531,7 @@ ; CHECK-LABEL: fcmp_ule_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfle.vf v0, v16, fa0 +; CHECK-NEXT: vmfle.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2566,9 +2542,8 @@ define @fcmp_une_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_une_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfne.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -2578,7 +2553,7 @@ ; CHECK-LABEL: fcmp_une_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2590,7 +2565,7 @@ ; CHECK-LABEL: fcmp_une_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2601,9 +2576,8 @@ define @fcmp_une_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_une_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmfne.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = fcmp une %va, %vb ret %vc @@ -2613,7 +2587,7 @@ ; CHECK-LABEL: fcmp_une_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmfne.vf v0, v16, fa0 +; CHECK-NEXT: vmfne.vf v0, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2624,12 +2598,11 @@ define @fcmp_uno_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: fcmp_uno_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmfne.vv v25, v16, v16 ; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret %vc = fcmp uno %va, %vb ret %vc @@ -2639,9 +2612,9 @@ ; CHECK-LABEL: fcmp_uno_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfne.vf v25, v8, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfne.vf v25, v16, fa0 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret @@ -2655,9 +2628,9 @@ ; CHECK-LABEL: fcmp_uno_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfne.vf v25, v8, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfne.vf v25, v16, fa0 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v25, v26 ; CHECK-NEXT: ret @@ -2670,12 +2643,11 @@ define @fcmp_uno_vv_nxv8f64_nonans( %va, %vb) #0 { ; CHECK-LABEL: fcmp_uno_vv_nxv8f64_nonans: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vmfne.vv v25, v16, v16 ; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmor.mm v0, v25, v26 +; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret %vc = fcmp uno %va, %vb ret %vc @@ -2685,9 +2657,9 @@ ; CHECK-LABEL: fcmp_uno_vf_nxv8f64_nonans: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: vmfne.vf v25, v8, fa0 -; CHECK-NEXT: vmfne.vv v26, v16, v16 +; CHECK-NEXT: vfmv.v.f v16, fa0 +; CHECK-NEXT: vmfne.vf v25, v16, fa0 +; CHECK-NEXT: vmfne.vv v26, v8, v8 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmor.mm v0, v26, v25 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: icmp_eq_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vv v0, v16, v17 +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc @@ -19,7 +19,7 @@ ; CHECK-LABEL: icmp_eq_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vx v0, v16, a0 +; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -32,7 +32,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmseq.vv v0, v25, v16 +; CHECK-NEXT: vmseq.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -44,7 +44,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i8 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -56,7 +56,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK-LABEL: icmp_eq_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -80,7 +80,7 @@ ; CHECK-LABEL: icmp_ne_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsne.vv v0, v16, v17 +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc @@ -90,7 +90,7 @@ ; CHECK-LABEL: icmp_ne_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsne.vx v0, v16, a0 +; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -103,7 +103,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vv v0, v25, v16 +; CHECK-NEXT: vmsne.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -115,7 +115,7 @@ ; CHECK-LABEL: icmp_ne_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsne.vi v0, v16, 5 +; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -127,7 +127,7 @@ ; CHECK-LABEL: icmp_ugt_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v17, v16 +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc @@ -137,7 +137,7 @@ ; CHECK-LABEL: icmp_ugt_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgtu.vx v0, v16, a0 +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -150,7 +150,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsltu.vv v0, v16, v25 +; CHECK-NEXT: vmsltu.vv v0, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -162,7 +162,7 @@ ; CHECK-LABEL: icmp_ugt_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, 5 +; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -174,7 +174,7 @@ ; CHECK-LABEL: icmp_uge_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v17, v16 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc @@ -185,7 +185,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -198,7 +198,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v16, v25 +; CHECK-NEXT: vmsleu.vv v0, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -211,7 +211,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, -16 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +224,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 15 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -236,7 +236,7 @@ ; CHECK-LABEL: icmp_uge_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 15 +; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -261,7 +261,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 1 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +274,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, -15 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -288,7 +288,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +300,7 @@ ; CHECK-LABEL: icmp_ult_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v16, v17 +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc @@ -310,7 +310,7 @@ ; CHECK-LABEL: icmp_ult_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -323,7 +323,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsltu.vv v0, v25, v16 +; CHECK-NEXT: vmsltu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -336,7 +336,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -349,7 +349,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -361,7 +361,7 @@ ; CHECK-LABEL: icmp_ult_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, -15 +; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -385,7 +385,7 @@ ; CHECK-LABEL: icmp_ult_vi_nxv8i8_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -398,7 +398,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -410,7 +410,7 @@ ; CHECK-LABEL: icmp_ule_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v16, v17 +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc @@ -420,7 +420,7 @@ ; CHECK-LABEL: icmp_ule_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vx v0, v16, a0 +; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -433,7 +433,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -445,7 +445,7 @@ ; CHECK-LABEL: icmp_ule_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 5 +; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -457,7 +457,7 @@ ; CHECK-LABEL: icmp_sgt_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vv v0, v17, v16 +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc @@ -467,7 +467,7 @@ ; CHECK-LABEL: icmp_sgt_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgt.vx v0, v16, a0 +; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -480,7 +480,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmslt.vv v0, v16, v25 +; CHECK-NEXT: vmslt.vv v0, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -492,7 +492,7 @@ ; CHECK-LABEL: icmp_sgt_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, 5 +; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -504,7 +504,7 @@ ; CHECK-LABEL: icmp_sge_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vv v0, v17, v16 +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc @@ -515,7 +515,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -528,7 +528,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v16, v25 +; CHECK-NEXT: vmsle.vv v0, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -541,7 +541,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, -16 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -554,7 +554,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, -15 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -566,7 +566,7 @@ ; CHECK-LABEL: icmp_sge_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, -15 +; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -579,7 +579,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -593,7 +593,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -605,7 +605,7 @@ ; CHECK-LABEL: icmp_slt_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vv v0, v16, v17 +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc @@ -615,7 +615,7 @@ ; CHECK-LABEL: icmp_slt_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -628,7 +628,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmslt.vv v0, v25, v16 +; CHECK-NEXT: vmslt.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -641,7 +641,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -654,7 +654,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -666,7 +666,7 @@ ; CHECK-LABEL: icmp_slt_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, -15 +; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -678,7 +678,7 @@ ; CHECK-LABEL: icmp_slt_vi_nxv8i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, zero +; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: ret %head = insertelement undef, i8 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -691,7 +691,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -703,7 +703,7 @@ ; CHECK-LABEL: icmp_sle_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vv v0, v16, v17 +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc @@ -713,7 +713,7 @@ ; CHECK-LABEL: icmp_sle_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vx v0, v16, a0 +; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -726,7 +726,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -738,7 +738,7 @@ ; CHECK-LABEL: icmp_sle_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, 5 +; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -750,7 +750,7 @@ ; CHECK-LABEL: icmp_eq_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vv v0, v16, v18 +; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc @@ -760,7 +760,7 @@ ; CHECK-LABEL: icmp_eq_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vx v0, v16, a0 +; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -773,7 +773,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmseq.vv v0, v26, v16 +; CHECK-NEXT: vmseq.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -785,7 +785,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i16 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -797,7 +797,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -809,7 +809,7 @@ ; CHECK-LABEL: icmp_eq_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -821,7 +821,7 @@ ; CHECK-LABEL: icmp_ne_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsne.vv v0, v16, v18 +; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc @@ -831,7 +831,7 @@ ; CHECK-LABEL: icmp_ne_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsne.vx v0, v16, a0 +; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -844,7 +844,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vv v0, v26, v16 +; CHECK-NEXT: vmsne.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -856,7 +856,7 @@ ; CHECK-LABEL: icmp_ne_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsne.vi v0, v16, 5 +; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -868,7 +868,7 @@ ; CHECK-LABEL: icmp_ugt_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v18, v16 +; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc @@ -878,7 +878,7 @@ ; CHECK-LABEL: icmp_ugt_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgtu.vx v0, v16, a0 +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -891,7 +891,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsltu.vv v0, v16, v26 +; CHECK-NEXT: vmsltu.vv v0, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -903,7 +903,7 @@ ; CHECK-LABEL: icmp_ugt_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, 5 +; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -915,7 +915,7 @@ ; CHECK-LABEL: icmp_uge_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v18, v16 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc @@ -926,7 +926,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -939,7 +939,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v16, v26 +; CHECK-NEXT: vmsleu.vv v0, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -952,7 +952,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, -16 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -965,7 +965,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 15 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -977,7 +977,7 @@ ; CHECK-LABEL: icmp_uge_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 15 +; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1002,7 +1002,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 1 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1015,7 +1015,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, -15 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1029,7 +1029,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1041,7 +1041,7 @@ ; CHECK-LABEL: icmp_ult_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v16, v18 +; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc @@ -1051,7 +1051,7 @@ ; CHECK-LABEL: icmp_ult_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1064,7 +1064,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsltu.vv v0, v26, v16 +; CHECK-NEXT: vmsltu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1077,7 +1077,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1090,7 +1090,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1102,7 +1102,7 @@ ; CHECK-LABEL: icmp_ult_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, -15 +; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1126,7 +1126,7 @@ ; CHECK-LABEL: icmp_ult_vi_nxv8i16_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1139,7 +1139,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1151,7 +1151,7 @@ ; CHECK-LABEL: icmp_ule_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v16, v18 +; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc @@ -1161,7 +1161,7 @@ ; CHECK-LABEL: icmp_ule_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vx v0, v16, a0 +; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1174,7 +1174,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1186,7 +1186,7 @@ ; CHECK-LABEL: icmp_ule_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 5 +; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1198,7 +1198,7 @@ ; CHECK-LABEL: icmp_sgt_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vv v0, v18, v16 +; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc @@ -1208,7 +1208,7 @@ ; CHECK-LABEL: icmp_sgt_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgt.vx v0, v16, a0 +; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1221,7 +1221,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmslt.vv v0, v16, v26 +; CHECK-NEXT: vmslt.vv v0, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1233,7 +1233,7 @@ ; CHECK-LABEL: icmp_sgt_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, 5 +; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1245,7 +1245,7 @@ ; CHECK-LABEL: icmp_sge_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vv v0, v18, v16 +; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc @@ -1256,7 +1256,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1269,7 +1269,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v16, v26 +; CHECK-NEXT: vmsle.vv v0, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1282,7 +1282,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, -16 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1295,7 +1295,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, -15 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1307,7 +1307,7 @@ ; CHECK-LABEL: icmp_sge_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, -15 +; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1320,7 +1320,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1334,7 +1334,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1346,7 +1346,7 @@ ; CHECK-LABEL: icmp_slt_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vv v0, v16, v18 +; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc @@ -1356,7 +1356,7 @@ ; CHECK-LABEL: icmp_slt_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1369,7 +1369,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmslt.vv v0, v26, v16 +; CHECK-NEXT: vmslt.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1382,7 +1382,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1395,7 +1395,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1407,7 +1407,7 @@ ; CHECK-LABEL: icmp_slt_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, -15 +; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1419,7 +1419,7 @@ ; CHECK-LABEL: icmp_slt_vi_nxv8i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, zero +; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: ret %head = insertelement undef, i16 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1432,7 +1432,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1444,7 +1444,7 @@ ; CHECK-LABEL: icmp_sle_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vv v0, v16, v18 +; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc @@ -1454,7 +1454,7 @@ ; CHECK-LABEL: icmp_sle_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vx v0, v16, a0 +; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1467,7 +1467,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1479,7 +1479,7 @@ ; CHECK-LABEL: icmp_sle_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, 5 +; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1491,7 +1491,7 @@ ; CHECK-LABEL: icmp_eq_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vv v0, v16, v20 +; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc @@ -1501,7 +1501,7 @@ ; CHECK-LABEL: icmp_eq_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vx v0, v16, a0 +; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1514,7 +1514,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmseq.vv v0, v28, v16 +; CHECK-NEXT: vmseq.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1526,7 +1526,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i32 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1538,7 +1538,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1550,7 +1550,7 @@ ; CHECK-LABEL: icmp_eq_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1562,7 +1562,7 @@ ; CHECK-LABEL: icmp_ne_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsne.vv v0, v16, v20 +; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc @@ -1572,7 +1572,7 @@ ; CHECK-LABEL: icmp_ne_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsne.vx v0, v16, a0 +; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1585,7 +1585,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsne.vv v0, v28, v16 +; CHECK-NEXT: vmsne.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1597,7 +1597,7 @@ ; CHECK-LABEL: icmp_ne_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsne.vi v0, v16, 5 +; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1609,7 +1609,7 @@ ; CHECK-LABEL: icmp_ugt_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v20, v16 +; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc @@ -1619,7 +1619,7 @@ ; CHECK-LABEL: icmp_ugt_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgtu.vx v0, v16, a0 +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1632,7 +1632,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsltu.vv v0, v16, v28 +; CHECK-NEXT: vmsltu.vv v0, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1644,7 +1644,7 @@ ; CHECK-LABEL: icmp_ugt_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, 5 +; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1656,7 +1656,7 @@ ; CHECK-LABEL: icmp_uge_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v20, v16 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc @@ -1667,7 +1667,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1680,7 +1680,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v16, v28 +; CHECK-NEXT: vmsleu.vv v0, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1693,7 +1693,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, -16 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1706,7 +1706,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 15 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1718,7 +1718,7 @@ ; CHECK-LABEL: icmp_uge_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 15 +; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1743,7 +1743,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 1 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1756,7 +1756,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, -15 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1770,7 +1770,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1782,7 +1782,7 @@ ; CHECK-LABEL: icmp_ult_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v16, v20 +; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc @@ -1792,7 +1792,7 @@ ; CHECK-LABEL: icmp_ult_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1805,7 +1805,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsltu.vv v0, v28, v16 +; CHECK-NEXT: vmsltu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1818,7 +1818,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1831,7 +1831,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1843,7 +1843,7 @@ ; CHECK-LABEL: icmp_ult_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, -15 +; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1867,7 +1867,7 @@ ; CHECK-LABEL: icmp_ult_vi_nxv8i32_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1880,7 +1880,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1892,7 +1892,7 @@ ; CHECK-LABEL: icmp_ule_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v16, v20 +; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc @@ -1902,7 +1902,7 @@ ; CHECK-LABEL: icmp_ule_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vx v0, v16, a0 +; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1915,7 +1915,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1927,7 +1927,7 @@ ; CHECK-LABEL: icmp_ule_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 5 +; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1939,7 +1939,7 @@ ; CHECK-LABEL: icmp_sgt_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vv v0, v20, v16 +; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc @@ -1949,7 +1949,7 @@ ; CHECK-LABEL: icmp_sgt_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgt.vx v0, v16, a0 +; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1962,7 +1962,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmslt.vv v0, v16, v28 +; CHECK-NEXT: vmslt.vv v0, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1974,7 +1974,7 @@ ; CHECK-LABEL: icmp_sgt_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, 5 +; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1986,7 +1986,7 @@ ; CHECK-LABEL: icmp_sge_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vv v0, v20, v16 +; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc @@ -1997,7 +1997,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2010,7 +2010,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v16, v28 +; CHECK-NEXT: vmsle.vv v0, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2023,7 +2023,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, -16 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2036,7 +2036,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, -15 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2048,7 +2048,7 @@ ; CHECK-LABEL: icmp_sge_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, -15 +; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2061,7 +2061,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2075,7 +2075,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2087,7 +2087,7 @@ ; CHECK-LABEL: icmp_slt_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vv v0, v16, v20 +; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc @@ -2097,7 +2097,7 @@ ; CHECK-LABEL: icmp_slt_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2110,7 +2110,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmslt.vv v0, v28, v16 +; CHECK-NEXT: vmslt.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2123,7 +2123,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2136,7 +2136,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2148,7 +2148,7 @@ ; CHECK-LABEL: icmp_slt_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, -15 +; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2160,7 +2160,7 @@ ; CHECK-LABEL: icmp_slt_vi_nxv8i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, zero +; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: ret %head = insertelement undef, i32 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2173,7 +2173,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2185,7 +2185,7 @@ ; CHECK-LABEL: icmp_sle_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vv v0, v16, v20 +; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc @@ -2195,7 +2195,7 @@ ; CHECK-LABEL: icmp_sle_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vx v0, v16, a0 +; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2208,7 +2208,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2220,7 +2220,7 @@ ; CHECK-LABEL: icmp_sle_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, 5 +; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2231,9 +2231,8 @@ define @icmp_eq_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmseq.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc @@ -2243,14 +2242,14 @@ ; CHECK-LABEL: icmp_eq_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmseq.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmseq.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2262,14 +2261,14 @@ ; CHECK-LABEL: icmp_eq_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmseq.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmseq.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2281,7 +2280,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i64 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2293,7 +2292,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2305,7 +2304,7 @@ ; CHECK-LABEL: icmp_eq_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2316,9 +2315,8 @@ define @icmp_ne_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ne_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsne.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc @@ -2328,14 +2326,14 @@ ; CHECK-LABEL: icmp_ne_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsne.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsne.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2347,14 +2345,14 @@ ; CHECK-LABEL: icmp_ne_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsne.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsne.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2366,7 +2364,7 @@ ; CHECK-LABEL: icmp_ne_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsne.vi v0, v16, 5 +; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2377,9 +2375,8 @@ define @icmp_ugt_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ugt_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsltu.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc @@ -2389,14 +2386,14 @@ ; CHECK-LABEL: icmp_ugt_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsltu.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsltu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2408,14 +2405,14 @@ ; CHECK-LABEL: icmp_ugt_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsltu.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsltu.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2427,7 +2424,7 @@ ; CHECK-LABEL: icmp_ugt_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, 5 +; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2438,9 +2435,8 @@ define @icmp_uge_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_uge_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc @@ -2450,14 +2446,14 @@ ; CHECK-LABEL: icmp_uge_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2469,14 +2465,14 @@ ; CHECK-LABEL: icmp_uge_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsleu.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsleu.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2488,8 +2484,8 @@ ; CHECK-LABEL: icmp_uge_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, -16 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, -16 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2501,8 +2497,8 @@ ; CHECK-LABEL: icmp_uge_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, 15 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, 15 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2514,7 +2510,7 @@ ; CHECK-LABEL: icmp_uge_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 15 +; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2538,8 +2534,8 @@ ; CHECK-LABEL: icmp_uge_vi_nxv8i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, 1 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, 1 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2551,8 +2547,8 @@ ; CHECK-LABEL: icmp_uge_vi_nxv8i64_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, -15 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, -15 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2565,8 +2561,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2577,9 +2573,8 @@ define @icmp_ult_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ult_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsltu.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc @@ -2589,14 +2584,14 @@ ; CHECK-LABEL: icmp_ult_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsltu.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsltu.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2608,14 +2603,14 @@ ; CHECK-LABEL: icmp_ult_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsltu.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsltu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2628,7 +2623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2641,7 +2636,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2653,7 +2648,7 @@ ; CHECK-LABEL: icmp_ult_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, -15 +; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2677,7 +2672,7 @@ ; CHECK-LABEL: icmp_ult_vi_nxv8i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2690,7 +2685,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2701,9 +2696,8 @@ define @icmp_ule_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ule_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsleu.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc @@ -2713,14 +2707,14 @@ ; CHECK-LABEL: icmp_ule_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsleu.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsleu.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2732,14 +2726,14 @@ ; CHECK-LABEL: icmp_ule_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2751,7 +2745,7 @@ ; CHECK-LABEL: icmp_ule_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 5 +; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2762,9 +2756,8 @@ define @icmp_sgt_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_sgt_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmslt.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmslt.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc @@ -2774,14 +2767,14 @@ ; CHECK-LABEL: icmp_sgt_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmslt.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmslt.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2793,14 +2786,14 @@ ; CHECK-LABEL: icmp_sgt_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmslt.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmslt.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2812,7 +2805,7 @@ ; CHECK-LABEL: icmp_sgt_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, 5 +; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2823,9 +2816,8 @@ define @icmp_sge_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_sge_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc @@ -2835,14 +2827,14 @@ ; CHECK-LABEL: icmp_sge_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2854,14 +2846,14 @@ ; CHECK-LABEL: icmp_sge_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsle.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsle.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2873,8 +2865,8 @@ ; CHECK-LABEL: icmp_sge_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, -16 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, -16 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2886,8 +2878,8 @@ ; CHECK-LABEL: icmp_sge_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, -15 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, -15 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2899,7 +2891,7 @@ ; CHECK-LABEL: icmp_sge_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, -15 +; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2911,8 +2903,8 @@ ; CHECK-LABEL: icmp_sge_vi_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, 0 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2925,8 +2917,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2937,9 +2929,8 @@ define @icmp_slt_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_slt_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmslt.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc @@ -2949,14 +2940,14 @@ ; CHECK-LABEL: icmp_slt_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmslt.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmslt.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2968,14 +2959,14 @@ ; CHECK-LABEL: icmp_slt_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmslt.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmslt.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2988,7 +2979,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3001,7 +2992,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3013,7 +3004,7 @@ ; CHECK-LABEL: icmp_slt_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, -15 +; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3025,7 +3016,7 @@ ; CHECK-LABEL: icmp_slt_vi_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, zero +; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: ret %head = insertelement undef, i64 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3038,7 +3029,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3049,9 +3040,8 @@ define @icmp_sle_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_sle_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsle.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc @@ -3061,14 +3051,14 @@ ; CHECK-LABEL: icmp_sle_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsle.vv v0, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsle.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3080,14 +3070,14 @@ ; CHECK-LABEL: icmp_sle_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -3099,7 +3089,7 @@ ; CHECK-LABEL: icmp_sle_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, 5 +; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: icmp_eq_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vv v0, v16, v17 +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc @@ -19,7 +19,7 @@ ; CHECK-LABEL: icmp_eq_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vx v0, v16, a0 +; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -32,7 +32,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmseq.vv v0, v25, v16 +; CHECK-NEXT: vmseq.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -44,7 +44,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i8 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -56,7 +56,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK-LABEL: icmp_eq_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -80,7 +80,7 @@ ; CHECK-LABEL: icmp_ne_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsne.vv v0, v16, v17 +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc @@ -90,7 +90,7 @@ ; CHECK-LABEL: icmp_ne_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsne.vx v0, v16, a0 +; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -103,7 +103,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsne.vv v0, v25, v16 +; CHECK-NEXT: vmsne.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -115,7 +115,7 @@ ; CHECK-LABEL: icmp_ne_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsne.vi v0, v16, 5 +; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -127,7 +127,7 @@ ; CHECK-LABEL: icmp_ugt_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v17, v16 +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc @@ -137,7 +137,7 @@ ; CHECK-LABEL: icmp_ugt_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgtu.vx v0, v16, a0 +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -150,7 +150,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsltu.vv v0, v16, v25 +; CHECK-NEXT: vmsltu.vv v0, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -162,7 +162,7 @@ ; CHECK-LABEL: icmp_ugt_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, 5 +; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -174,7 +174,7 @@ ; CHECK-LABEL: icmp_uge_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v17, v16 +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc @@ -185,7 +185,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -198,7 +198,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v16, v25 +; CHECK-NEXT: vmsleu.vv v0, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -211,7 +211,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, -16 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +224,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 15 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -236,7 +236,7 @@ ; CHECK-LABEL: icmp_uge_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 15 +; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -261,7 +261,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 1 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +274,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, -15 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -288,7 +288,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +300,7 @@ ; CHECK-LABEL: icmp_ult_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v16, v17 +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc @@ -310,7 +310,7 @@ ; CHECK-LABEL: icmp_ult_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -323,7 +323,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsltu.vv v0, v25, v16 +; CHECK-NEXT: vmsltu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -336,7 +336,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -349,7 +349,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -361,7 +361,7 @@ ; CHECK-LABEL: icmp_ult_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, -15 +; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -385,7 +385,7 @@ ; CHECK-LABEL: icmp_ult_vi_nxv8i8_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -398,7 +398,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -410,7 +410,7 @@ ; CHECK-LABEL: icmp_ule_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v16, v17 +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc @@ -420,7 +420,7 @@ ; CHECK-LABEL: icmp_ule_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vx v0, v16, a0 +; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -433,7 +433,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsleu.vv v0, v25, v16 +; CHECK-NEXT: vmsleu.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -445,7 +445,7 @@ ; CHECK-LABEL: icmp_ule_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 5 +; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -457,7 +457,7 @@ ; CHECK-LABEL: icmp_sgt_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vv v0, v17, v16 +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc @@ -467,7 +467,7 @@ ; CHECK-LABEL: icmp_sgt_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgt.vx v0, v16, a0 +; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -480,7 +480,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmslt.vv v0, v16, v25 +; CHECK-NEXT: vmslt.vv v0, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -492,7 +492,7 @@ ; CHECK-LABEL: icmp_sgt_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, 5 +; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -504,7 +504,7 @@ ; CHECK-LABEL: icmp_sge_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vv v0, v17, v16 +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc @@ -515,7 +515,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -528,7 +528,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v16, v25 +; CHECK-NEXT: vmsle.vv v0, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -541,7 +541,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, -16 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -554,7 +554,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, -15 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -566,7 +566,7 @@ ; CHECK-LABEL: icmp_sge_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, -15 +; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -579,7 +579,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.i v25, 0 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -593,7 +593,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -605,7 +605,7 @@ ; CHECK-LABEL: icmp_slt_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vv v0, v16, v17 +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc @@ -615,7 +615,7 @@ ; CHECK-LABEL: icmp_slt_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -628,7 +628,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmslt.vv v0, v25, v16 +; CHECK-NEXT: vmslt.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -641,7 +641,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -654,7 +654,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -666,7 +666,7 @@ ; CHECK-LABEL: icmp_slt_iv_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, -15 +; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i8 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -678,7 +678,7 @@ ; CHECK-LABEL: icmp_slt_vi_nxv8i8_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, zero +; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: ret %head = insertelement undef, i8 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -691,7 +691,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -703,7 +703,7 @@ ; CHECK-LABEL: icmp_sle_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vv v0, v16, v17 +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc @@ -713,7 +713,7 @@ ; CHECK-LABEL: icmp_sle_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vx v0, v16, a0 +; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -726,7 +726,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmv.v.x v25, a0 -; CHECK-NEXT: vmsle.vv v0, v25, v16 +; CHECK-NEXT: vmsle.vv v0, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -738,7 +738,7 @@ ; CHECK-LABEL: icmp_sle_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, 5 +; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i8 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -750,7 +750,7 @@ ; CHECK-LABEL: icmp_eq_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vv v0, v16, v18 +; CHECK-NEXT: vmseq.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc @@ -760,7 +760,7 @@ ; CHECK-LABEL: icmp_eq_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vx v0, v16, a0 +; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -773,7 +773,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmseq.vv v0, v26, v16 +; CHECK-NEXT: vmseq.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -785,7 +785,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i16 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -797,7 +797,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -809,7 +809,7 @@ ; CHECK-LABEL: icmp_eq_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -821,7 +821,7 @@ ; CHECK-LABEL: icmp_ne_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsne.vv v0, v16, v18 +; CHECK-NEXT: vmsne.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc @@ -831,7 +831,7 @@ ; CHECK-LABEL: icmp_ne_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsne.vx v0, v16, a0 +; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -844,7 +844,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsne.vv v0, v26, v16 +; CHECK-NEXT: vmsne.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -856,7 +856,7 @@ ; CHECK-LABEL: icmp_ne_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsne.vi v0, v16, 5 +; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -868,7 +868,7 @@ ; CHECK-LABEL: icmp_ugt_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v18, v16 +; CHECK-NEXT: vmsltu.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc @@ -878,7 +878,7 @@ ; CHECK-LABEL: icmp_ugt_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgtu.vx v0, v16, a0 +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -891,7 +891,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsltu.vv v0, v16, v26 +; CHECK-NEXT: vmsltu.vv v0, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -903,7 +903,7 @@ ; CHECK-LABEL: icmp_ugt_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, 5 +; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -915,7 +915,7 @@ ; CHECK-LABEL: icmp_uge_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v18, v16 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc @@ -926,7 +926,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -939,7 +939,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v16, v26 +; CHECK-NEXT: vmsleu.vv v0, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -952,7 +952,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, -16 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -965,7 +965,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 15 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -977,7 +977,7 @@ ; CHECK-LABEL: icmp_uge_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 15 +; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1002,7 +1002,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 1 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1015,7 +1015,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, -15 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1029,7 +1029,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1041,7 +1041,7 @@ ; CHECK-LABEL: icmp_ult_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v16, v18 +; CHECK-NEXT: vmsltu.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc @@ -1051,7 +1051,7 @@ ; CHECK-LABEL: icmp_ult_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1064,7 +1064,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsltu.vv v0, v26, v16 +; CHECK-NEXT: vmsltu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1077,7 +1077,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1090,7 +1090,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1102,7 +1102,7 @@ ; CHECK-LABEL: icmp_ult_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, -15 +; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1126,7 +1126,7 @@ ; CHECK-LABEL: icmp_ult_vi_nxv8i16_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1139,7 +1139,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1151,7 +1151,7 @@ ; CHECK-LABEL: icmp_ule_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v16, v18 +; CHECK-NEXT: vmsleu.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc @@ -1161,7 +1161,7 @@ ; CHECK-LABEL: icmp_ule_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vx v0, v16, a0 +; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1174,7 +1174,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsleu.vv v0, v26, v16 +; CHECK-NEXT: vmsleu.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1186,7 +1186,7 @@ ; CHECK-LABEL: icmp_ule_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 5 +; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1198,7 +1198,7 @@ ; CHECK-LABEL: icmp_sgt_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vv v0, v18, v16 +; CHECK-NEXT: vmslt.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc @@ -1208,7 +1208,7 @@ ; CHECK-LABEL: icmp_sgt_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgt.vx v0, v16, a0 +; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1221,7 +1221,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmslt.vv v0, v16, v26 +; CHECK-NEXT: vmslt.vv v0, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1233,7 +1233,7 @@ ; CHECK-LABEL: icmp_sgt_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, 5 +; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1245,7 +1245,7 @@ ; CHECK-LABEL: icmp_sge_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vv v0, v18, v16 +; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc @@ -1256,7 +1256,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1269,7 +1269,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v16, v26 +; CHECK-NEXT: vmsle.vv v0, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1282,7 +1282,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, -16 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1295,7 +1295,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, -15 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1307,7 +1307,7 @@ ; CHECK-LABEL: icmp_sge_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, -15 +; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1320,7 +1320,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.i v26, 0 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1334,7 +1334,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1346,7 +1346,7 @@ ; CHECK-LABEL: icmp_slt_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vv v0, v16, v18 +; CHECK-NEXT: vmslt.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc @@ -1356,7 +1356,7 @@ ; CHECK-LABEL: icmp_slt_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1369,7 +1369,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmslt.vv v0, v26, v16 +; CHECK-NEXT: vmslt.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1382,7 +1382,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1395,7 +1395,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1407,7 +1407,7 @@ ; CHECK-LABEL: icmp_slt_iv_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, -15 +; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i16 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1419,7 +1419,7 @@ ; CHECK-LABEL: icmp_slt_vi_nxv8i16_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, zero +; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: ret %head = insertelement undef, i16 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1432,7 +1432,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1444,7 +1444,7 @@ ; CHECK-LABEL: icmp_sle_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vv v0, v16, v18 +; CHECK-NEXT: vmsle.vv v0, v8, v10 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc @@ -1454,7 +1454,7 @@ ; CHECK-LABEL: icmp_sle_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vx v0, v16, a0 +; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1467,7 +1467,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmv.v.x v26, a0 -; CHECK-NEXT: vmsle.vv v0, v26, v16 +; CHECK-NEXT: vmsle.vv v0, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1479,7 +1479,7 @@ ; CHECK-LABEL: icmp_sle_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, 5 +; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i16 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1491,7 +1491,7 @@ ; CHECK-LABEL: icmp_eq_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vv v0, v16, v20 +; CHECK-NEXT: vmseq.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc @@ -1501,7 +1501,7 @@ ; CHECK-LABEL: icmp_eq_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vx v0, v16, a0 +; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1514,7 +1514,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmseq.vv v0, v28, v16 +; CHECK-NEXT: vmseq.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1526,7 +1526,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i32 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1538,7 +1538,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1550,7 +1550,7 @@ ; CHECK-LABEL: icmp_eq_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1562,7 +1562,7 @@ ; CHECK-LABEL: icmp_ne_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsne.vv v0, v16, v20 +; CHECK-NEXT: vmsne.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc @@ -1572,7 +1572,7 @@ ; CHECK-LABEL: icmp_ne_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsne.vx v0, v16, a0 +; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1585,7 +1585,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsne.vv v0, v28, v16 +; CHECK-NEXT: vmsne.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1597,7 +1597,7 @@ ; CHECK-LABEL: icmp_ne_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsne.vi v0, v16, 5 +; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1609,7 +1609,7 @@ ; CHECK-LABEL: icmp_ugt_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v20, v16 +; CHECK-NEXT: vmsltu.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc @@ -1619,7 +1619,7 @@ ; CHECK-LABEL: icmp_ugt_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgtu.vx v0, v16, a0 +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1632,7 +1632,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsltu.vv v0, v16, v28 +; CHECK-NEXT: vmsltu.vv v0, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1644,7 +1644,7 @@ ; CHECK-LABEL: icmp_ugt_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, 5 +; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1656,7 +1656,7 @@ ; CHECK-LABEL: icmp_uge_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v20, v16 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc @@ -1667,7 +1667,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1680,7 +1680,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v16, v28 +; CHECK-NEXT: vmsleu.vv v0, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1693,7 +1693,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, -16 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1706,7 +1706,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 15 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1718,7 +1718,7 @@ ; CHECK-LABEL: icmp_uge_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 15 +; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1743,7 +1743,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 1 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1756,7 +1756,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, -15 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1770,7 +1770,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1782,7 +1782,7 @@ ; CHECK-LABEL: icmp_ult_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vv v0, v16, v20 +; CHECK-NEXT: vmsltu.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc @@ -1792,7 +1792,7 @@ ; CHECK-LABEL: icmp_ult_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1805,7 +1805,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsltu.vv v0, v28, v16 +; CHECK-NEXT: vmsltu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1818,7 +1818,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1831,7 +1831,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1843,7 +1843,7 @@ ; CHECK-LABEL: icmp_ult_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, -15 +; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1867,7 +1867,7 @@ ; CHECK-LABEL: icmp_ult_vi_nxv8i32_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1880,7 +1880,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1892,7 +1892,7 @@ ; CHECK-LABEL: icmp_ule_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vv v0, v16, v20 +; CHECK-NEXT: vmsleu.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc @@ -1902,7 +1902,7 @@ ; CHECK-LABEL: icmp_ule_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vx v0, v16, a0 +; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1915,7 +1915,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsleu.vv v0, v28, v16 +; CHECK-NEXT: vmsleu.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1927,7 +1927,7 @@ ; CHECK-LABEL: icmp_ule_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 5 +; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1939,7 +1939,7 @@ ; CHECK-LABEL: icmp_sgt_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vv v0, v20, v16 +; CHECK-NEXT: vmslt.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc @@ -1949,7 +1949,7 @@ ; CHECK-LABEL: icmp_sgt_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgt.vx v0, v16, a0 +; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1962,7 +1962,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmslt.vv v0, v16, v28 +; CHECK-NEXT: vmslt.vv v0, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1974,7 +1974,7 @@ ; CHECK-LABEL: icmp_sgt_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, 5 +; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1986,7 +1986,7 @@ ; CHECK-LABEL: icmp_sge_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vv v0, v20, v16 +; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc @@ -1997,7 +1997,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2010,7 +2010,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v16, v28 +; CHECK-NEXT: vmsle.vv v0, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2023,7 +2023,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, -16 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2036,7 +2036,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, -15 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2048,7 +2048,7 @@ ; CHECK-LABEL: icmp_sge_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, -15 +; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2061,7 +2061,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.i v28, 0 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2075,7 +2075,7 @@ ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2087,7 +2087,7 @@ ; CHECK-LABEL: icmp_slt_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vv v0, v16, v20 +; CHECK-NEXT: vmslt.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc @@ -2097,7 +2097,7 @@ ; CHECK-LABEL: icmp_slt_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2110,7 +2110,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmslt.vv v0, v28, v16 +; CHECK-NEXT: vmslt.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2123,7 +2123,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2136,7 +2136,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2148,7 +2148,7 @@ ; CHECK-LABEL: icmp_slt_iv_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, -15 +; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i32 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2160,7 +2160,7 @@ ; CHECK-LABEL: icmp_slt_vi_nxv8i32_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, zero +; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: ret %head = insertelement undef, i32 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2173,7 +2173,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2185,7 +2185,7 @@ ; CHECK-LABEL: icmp_sle_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vv v0, v16, v20 +; CHECK-NEXT: vmsle.vv v0, v8, v12 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc @@ -2195,7 +2195,7 @@ ; CHECK-LABEL: icmp_sle_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vx v0, v16, a0 +; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2208,7 +2208,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmv.v.x v28, a0 -; CHECK-NEXT: vmsle.vv v0, v28, v16 +; CHECK-NEXT: vmsle.vv v0, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2220,7 +2220,7 @@ ; CHECK-LABEL: icmp_sle_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, 5 +; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i32 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2231,9 +2231,8 @@ define @icmp_eq_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_eq_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmseq.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp eq %va, %vb ret %vc @@ -2243,7 +2242,7 @@ ; CHECK-LABEL: icmp_eq_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmseq.vx v0, v16, a0 +; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2255,8 +2254,8 @@ ; CHECK-LABEL: icmp_eq_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmseq.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmseq.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2268,7 +2267,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i64 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2280,7 +2279,7 @@ ; CHECK-LABEL: icmp_eq_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2292,7 +2291,7 @@ ; CHECK-LABEL: icmp_eq_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 5 +; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2303,9 +2302,8 @@ define @icmp_ne_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ne_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsne.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp ne %va, %vb ret %vc @@ -2315,7 +2313,7 @@ ; CHECK-LABEL: icmp_ne_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsne.vx v0, v16, a0 +; CHECK-NEXT: vmsne.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2327,8 +2325,8 @@ ; CHECK-LABEL: icmp_ne_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsne.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsne.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2340,7 +2338,7 @@ ; CHECK-LABEL: icmp_ne_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsne.vi v0, v16, 5 +; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2351,9 +2349,8 @@ define @icmp_ugt_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ugt_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsltu.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp ugt %va, %vb ret %vc @@ -2363,7 +2360,7 @@ ; CHECK-LABEL: icmp_ugt_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgtu.vx v0, v16, a0 +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2375,8 +2372,8 @@ ; CHECK-LABEL: icmp_ugt_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsltu.vv v0, v16, v8 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsltu.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2388,7 +2385,7 @@ ; CHECK-LABEL: icmp_ugt_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, 5 +; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2399,9 +2396,8 @@ define @icmp_uge_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_uge_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp uge %va, %vb ret %vc @@ -2411,8 +2407,8 @@ ; CHECK-LABEL: icmp_uge_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2424,8 +2420,8 @@ ; CHECK-LABEL: icmp_uge_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsleu.vv v0, v16, v8 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsleu.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2437,8 +2433,8 @@ ; CHECK-LABEL: icmp_uge_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, -16 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, -16 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2450,8 +2446,8 @@ ; CHECK-LABEL: icmp_uge_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, 15 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, 15 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2463,7 +2459,7 @@ ; CHECK-LABEL: icmp_uge_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 15 +; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2487,8 +2483,8 @@ ; CHECK-LABEL: icmp_uge_vi_nxv8i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, 1 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, 1 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2500,8 +2496,8 @@ ; CHECK-LABEL: icmp_uge_vi_nxv8i64_4: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, -15 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, -15 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2514,8 +2510,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2526,9 +2522,8 @@ define @icmp_ult_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ult_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsltu.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp ult %va, %vb ret %vc @@ -2538,7 +2533,7 @@ ; CHECK-LABEL: icmp_ult_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2550,8 +2545,8 @@ ; CHECK-LABEL: icmp_ult_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsltu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsltu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2564,7 +2559,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2577,7 +2572,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2589,7 +2584,7 @@ ; CHECK-LABEL: icmp_ult_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgtu.vi v0, v16, -15 +; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2613,7 +2608,7 @@ ; CHECK-LABEL: icmp_ult_vi_nxv8i64_3: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmseq.vi v0, v16, 0 +; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2626,7 +2621,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsltu.vx v0, v16, a0 +; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2637,9 +2632,8 @@ define @icmp_ule_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_ule_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsleu.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp ule %va, %vb ret %vc @@ -2649,7 +2643,7 @@ ; CHECK-LABEL: icmp_ule_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsleu.vx v0, v16, a0 +; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2661,8 +2655,8 @@ ; CHECK-LABEL: icmp_ule_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsleu.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2674,7 +2668,7 @@ ; CHECK-LABEL: icmp_ule_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsleu.vi v0, v16, 5 +; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2685,9 +2679,8 @@ define @icmp_sgt_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_sgt_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmslt.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmslt.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp sgt %va, %vb ret %vc @@ -2697,7 +2690,7 @@ ; CHECK-LABEL: icmp_sgt_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgt.vx v0, v16, a0 +; CHECK-NEXT: vmsgt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2709,8 +2702,8 @@ ; CHECK-LABEL: icmp_sgt_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmslt.vv v0, v16, v8 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmslt.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2722,7 +2715,7 @@ ; CHECK-LABEL: icmp_sgt_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, 5 +; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2733,9 +2726,8 @@ define @icmp_sge_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_sge_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %vc = icmp sge %va, %vb ret %vc @@ -2745,8 +2737,8 @@ ; CHECK-LABEL: icmp_sge_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2758,8 +2750,8 @@ ; CHECK-LABEL: icmp_sge_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsle.vv v0, v16, v8 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsle.vv v0, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2771,8 +2763,8 @@ ; CHECK-LABEL: icmp_sge_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, -16 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, -16 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2784,8 +2776,8 @@ ; CHECK-LABEL: icmp_sge_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, -15 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, -15 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2797,7 +2789,7 @@ ; CHECK-LABEL: icmp_sge_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, -15 +; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2809,8 +2801,8 @@ ; CHECK-LABEL: icmp_sge_vi_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.i v8, 0 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.i v16, 0 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2823,8 +2815,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2835,9 +2827,8 @@ define @icmp_slt_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_slt_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmslt.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp slt %va, %vb ret %vc @@ -2847,7 +2838,7 @@ ; CHECK-LABEL: icmp_slt_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2859,8 +2850,8 @@ ; CHECK-LABEL: icmp_slt_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmslt.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmslt.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2873,7 +2864,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2886,7 +2877,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2898,7 +2889,7 @@ ; CHECK-LABEL: icmp_slt_iv_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsgt.vi v0, v16, -15 +; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret %head = insertelement undef, i64 -15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2910,7 +2901,7 @@ ; CHECK-LABEL: icmp_slt_vi_nxv8i64_2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, zero +; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: ret %head = insertelement undef, i64 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2923,7 +2914,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmslt.vx v0, v16, a0 +; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2934,9 +2925,8 @@ define @icmp_sle_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: icmp_sle_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmsle.vv v0, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v16 ; CHECK-NEXT: ret %vc = icmp sle %va, %vb ret %vc @@ -2946,7 +2936,7 @@ ; CHECK-LABEL: icmp_sle_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsle.vx v0, v16, a0 +; CHECK-NEXT: vmsle.vx v0, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2958,8 +2948,8 @@ ; CHECK-LABEL: icmp_sle_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vmsle.vv v0, v8, v16 +; CHECK-NEXT: vmv.v.x v16, a0 +; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -2971,7 +2961,7 @@ ; CHECK-LABEL: icmp_sle_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmsle.vi v0, v16, 5 +; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret %head = insertelement undef, i64 5, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vaadd.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vaadd.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vaadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vaadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vaadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaadd.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vaadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaadd.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vaaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vaaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vaaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vaaddu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vaaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vaaddu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vadc.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +30,12 @@ i32); define @intrinsic_vadc_vvm_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +52,12 @@ i32); define @intrinsic_vadc_vvm_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +74,12 @@ i32); define @intrinsic_vadc_vvm_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +96,12 @@ i32); define @intrinsic_vadc_vvm_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +118,12 @@ i32); define @intrinsic_vadc_vvm_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +140,12 @@ i32); define @intrinsic_vadc_vvm_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +162,12 @@ i32); define @intrinsic_vadc_vvm_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +184,12 @@ i32); define @intrinsic_vadc_vvm_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +206,12 @@ i32); define @intrinsic_vadc_vvm_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +228,12 @@ i32); define @intrinsic_vadc_vvm_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +250,12 @@ i32); define @intrinsic_vadc_vvm_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +272,12 @@ i32); define @intrinsic_vadc_vvm_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +294,12 @@ i32); define @intrinsic_vadc_vvm_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +316,12 @@ i32); define @intrinsic_vadc_vvm_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +338,12 @@ i32); define @intrinsic_vadc_vvm_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +360,12 @@ i32); define @intrinsic_vadc_vvm_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +382,12 @@ i32); define @intrinsic_vadc_vvm_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +404,12 @@ i32); define @intrinsic_vadc_vxm_nxv1i8_nxv1i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i8.i8( %0, i8 %1, @@ -387,10 +426,12 @@ i32); define @intrinsic_vadc_vxm_nxv2i8_nxv2i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i8.i8( %0, i8 %1, @@ -407,10 +448,12 @@ i32); define @intrinsic_vadc_vxm_nxv4i8_nxv4i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i8.i8( %0, i8 %1, @@ -427,10 +470,12 @@ i32); define @intrinsic_vadc_vxm_nxv8i8_nxv8i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i8.i8( %0, i8 %1, @@ -447,10 +492,12 @@ i32); define @intrinsic_vadc_vxm_nxv16i8_nxv16i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i8.i8( %0, i8 %1, @@ -467,10 +514,12 @@ i32); define @intrinsic_vadc_vxm_nxv32i8_nxv32i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv32i8.i8( %0, i8 %1, @@ -487,10 +536,12 @@ i32); define @intrinsic_vadc_vxm_nxv64i8_nxv64i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv64i8.i8( %0, i8 %1, @@ -507,10 +558,12 @@ i32); define @intrinsic_vadc_vxm_nxv1i16_nxv1i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i16.i16( %0, i16 %1, @@ -527,10 +580,12 @@ i32); define @intrinsic_vadc_vxm_nxv2i16_nxv2i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i16.i16( %0, i16 %1, @@ -547,10 +602,12 @@ i32); define @intrinsic_vadc_vxm_nxv4i16_nxv4i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i16.i16( %0, i16 %1, @@ -567,10 +624,12 @@ i32); define @intrinsic_vadc_vxm_nxv8i16_nxv8i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i16.i16( %0, i16 %1, @@ -587,10 +646,12 @@ i32); define @intrinsic_vadc_vxm_nxv16i16_nxv16i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i16.i16( %0, i16 %1, @@ -607,10 +668,12 @@ i32); define @intrinsic_vadc_vxm_nxv32i16_nxv32i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv32i16.i16( %0, i16 %1, @@ -627,10 +690,12 @@ i32); define @intrinsic_vadc_vxm_nxv1i32_nxv1i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i32.i32( %0, i32 %1, @@ -647,10 +712,12 @@ i32); define @intrinsic_vadc_vxm_nxv2i32_nxv2i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i32.i32( %0, i32 %1, @@ -667,10 +734,12 @@ i32); define @intrinsic_vadc_vxm_nxv4i32_nxv4i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i32.i32( %0, i32 %1, @@ -687,10 +756,12 @@ i32); define @intrinsic_vadc_vxm_nxv8i32_nxv8i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i32.i32( %0, i32 %1, @@ -707,10 +778,12 @@ i32); define @intrinsic_vadc_vxm_nxv16i32_nxv16i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i32.i32( %0, i32 %1, @@ -721,10 +794,12 @@ } define @intrinsic_vadc_vim_nxv1i8_nxv1i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv1i8.i8( %0, i8 -9, @@ -735,10 +810,12 @@ } define @intrinsic_vadc_vim_nxv2i8_nxv2i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv2i8.i8( %0, i8 9, @@ -749,10 +826,12 @@ } define @intrinsic_vadc_vim_nxv4i8_nxv4i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv4i8.i8( %0, i8 -9, @@ -763,10 +842,12 @@ } define @intrinsic_vadc_vim_nxv8i8_nxv8i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv8i8.i8( %0, i8 9, @@ -777,10 +858,12 @@ } define @intrinsic_vadc_vim_nxv16i8_nxv16i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv16i8.i8( %0, i8 -9, @@ -791,10 +874,12 @@ } define @intrinsic_vadc_vim_nxv32i8_nxv32i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv32i8.i8( %0, i8 9, @@ -805,10 +890,12 @@ } define @intrinsic_vadc_vim_nxv64i8_nxv64i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv64i8.i8( %0, i8 -9, @@ -819,10 +906,12 @@ } define @intrinsic_vadc_vim_nxv1i16_nxv1i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv1i16.i16( %0, i16 9, @@ -833,10 +922,12 @@ } define @intrinsic_vadc_vim_nxv2i16_nxv2i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv2i16.i16( %0, i16 -9, @@ -847,10 +938,12 @@ } define @intrinsic_vadc_vim_nxv4i16_nxv4i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv4i16.i16( %0, i16 9, @@ -861,10 +954,12 @@ } define @intrinsic_vadc_vim_nxv8i16_nxv8i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv8i16.i16( %0, i16 -9, @@ -875,10 +970,12 @@ } define @intrinsic_vadc_vim_nxv16i16_nxv16i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv16i16.i16( %0, i16 9, @@ -889,10 +986,12 @@ } define @intrinsic_vadc_vim_nxv32i16_nxv32i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv32i16.i16( %0, i16 -9, @@ -903,10 +1002,12 @@ } define @intrinsic_vadc_vim_nxv1i32_nxv1i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv1i32.i32( %0, i32 9, @@ -917,10 +1018,12 @@ } define @intrinsic_vadc_vim_nxv2i32_nxv2i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv2i32.i32( %0, i32 -9, @@ -931,10 +1034,12 @@ } define @intrinsic_vadc_vim_nxv4i32_nxv4i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv4i32.i32( %0, i32 9, @@ -945,10 +1050,12 @@ } define @intrinsic_vadc_vim_nxv8i32_nxv8i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv8i32.i32( %0, i32 -9, @@ -959,10 +1066,12 @@ } define @intrinsic_vadc_vim_nxv16i32_nxv16i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv16i32.i32( %0, i32 9, diff --git a/llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vadc.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +30,12 @@ i64); define @intrinsic_vadc_vvm_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +52,12 @@ i64); define @intrinsic_vadc_vvm_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +74,12 @@ i64); define @intrinsic_vadc_vvm_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +96,12 @@ i64); define @intrinsic_vadc_vvm_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +118,12 @@ i64); define @intrinsic_vadc_vvm_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +140,12 @@ i64); define @intrinsic_vadc_vvm_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +162,12 @@ i64); define @intrinsic_vadc_vvm_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +184,12 @@ i64); define @intrinsic_vadc_vvm_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +206,12 @@ i64); define @intrinsic_vadc_vvm_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +228,12 @@ i64); define @intrinsic_vadc_vvm_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +250,12 @@ i64); define @intrinsic_vadc_vvm_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +272,12 @@ i64); define @intrinsic_vadc_vvm_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +294,12 @@ i64); define @intrinsic_vadc_vvm_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +316,12 @@ i64); define @intrinsic_vadc_vvm_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +338,12 @@ i64); define @intrinsic_vadc_vvm_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +360,12 @@ i64); define @intrinsic_vadc_vvm_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +382,12 @@ i64); define @intrinsic_vadc_vvm_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +404,12 @@ i64); define @intrinsic_vadc_vvm_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i64.nxv1i64( %0, %1, @@ -387,10 +426,12 @@ i64); define @intrinsic_vadc_vvm_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i64.nxv2i64( %0, %1, @@ -407,10 +448,12 @@ i64); define @intrinsic_vadc_vvm_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i64.nxv4i64( %0, %1, @@ -427,10 +470,12 @@ i64); define @intrinsic_vadc_vvm_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vadc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vvm_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i64.nxv8i64( %0, %1, @@ -447,10 +492,12 @@ i64); define @intrinsic_vadc_vxm_nxv1i8_nxv1i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i8.i8( %0, i8 %1, @@ -467,10 +514,12 @@ i64); define @intrinsic_vadc_vxm_nxv2i8_nxv2i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i8.i8( %0, i8 %1, @@ -487,10 +536,12 @@ i64); define @intrinsic_vadc_vxm_nxv4i8_nxv4i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i8.i8( %0, i8 %1, @@ -507,10 +558,12 @@ i64); define @intrinsic_vadc_vxm_nxv8i8_nxv8i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i8.i8( %0, i8 %1, @@ -527,10 +580,12 @@ i64); define @intrinsic_vadc_vxm_nxv16i8_nxv16i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i8.i8( %0, i8 %1, @@ -547,10 +602,12 @@ i64); define @intrinsic_vadc_vxm_nxv32i8_nxv32i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv32i8.i8( %0, i8 %1, @@ -567,10 +624,12 @@ i64); define @intrinsic_vadc_vxm_nxv64i8_nxv64i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv64i8.i8( %0, i8 %1, @@ -587,10 +646,12 @@ i64); define @intrinsic_vadc_vxm_nxv1i16_nxv1i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i16.i16( %0, i16 %1, @@ -607,10 +668,12 @@ i64); define @intrinsic_vadc_vxm_nxv2i16_nxv2i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i16.i16( %0, i16 %1, @@ -627,10 +690,12 @@ i64); define @intrinsic_vadc_vxm_nxv4i16_nxv4i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i16.i16( %0, i16 %1, @@ -647,10 +712,12 @@ i64); define @intrinsic_vadc_vxm_nxv8i16_nxv8i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i16.i16( %0, i16 %1, @@ -667,10 +734,12 @@ i64); define @intrinsic_vadc_vxm_nxv16i16_nxv16i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i16.i16( %0, i16 %1, @@ -687,10 +756,12 @@ i64); define @intrinsic_vadc_vxm_nxv32i16_nxv32i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv32i16.i16( %0, i16 %1, @@ -707,10 +778,12 @@ i64); define @intrinsic_vadc_vxm_nxv1i32_nxv1i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i32.i32( %0, i32 %1, @@ -727,10 +800,12 @@ i64); define @intrinsic_vadc_vxm_nxv2i32_nxv2i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i32.i32( %0, i32 %1, @@ -747,10 +822,12 @@ i64); define @intrinsic_vadc_vxm_nxv4i32_nxv4i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i32.i32( %0, i32 %1, @@ -767,10 +844,12 @@ i64); define @intrinsic_vadc_vxm_nxv8i32_nxv8i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i32.i32( %0, i32 %1, @@ -787,10 +866,12 @@ i64); define @intrinsic_vadc_vxm_nxv16i32_nxv16i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv16i32.i32( %0, i32 %1, @@ -807,10 +888,12 @@ i64); define @intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv1i64.i64( %0, i64 %1, @@ -827,10 +910,12 @@ i64); define @intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv2i64.i64( %0, i64 %1, @@ -847,10 +932,12 @@ i64); define @intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv4i64.i64( %0, i64 %1, @@ -867,10 +954,12 @@ i64); define @intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vadc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vxm_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vadc.nxv8i64.i64( %0, i64 %1, @@ -881,10 +970,12 @@ } define @intrinsic_vadc_vim_nxv1i8_nxv1i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv1i8.i8( %0, i8 9, @@ -895,10 +986,12 @@ } define @intrinsic_vadc_vim_nxv2i8_nxv2i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv2i8.i8( %0, i8 -9, @@ -909,10 +1002,12 @@ } define @intrinsic_vadc_vim_nxv4i8_nxv4i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv4i8.i8( %0, i8 9, @@ -923,10 +1018,12 @@ } define @intrinsic_vadc_vim_nxv8i8_nxv8i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv8i8.i8( %0, i8 -9, @@ -937,10 +1034,12 @@ } define @intrinsic_vadc_vim_nxv16i8_nxv16i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv16i8.i8( %0, i8 9, @@ -951,10 +1050,12 @@ } define @intrinsic_vadc_vim_nxv32i8_nxv32i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv32i8.i8( %0, i8 -9, @@ -965,10 +1066,12 @@ } define @intrinsic_vadc_vim_nxv64i8_nxv64i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv64i8.i8( %0, i8 9, @@ -979,10 +1082,12 @@ } define @intrinsic_vadc_vim_nxv1i16_nxv1i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv1i16.i16( %0, i16 -9, @@ -993,10 +1098,12 @@ } define @intrinsic_vadc_vim_nxv2i16_nxv2i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv2i16.i16( %0, i16 9, @@ -1007,10 +1114,12 @@ } define @intrinsic_vadc_vim_nxv4i16_nxv4i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv4i16.i16( %0, i16 -9, @@ -1021,10 +1130,12 @@ } define @intrinsic_vadc_vim_nxv8i16_nxv8i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv8i16.i16( %0, i16 9, @@ -1035,10 +1146,12 @@ } define @intrinsic_vadc_vim_nxv16i16_nxv16i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv16i16.i16( %0, i16 -9, @@ -1049,10 +1162,12 @@ } define @intrinsic_vadc_vim_nxv32i16_nxv32i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv32i16.i16( %0, i16 9, @@ -1063,10 +1178,12 @@ } define @intrinsic_vadc_vim_nxv1i32_nxv1i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv1i32.i32( %0, i32 -9, @@ -1077,10 +1194,12 @@ } define @intrinsic_vadc_vim_nxv2i32_nxv2i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv2i32.i32( %0, i32 9, @@ -1091,10 +1210,12 @@ } define @intrinsic_vadc_vim_nxv4i32_nxv4i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv4i32.i32( %0, i32 -9, @@ -1105,10 +1226,12 @@ } define @intrinsic_vadc_vim_nxv8i32_nxv8i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv8i32.i32( %0, i32 9, @@ -1119,10 +1242,12 @@ } define @intrinsic_vadc_vim_nxv16i32_nxv16i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv16i32.i32( %0, i32 -9, @@ -1133,10 +1258,12 @@ } define @intrinsic_vadc_vim_nxv1i64_nxv1i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv1i64.i64( %0, i64 9, @@ -1147,10 +1274,12 @@ } define @intrinsic_vadc_vim_nxv2i64_nxv2i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv2i64.i64( %0, i64 -9, @@ -1161,10 +1290,12 @@ } define @intrinsic_vadc_vim_nxv4i64_nxv4i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vadc.nxv4i64.i64( %0, i64 9, @@ -1175,10 +1306,12 @@ } define @intrinsic_vadc_vim_nxv8i64_nxv8i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadc_vim_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vadc.vim v8, v8, -9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadc_vim_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vadc.vim {{v[0-9]+}}, {{v[0-9]+}}, -9, v0 %a = call @llvm.riscv.vadc.nxv8i64.i64( %0, i64 -9, diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vadd.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vadd.nxv64i8.i8( %0, i8 -9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vadd.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vadd_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vadd_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vadd_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vadd_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vadd_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vadd_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vadd_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vadd_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vadd_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vadd_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vadd_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vadd_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vadd_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vadd_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vadd_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vadd_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vadd_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vadd_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vadd_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vadd_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vadd_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vadd_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vadd.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vadd_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vadd_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vadd_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vadd_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vadd_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vadd_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vadd_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vadd_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vadd_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vadd_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vadd_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vadd_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vadd_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vadd_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vadd_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vadd_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vadd_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vadd_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vadd_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vadd_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vadd_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vadd_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vadd_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vadd.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vadd_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vadd.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -44,7 +44,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu ; CHECK-NEXT: vmv.v.i v25, 2 -; CHECK-NEXT: vadd.vi v16, v25, 3 +; CHECK-NEXT: vadd.vi v8, v25, 3 ; CHECK-NEXT: ret %heada = insertelement undef, i8 2, i32 0 %splata = shufflevector %heada, undef, zeroinitializer @@ -58,7 +58,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -70,7 +70,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -82,7 +82,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -94,7 +94,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,7 +106,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -118,7 +118,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -130,7 +130,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -142,7 +142,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -154,7 +154,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -166,7 +166,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -178,7 +178,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -190,7 +190,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -202,7 +202,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,7 +214,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -226,7 +226,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -238,7 +238,7 @@ ; CHECK-LABEL: vadd_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -250,7 +250,7 @@ ; CHECK-LABEL: vadd_vx_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -262,7 +262,7 @@ ; CHECK-LABEL: vadd_vx_nxv64i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +274,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +286,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -298,7 +298,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +310,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -322,7 +322,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,7 +334,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,7 +346,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -358,7 +358,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -370,7 +370,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -382,7 +382,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -394,7 +394,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -406,7 +406,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -418,7 +418,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -430,7 +430,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -442,7 +442,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -454,7 +454,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -466,7 +466,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -478,7 +478,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -490,7 +490,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -502,7 +502,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -514,7 +514,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -526,7 +526,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -538,7 +538,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -550,7 +550,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -562,7 +562,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -574,7 +574,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -586,7 +586,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -598,7 +598,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -610,7 +610,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -622,7 +622,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -634,7 +634,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -646,7 +646,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -658,7 +658,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -677,7 +677,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vadd.vv v16, v16, v25 +; CHECK-NEXT: vadd.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -689,7 +689,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -701,7 +701,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i64 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -720,7 +720,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vadd.vv v16, v16, v26 +; CHECK-NEXT: vadd.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -732,7 +732,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -744,7 +744,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i64 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -759,11 +759,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vadd.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vadd.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -775,7 +775,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -787,7 +787,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i64 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -799,14 +799,14 @@ ; CHECK-LABEL: vadd_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vadd.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -818,7 +818,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -830,7 +830,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i64 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -41,7 +41,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -53,7 +53,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -65,7 +65,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -77,7 +77,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -89,7 +89,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -101,7 +101,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -113,7 +113,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -125,7 +125,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -137,7 +137,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -149,7 +149,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -161,7 +161,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -173,7 +173,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -185,7 +185,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -209,7 +209,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -221,7 +221,7 @@ ; CHECK-LABEL: vadd_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -233,7 +233,7 @@ ; CHECK-LABEL: vadd_vx_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +245,7 @@ ; CHECK-LABEL: vadd_vx_nxv64i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i8 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,7 +257,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -269,7 +269,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +281,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -293,7 +293,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -305,7 +305,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -317,7 +317,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -329,7 +329,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -341,7 +341,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -353,7 +353,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -365,7 +365,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -377,7 +377,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -389,7 +389,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -401,7 +401,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,7 +413,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,7 +425,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -437,7 +437,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +449,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,7 +461,7 @@ ; CHECK-LABEL: vadd_vx_nxv32i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i16 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -473,7 +473,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +485,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +497,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -509,7 +509,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -521,7 +521,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -533,7 +533,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -545,7 +545,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -557,7 +557,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -569,7 +569,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -581,7 +581,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -593,7 +593,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -605,7 +605,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -617,7 +617,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -629,7 +629,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -641,7 +641,7 @@ ; CHECK-LABEL: vadd_vx_nxv16i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i32 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -653,7 +653,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -665,7 +665,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -677,7 +677,7 @@ ; CHECK-LABEL: vadd_vx_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i64 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -689,7 +689,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -701,7 +701,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -713,7 +713,7 @@ ; CHECK-LABEL: vadd_vx_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i64 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -725,7 +725,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -737,7 +737,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -749,7 +749,7 @@ ; CHECK-LABEL: vadd_vx_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i64 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -761,7 +761,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vadd.vx v16, v16, a0 +; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -773,7 +773,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, -1 +; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -785,7 +785,7 @@ ; CHECK-LABEL: vadd_vx_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vadd.vi v16, v16, 2 +; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret %head = insertelement undef, i64 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i32.nxv1i32( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i32( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i32.nxv2i32( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i32( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i32.nxv4i32( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i32( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i32.nxv8i32( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i32( @@ -202,11 +202,9 @@ define @intrinsic_vamoadd_v_nxv16i32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv16i32.nxv16i32( @@ -228,11 +226,9 @@ define @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i32( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i32.nxv1i16( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i16( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i32.nxv2i16( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i16( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i32.nxv4i16( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i16( @@ -399,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i32.nxv8i16( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i16( @@ -446,11 +442,9 @@ define @intrinsic_vamoadd_v_nxv16i32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv16i32.nxv16i16( @@ -472,11 +466,9 @@ define @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i16( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i32.nxv1i8( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i8( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i32.nxv2i8( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i8( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i32.nxv4i8( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i8( @@ -643,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i32.nxv8i8( @@ -667,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i8( @@ -690,11 +682,9 @@ define @intrinsic_vamoadd_v_nxv16i32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv16i32.nxv16i8( @@ -716,11 +706,9 @@ define @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i32.nxv1i64( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i64( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoaddei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i32.nxv2i64( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoaddei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i64( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoaddei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i32.nxv4i64( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoaddei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i64( @@ -154,11 +154,9 @@ define @intrinsic_vamoadd_v_nxv8i32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoaddei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i32.nxv8i64( @@ -180,11 +178,9 @@ define @intrinsic_vamoadd_mask_v_nxv8i32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoaddei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i64( @@ -207,8 +203,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoaddei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i64.nxv1i64( @@ -231,8 +227,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoaddei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i64( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoaddei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i64.nxv2i64( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoaddei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i64( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoaddei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i64.nxv4i64( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoaddei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i64( @@ -350,11 +346,9 @@ define @intrinsic_vamoadd_v_nxv8i64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoaddei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoaddei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i64.nxv8i64( @@ -376,11 +370,9 @@ define @intrinsic_vamoadd_mask_v_nxv8i64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoaddei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoaddei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i64( @@ -403,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i32.nxv1i32( @@ -427,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i32( @@ -451,8 +443,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i32.nxv2i32( @@ -475,8 +467,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i32( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i32.nxv4i32( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i32( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i32.nxv8i32( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i32( @@ -594,11 +586,9 @@ define @intrinsic_vamoadd_v_nxv16i32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv16i32.nxv16i32( @@ -620,11 +610,9 @@ define @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i32( @@ -647,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i64.nxv1i32( @@ -671,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoaddei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i32( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i64.nxv2i32( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoaddei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i32( @@ -743,8 +731,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i64.nxv4i32( @@ -767,8 +755,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoaddei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i32( @@ -790,11 +778,9 @@ define @intrinsic_vamoadd_v_nxv8i64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoaddei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i64.nxv8i32( @@ -816,11 +802,9 @@ define @intrinsic_vamoadd_mask_v_nxv8i64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoaddei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoaddei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i32( @@ -843,8 +827,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i32.nxv1i16( @@ -867,8 +851,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i16( @@ -891,8 +875,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i32.nxv2i16( @@ -915,8 +899,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i16( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i32.nxv4i16( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i16( @@ -987,8 +971,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i32.nxv8i16( @@ -1011,8 +995,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i16( @@ -1034,11 +1018,9 @@ define @intrinsic_vamoadd_v_nxv16i32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv16i32.nxv16i16( @@ -1060,11 +1042,9 @@ define @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i16( @@ -1087,8 +1067,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i64.nxv1i16( @@ -1111,8 +1091,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoaddei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i16( @@ -1135,8 +1115,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i64.nxv2i16( @@ -1159,8 +1139,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoaddei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i16( @@ -1183,8 +1163,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i64.nxv4i16( @@ -1207,8 +1187,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoaddei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i16( @@ -1230,11 +1210,9 @@ define @intrinsic_vamoadd_v_nxv8i64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoaddei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i64.nxv8i16( @@ -1256,11 +1234,9 @@ define @intrinsic_vamoadd_mask_v_nxv8i64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoaddei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoaddei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i16( @@ -1283,8 +1259,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i32.nxv1i8( @@ -1307,8 +1283,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i32.nxv1i8( @@ -1331,8 +1307,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i32.nxv2i8( @@ -1355,8 +1331,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i32.nxv2i8( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i32.nxv4i8( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i32.nxv4i8( @@ -1427,8 +1403,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i32.nxv8i8( @@ -1451,8 +1427,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i32.nxv8i8( @@ -1474,11 +1450,9 @@ define @intrinsic_vamoadd_v_nxv16i32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv16i32.nxv16i8( @@ -1500,11 +1474,9 @@ define @intrinsic_vamoadd_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoaddei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv16i32.nxv16i8( @@ -1527,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv1i64.nxv1i8( @@ -1551,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoaddei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoaddei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv1i64.nxv1i8( @@ -1575,8 +1547,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv2i64.nxv2i8( @@ -1599,8 +1571,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoaddei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoaddei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv2i64.nxv2i8( @@ -1623,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv4i64.nxv4i8( @@ -1647,8 +1619,8 @@ ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoaddei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoaddei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv4i64.nxv4i8( @@ -1670,11 +1642,9 @@ define @intrinsic_vamoadd_v_nxv8i64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoaddei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.nxv8i64.nxv8i8( @@ -1696,11 +1666,9 @@ define @intrinsic_vamoadd_mask_v_nxv8i64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoadd_mask_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoaddei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoaddei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoadd.mask.nxv8i64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i32.nxv1i32( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i32.nxv1i32( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i32.nxv2i32( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i32.nxv2i32( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i32.nxv4i32( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i32.nxv4i32( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i32.nxv8i32( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i32.nxv8i32( @@ -202,11 +202,9 @@ define @intrinsic_vamoand_v_nxv16i32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv16i32.nxv16i32( @@ -228,11 +226,9 @@ define @intrinsic_vamoand_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv16i32.nxv16i32( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i32.nxv1i16( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i32.nxv1i16( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i32.nxv2i16( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i32.nxv2i16( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i32.nxv4i16( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i32.nxv4i16( @@ -399,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i32.nxv8i16( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i32.nxv8i16( @@ -446,11 +442,9 @@ define @intrinsic_vamoand_v_nxv16i32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv16i32.nxv16i16( @@ -472,11 +466,9 @@ define @intrinsic_vamoand_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv16i32.nxv16i16( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i32.nxv1i8( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i32.nxv1i8( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i32.nxv2i8( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i32.nxv2i8( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i32.nxv4i8( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i32.nxv4i8( @@ -643,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i32.nxv8i8( @@ -667,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i32.nxv8i8( @@ -690,11 +682,9 @@ define @intrinsic_vamoand_v_nxv16i32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv16i32.nxv16i8( @@ -716,11 +706,9 @@ define @intrinsic_vamoand_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv16i32.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i32.nxv1i64( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i32.nxv1i64( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoandei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i32.nxv2i64( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoandei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i32.nxv2i64( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoandei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i32.nxv4i64( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoandei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i32.nxv4i64( @@ -154,11 +154,9 @@ define @intrinsic_vamoand_v_nxv8i32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoandei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoandei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i32.nxv8i64( @@ -180,11 +178,9 @@ define @intrinsic_vamoand_mask_v_nxv8i32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoandei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoandei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i32.nxv8i64( @@ -207,8 +203,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoandei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i64.nxv1i64( @@ -231,8 +227,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoandei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i64.nxv1i64( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoandei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i64.nxv2i64( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoandei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i64.nxv2i64( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoandei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i64.nxv4i64( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoandei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i64.nxv4i64( @@ -350,11 +346,9 @@ define @intrinsic_vamoand_v_nxv8i64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoandei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoandei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i64.nxv8i64( @@ -376,11 +370,9 @@ define @intrinsic_vamoand_mask_v_nxv8i64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoandei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoandei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i64.nxv8i64( @@ -403,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i32.nxv1i32( @@ -427,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i32.nxv1i32( @@ -451,8 +443,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i32.nxv2i32( @@ -475,8 +467,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i32.nxv2i32( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i32.nxv4i32( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i32.nxv4i32( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i32.nxv8i32( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i32.nxv8i32( @@ -594,11 +586,9 @@ define @intrinsic_vamoand_v_nxv16i32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv16i32.nxv16i32( @@ -620,11 +610,9 @@ define @intrinsic_vamoand_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv16i32.nxv16i32( @@ -647,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i64.nxv1i32( @@ -671,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoandei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i64.nxv1i32( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i64.nxv2i32( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoandei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i64.nxv2i32( @@ -743,8 +731,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i64.nxv4i32( @@ -767,8 +755,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoandei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i64.nxv4i32( @@ -790,11 +778,9 @@ define @intrinsic_vamoand_v_nxv8i64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoandei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i64.nxv8i32( @@ -816,11 +802,9 @@ define @intrinsic_vamoand_mask_v_nxv8i64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoandei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoandei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i64.nxv8i32( @@ -843,8 +827,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i32.nxv1i16( @@ -867,8 +851,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i32.nxv1i16( @@ -891,8 +875,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i32.nxv2i16( @@ -915,8 +899,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i32.nxv2i16( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i32.nxv4i16( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i32.nxv4i16( @@ -987,8 +971,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i32.nxv8i16( @@ -1011,8 +995,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i32.nxv8i16( @@ -1034,11 +1018,9 @@ define @intrinsic_vamoand_v_nxv16i32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv16i32.nxv16i16( @@ -1060,11 +1042,9 @@ define @intrinsic_vamoand_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv16i32.nxv16i16( @@ -1087,8 +1067,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i64.nxv1i16( @@ -1111,8 +1091,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoandei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i64.nxv1i16( @@ -1135,8 +1115,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i64.nxv2i16( @@ -1159,8 +1139,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoandei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i64.nxv2i16( @@ -1183,8 +1163,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i64.nxv4i16( @@ -1207,8 +1187,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoandei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i64.nxv4i16( @@ -1230,11 +1210,9 @@ define @intrinsic_vamoand_v_nxv8i64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoandei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i64.nxv8i16( @@ -1256,11 +1234,9 @@ define @intrinsic_vamoand_mask_v_nxv8i64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoandei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoandei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i64.nxv8i16( @@ -1283,8 +1259,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i32.nxv1i8( @@ -1307,8 +1283,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i32.nxv1i8( @@ -1331,8 +1307,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i32.nxv2i8( @@ -1355,8 +1331,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i32.nxv2i8( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i32.nxv4i8( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i32.nxv4i8( @@ -1427,8 +1403,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i32.nxv8i8( @@ -1451,8 +1427,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i32.nxv8i8( @@ -1474,11 +1450,9 @@ define @intrinsic_vamoand_v_nxv16i32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv16i32.nxv16i8( @@ -1500,11 +1474,9 @@ define @intrinsic_vamoand_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoandei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv16i32.nxv16i8( @@ -1527,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv1i64.nxv1i8( @@ -1551,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoandei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoandei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv1i64.nxv1i8( @@ -1575,8 +1547,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv2i64.nxv2i8( @@ -1599,8 +1571,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoandei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoandei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv2i64.nxv2i8( @@ -1623,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vamoand_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv4i64.nxv4i8( @@ -1647,8 +1619,8 @@ ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoandei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoandei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv4i64.nxv4i8( @@ -1670,11 +1642,9 @@ define @intrinsic_vamoand_v_nxv8i64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoand_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoandei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.nxv8i64.nxv8i8( @@ -1696,11 +1666,9 @@ define @intrinsic_vamoand_mask_v_nxv8i64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoand_mask_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoandei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoandei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoand.mask.nxv8i64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i32.nxv1i32( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i32.nxv1i32( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i32.nxv2i32( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i32.nxv2i32( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i32.nxv4i32( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i32.nxv4i32( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i32.nxv8i32( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i32.nxv8i32( @@ -202,11 +202,9 @@ define @intrinsic_vamomax_v_nxv16i32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv16i32.nxv16i32( @@ -228,11 +226,9 @@ define @intrinsic_vamomax_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv16i32.nxv16i32( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i32.nxv1i16( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i32.nxv1i16( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i32.nxv2i16( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i32.nxv2i16( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i32.nxv4i16( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i32.nxv4i16( @@ -399,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i32.nxv8i16( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i32.nxv8i16( @@ -446,11 +442,9 @@ define @intrinsic_vamomax_v_nxv16i32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv16i32.nxv16i16( @@ -472,11 +466,9 @@ define @intrinsic_vamomax_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv16i32.nxv16i16( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i32.nxv1i8( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i32.nxv1i8( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i32.nxv2i8( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i32.nxv2i8( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i32.nxv4i8( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i32.nxv4i8( @@ -643,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i32.nxv8i8( @@ -667,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i32.nxv8i8( @@ -690,11 +682,9 @@ define @intrinsic_vamomax_v_nxv16i32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv16i32.nxv16i8( @@ -716,11 +706,9 @@ define @intrinsic_vamomax_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv16i32.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i32.nxv1i64( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i32.nxv1i64( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamomaxei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i32.nxv2i64( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamomaxei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i32.nxv2i64( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamomaxei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i32.nxv4i64( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamomaxei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i32.nxv4i64( @@ -154,11 +154,9 @@ define @intrinsic_vamomax_v_nxv8i32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamomaxei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i32.nxv8i64( @@ -180,11 +178,9 @@ define @intrinsic_vamomax_mask_v_nxv8i32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamomaxei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i32.nxv8i64( @@ -207,8 +203,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i64.nxv1i64( @@ -231,8 +227,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i64.nxv1i64( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i64.nxv2i64( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i64.nxv2i64( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i64.nxv4i64( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i64.nxv4i64( @@ -350,11 +346,9 @@ define @intrinsic_vamomax_v_nxv8i64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i64.nxv8i64( @@ -376,11 +370,9 @@ define @intrinsic_vamomax_mask_v_nxv8i64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i64.nxv8i64( @@ -403,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i32.nxv1i32( @@ -427,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i32.nxv1i32( @@ -451,8 +443,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i32.nxv2i32( @@ -475,8 +467,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i32.nxv2i32( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i32.nxv4i32( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i32.nxv4i32( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i32.nxv8i32( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i32.nxv8i32( @@ -594,11 +586,9 @@ define @intrinsic_vamomax_v_nxv16i32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv16i32.nxv16i32( @@ -620,11 +610,9 @@ define @intrinsic_vamomax_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv16i32.nxv16i32( @@ -647,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i64.nxv1i32( @@ -671,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i64.nxv1i32( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i64.nxv2i32( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i64.nxv2i32( @@ -743,8 +731,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i64.nxv4i32( @@ -767,8 +755,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i64.nxv4i32( @@ -790,11 +778,9 @@ define @intrinsic_vamomax_v_nxv8i64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i64.nxv8i32( @@ -816,11 +802,9 @@ define @intrinsic_vamomax_mask_v_nxv8i64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i64.nxv8i32( @@ -843,8 +827,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i32.nxv1i16( @@ -867,8 +851,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i32.nxv1i16( @@ -891,8 +875,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i32.nxv2i16( @@ -915,8 +899,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i32.nxv2i16( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i32.nxv4i16( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i32.nxv4i16( @@ -987,8 +971,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i32.nxv8i16( @@ -1011,8 +995,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i32.nxv8i16( @@ -1034,11 +1018,9 @@ define @intrinsic_vamomax_v_nxv16i32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv16i32.nxv16i16( @@ -1060,11 +1042,9 @@ define @intrinsic_vamomax_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv16i32.nxv16i16( @@ -1087,8 +1067,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i64.nxv1i16( @@ -1111,8 +1091,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i64.nxv1i16( @@ -1135,8 +1115,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i64.nxv2i16( @@ -1159,8 +1139,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i64.nxv2i16( @@ -1183,8 +1163,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i64.nxv4i16( @@ -1207,8 +1187,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i64.nxv4i16( @@ -1230,11 +1210,9 @@ define @intrinsic_vamomax_v_nxv8i64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i64.nxv8i16( @@ -1256,11 +1234,9 @@ define @intrinsic_vamomax_mask_v_nxv8i64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i64.nxv8i16( @@ -1283,8 +1259,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i32.nxv1i8( @@ -1307,8 +1283,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i32.nxv1i8( @@ -1331,8 +1307,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i32.nxv2i8( @@ -1355,8 +1331,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i32.nxv2i8( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i32.nxv4i8( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i32.nxv4i8( @@ -1427,8 +1403,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i32.nxv8i8( @@ -1451,8 +1427,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i32.nxv8i8( @@ -1474,11 +1450,9 @@ define @intrinsic_vamomax_v_nxv16i32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv16i32.nxv16i8( @@ -1500,11 +1474,9 @@ define @intrinsic_vamomax_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv16i32.nxv16i8( @@ -1527,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv1i64.nxv1i8( @@ -1551,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv1i64.nxv1i8( @@ -1575,8 +1547,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv2i64.nxv2i8( @@ -1599,8 +1571,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv2i64.nxv2i8( @@ -1623,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vamomax_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv4i64.nxv4i8( @@ -1647,8 +1619,8 @@ ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv4i64.nxv4i8( @@ -1670,11 +1642,9 @@ define @intrinsic_vamomax_v_nxv8i64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomax_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.nxv8i64.nxv8i8( @@ -1696,11 +1666,9 @@ define @intrinsic_vamomax_mask_v_nxv8i64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomax_mask_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomax.mask.nxv8i64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i32.nxv1i16( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i16( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i32.nxv2i16( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i16( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i32.nxv4i16( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i16( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i32.nxv8i16( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i16( @@ -202,11 +202,9 @@ define @intrinsic_vamomaxu_v_nxv16i32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv16i32.nxv16i16( @@ -228,11 +226,9 @@ define @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i16( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i32.nxv1i8( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i8( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i32.nxv2i8( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i8( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i32.nxv4i8( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i8( @@ -399,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i32.nxv8i8( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i8( @@ -446,11 +442,9 @@ define @intrinsic_vamomaxu_v_nxv16i32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv16i32.nxv16i8( @@ -472,11 +466,9 @@ define @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i8( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i32.nxv1i32( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i32( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i32.nxv2i32( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i32( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i32.nxv4i32( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i32( @@ -643,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i32.nxv8i32( @@ -667,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i32( @@ -690,11 +682,9 @@ define @intrinsic_vamomaxu_v_nxv16i32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv16i32.nxv16i32( @@ -716,11 +706,9 @@ define @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i32.nxv1i32( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i32( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i32.nxv2i32( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i32( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i32.nxv4i32( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i32( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i32.nxv8i32( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i32( @@ -202,11 +202,9 @@ define @intrinsic_vamomaxu_v_nxv16i32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv16i32.nxv16i32( @@ -228,11 +226,9 @@ define @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i32( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i64.nxv1i32( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i32( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i64.nxv2i32( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxuei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i32( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i64.nxv4i32( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxuei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i32( @@ -398,11 +394,9 @@ define @intrinsic_vamomaxu_v_nxv8i64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxuei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i64.nxv8i32( @@ -424,11 +418,9 @@ define @intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxuei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxuei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i32( @@ -451,8 +443,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i32.nxv1i16( @@ -475,8 +467,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i16( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i32.nxv2i16( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i16( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i32.nxv4i16( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i16( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i32.nxv8i16( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i16( @@ -642,11 +634,9 @@ define @intrinsic_vamomaxu_v_nxv16i32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv16i32.nxv16i16( @@ -668,11 +658,9 @@ define @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i16( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i64.nxv1i16( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i16( @@ -743,8 +731,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i64.nxv2i16( @@ -767,8 +755,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxuei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i16( @@ -791,8 +779,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i64.nxv4i16( @@ -815,8 +803,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxuei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i16( @@ -838,11 +826,9 @@ define @intrinsic_vamomaxu_v_nxv8i64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxuei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i64.nxv8i16( @@ -864,11 +850,9 @@ define @intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxuei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxuei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i16( @@ -891,8 +875,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i32.nxv1i8( @@ -915,8 +899,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i8( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i32.nxv2i8( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i8( @@ -987,8 +971,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i32.nxv4i8( @@ -1011,8 +995,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i8( @@ -1035,8 +1019,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i32.nxv8i8( @@ -1059,8 +1043,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i8( @@ -1082,11 +1066,9 @@ define @intrinsic_vamomaxu_v_nxv16i32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv16i32.nxv16i8( @@ -1108,11 +1090,9 @@ define @intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamomaxuei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv16i32.nxv16i8( @@ -1135,8 +1115,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i64.nxv1i8( @@ -1159,8 +1139,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i8( @@ -1183,8 +1163,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i64.nxv2i8( @@ -1207,8 +1187,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxuei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i8( @@ -1231,8 +1211,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i64.nxv4i8( @@ -1255,8 +1235,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxuei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i8( @@ -1278,11 +1258,9 @@ define @intrinsic_vamomaxu_v_nxv8i64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxuei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i64.nxv8i8( @@ -1304,11 +1282,9 @@ define @intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxuei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxuei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i8( @@ -1331,8 +1307,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i32.nxv1i64( @@ -1355,8 +1331,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamomaxuei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i32.nxv1i64( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamomaxuei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i32.nxv2i64( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamomaxuei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamomaxuei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i32.nxv2i64( @@ -1427,8 +1403,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamomaxuei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i32.nxv4i64( @@ -1451,8 +1427,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamomaxuei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamomaxuei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i32.nxv4i64( @@ -1474,11 +1450,9 @@ define @intrinsic_vamomaxu_v_nxv8i32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamomaxuei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i32.nxv8i64( @@ -1500,11 +1474,9 @@ define @intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamomaxuei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamomaxuei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i32.nxv8i64( @@ -1527,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxuei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv1i64.nxv1i64( @@ -1551,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamomaxuei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamomaxuei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv1i64.nxv1i64( @@ -1575,8 +1547,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxuei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv2i64.nxv2i64( @@ -1599,8 +1571,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamomaxuei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamomaxuei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv2i64.nxv2i64( @@ -1623,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxuei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv4i64.nxv4i64( @@ -1647,8 +1619,8 @@ ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamomaxuei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamomaxuei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv4i64.nxv4i64( @@ -1670,11 +1642,9 @@ define @intrinsic_vamomaxu_v_nxv8i64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxuei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxuei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.nxv8i64.nxv8i64( @@ -1696,11 +1666,9 @@ define @intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomaxu_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamomaxuei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamomaxuei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomaxu.mask.nxv8i64.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i32.nxv1i32( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i32.nxv1i32( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i32.nxv2i32( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i32.nxv2i32( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i32.nxv4i32( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i32.nxv4i32( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i32.nxv8i32( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i32.nxv8i32( @@ -202,11 +202,9 @@ define @intrinsic_vamomin_v_nxv16i32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv16i32.nxv16i32( @@ -228,11 +226,9 @@ define @intrinsic_vamomin_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv16i32.nxv16i32( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i32.nxv1i16( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i32.nxv1i16( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i32.nxv2i16( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i32.nxv2i16( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i32.nxv4i16( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i32.nxv4i16( @@ -399,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i32.nxv8i16( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i32.nxv8i16( @@ -446,11 +442,9 @@ define @intrinsic_vamomin_v_nxv16i32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv16i32.nxv16i16( @@ -472,11 +466,9 @@ define @intrinsic_vamomin_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv16i32.nxv16i16( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i32.nxv1i8( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i32.nxv1i8( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i32.nxv2i8( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i32.nxv2i8( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i32.nxv4i8( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i32.nxv4i8( @@ -643,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i32.nxv8i8( @@ -667,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i32.nxv8i8( @@ -690,11 +682,9 @@ define @intrinsic_vamomin_v_nxv16i32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv16i32.nxv16i8( @@ -716,11 +706,9 @@ define @intrinsic_vamomin_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv16i32.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i32.nxv1i64( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i32.nxv1i64( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamominei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i32.nxv2i64( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamominei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i32.nxv2i64( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamominei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i32.nxv4i64( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamominei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i32.nxv4i64( @@ -154,11 +154,9 @@ define @intrinsic_vamomin_v_nxv8i32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamominei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamominei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i32.nxv8i64( @@ -180,11 +178,9 @@ define @intrinsic_vamomin_mask_v_nxv8i32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamominei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamominei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i32.nxv8i64( @@ -207,8 +203,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i64.nxv1i64( @@ -231,8 +227,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i64.nxv1i64( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i64.nxv2i64( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i64.nxv2i64( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i64.nxv4i64( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i64.nxv4i64( @@ -350,11 +346,9 @@ define @intrinsic_vamomin_v_nxv8i64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i64.nxv8i64( @@ -376,11 +370,9 @@ define @intrinsic_vamomin_mask_v_nxv8i64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i64.nxv8i64( @@ -403,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i32.nxv1i32( @@ -427,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i32.nxv1i32( @@ -451,8 +443,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i32.nxv2i32( @@ -475,8 +467,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i32.nxv2i32( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i32.nxv4i32( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i32.nxv4i32( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i32.nxv8i32( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i32.nxv8i32( @@ -594,11 +586,9 @@ define @intrinsic_vamomin_v_nxv16i32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv16i32.nxv16i32( @@ -620,11 +610,9 @@ define @intrinsic_vamomin_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv16i32.nxv16i32( @@ -647,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i64.nxv1i32( @@ -671,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i64.nxv1i32( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i64.nxv2i32( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i64.nxv2i32( @@ -743,8 +731,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i64.nxv4i32( @@ -767,8 +755,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i64.nxv4i32( @@ -790,11 +778,9 @@ define @intrinsic_vamomin_v_nxv8i64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i64.nxv8i32( @@ -816,11 +802,9 @@ define @intrinsic_vamomin_mask_v_nxv8i64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i64.nxv8i32( @@ -843,8 +827,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i32.nxv1i16( @@ -867,8 +851,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i32.nxv1i16( @@ -891,8 +875,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i32.nxv2i16( @@ -915,8 +899,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i32.nxv2i16( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i32.nxv4i16( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i32.nxv4i16( @@ -987,8 +971,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i32.nxv8i16( @@ -1011,8 +995,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i32.nxv8i16( @@ -1034,11 +1018,9 @@ define @intrinsic_vamomin_v_nxv16i32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv16i32.nxv16i16( @@ -1060,11 +1042,9 @@ define @intrinsic_vamomin_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv16i32.nxv16i16( @@ -1087,8 +1067,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i64.nxv1i16( @@ -1111,8 +1091,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i64.nxv1i16( @@ -1135,8 +1115,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i64.nxv2i16( @@ -1159,8 +1139,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i64.nxv2i16( @@ -1183,8 +1163,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i64.nxv4i16( @@ -1207,8 +1187,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i64.nxv4i16( @@ -1230,11 +1210,9 @@ define @intrinsic_vamomin_v_nxv8i64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i64.nxv8i16( @@ -1256,11 +1234,9 @@ define @intrinsic_vamomin_mask_v_nxv8i64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i64.nxv8i16( @@ -1283,8 +1259,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i32.nxv1i8( @@ -1307,8 +1283,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i32.nxv1i8( @@ -1331,8 +1307,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i32.nxv2i8( @@ -1355,8 +1331,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i32.nxv2i8( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i32.nxv4i8( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i32.nxv4i8( @@ -1427,8 +1403,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i32.nxv8i8( @@ -1451,8 +1427,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i32.nxv8i8( @@ -1474,11 +1450,9 @@ define @intrinsic_vamomin_v_nxv16i32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv16i32.nxv16i8( @@ -1500,11 +1474,9 @@ define @intrinsic_vamomin_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv16i32.nxv16i8( @@ -1527,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv1i64.nxv1i8( @@ -1551,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv1i64.nxv1i8( @@ -1575,8 +1547,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv2i64.nxv2i8( @@ -1599,8 +1571,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv2i64.nxv2i8( @@ -1623,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vamomin_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv4i64.nxv4i8( @@ -1647,8 +1619,8 @@ ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv4i64.nxv4i8( @@ -1670,11 +1642,9 @@ define @intrinsic_vamomin_v_nxv8i64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamomin_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.nxv8i64.nxv8i8( @@ -1696,11 +1666,9 @@ define @intrinsic_vamomin_mask_v_nxv8i64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamomin_mask_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamomin.mask.nxv8i64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i32.nxv1i32( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i32.nxv1i32( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i32.nxv2i32( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i32.nxv2i32( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i32.nxv4i32( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i32.nxv4i32( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i32.nxv8i32( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i32.nxv8i32( @@ -202,11 +202,9 @@ define @intrinsic_vamominu_v_nxv16i32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv16i32.nxv16i32( @@ -228,11 +226,9 @@ define @intrinsic_vamominu_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv16i32.nxv16i32( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i32.nxv1i16( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i32.nxv1i16( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i32.nxv2i16( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i32.nxv2i16( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i32.nxv4i16( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i32.nxv4i16( @@ -399,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i32.nxv8i16( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i32.nxv8i16( @@ -446,11 +442,9 @@ define @intrinsic_vamominu_v_nxv16i32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv16i32.nxv16i16( @@ -472,11 +466,9 @@ define @intrinsic_vamominu_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv16i32.nxv16i16( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i32.nxv1i8( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i32.nxv1i8( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i32.nxv2i8( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i32.nxv2i8( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i32.nxv4i8( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i32.nxv4i8( @@ -643,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i32.nxv8i8( @@ -667,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i32.nxv8i8( @@ -690,11 +682,9 @@ define @intrinsic_vamominu_v_nxv16i32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv16i32.nxv16i8( @@ -716,11 +706,9 @@ define @intrinsic_vamominu_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv16i32.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i32.nxv1i64( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i32.nxv1i64( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamominuei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i32.nxv2i64( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamominuei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i32.nxv2i64( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamominuei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i32.nxv4i64( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamominuei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i32.nxv4i64( @@ -154,11 +154,9 @@ define @intrinsic_vamominu_v_nxv8i32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamominuei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamominuei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i32.nxv8i64( @@ -180,11 +178,9 @@ define @intrinsic_vamominu_mask_v_nxv8i32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamominuei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamominuei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i32.nxv8i64( @@ -207,8 +203,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominuei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i64.nxv1i64( @@ -231,8 +227,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominuei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i64.nxv1i64( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominuei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i64.nxv2i64( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominuei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i64.nxv2i64( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominuei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i64.nxv4i64( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominuei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i64.nxv4i64( @@ -350,11 +346,9 @@ define @intrinsic_vamominu_v_nxv8i64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominuei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominuei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i64.nxv8i64( @@ -376,11 +370,9 @@ define @intrinsic_vamominu_mask_v_nxv8i64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominuei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominuei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i64.nxv8i64( @@ -403,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i32.nxv1i32( @@ -427,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i32.nxv1i32( @@ -451,8 +443,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i32.nxv2i32( @@ -475,8 +467,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i32.nxv2i32( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i32.nxv4i32( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i32.nxv4i32( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i32.nxv8i32( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i32.nxv8i32( @@ -594,11 +586,9 @@ define @intrinsic_vamominu_v_nxv16i32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv16i32.nxv16i32( @@ -620,11 +610,9 @@ define @intrinsic_vamominu_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv16i32.nxv16i32( @@ -647,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i64.nxv1i32( @@ -671,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominuei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i64.nxv1i32( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i64.nxv2i32( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominuei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i64.nxv2i32( @@ -743,8 +731,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i64.nxv4i32( @@ -767,8 +755,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominuei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i64.nxv4i32( @@ -790,11 +778,9 @@ define @intrinsic_vamominu_v_nxv8i64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominuei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i64.nxv8i32( @@ -816,11 +802,9 @@ define @intrinsic_vamominu_mask_v_nxv8i64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominuei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominuei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i64.nxv8i32( @@ -843,8 +827,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i32.nxv1i16( @@ -867,8 +851,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i32.nxv1i16( @@ -891,8 +875,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i32.nxv2i16( @@ -915,8 +899,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i32.nxv2i16( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i32.nxv4i16( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i32.nxv4i16( @@ -987,8 +971,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i32.nxv8i16( @@ -1011,8 +995,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i32.nxv8i16( @@ -1034,11 +1018,9 @@ define @intrinsic_vamominu_v_nxv16i32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv16i32.nxv16i16( @@ -1060,11 +1042,9 @@ define @intrinsic_vamominu_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv16i32.nxv16i16( @@ -1087,8 +1067,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i64.nxv1i16( @@ -1111,8 +1091,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominuei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i64.nxv1i16( @@ -1135,8 +1115,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i64.nxv2i16( @@ -1159,8 +1139,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominuei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i64.nxv2i16( @@ -1183,8 +1163,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i64.nxv4i16( @@ -1207,8 +1187,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominuei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i64.nxv4i16( @@ -1230,11 +1210,9 @@ define @intrinsic_vamominu_v_nxv8i64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominuei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i64.nxv8i16( @@ -1256,11 +1234,9 @@ define @intrinsic_vamominu_mask_v_nxv8i64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominuei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominuei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i64.nxv8i16( @@ -1283,8 +1259,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i32.nxv1i8( @@ -1307,8 +1283,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i32.nxv1i8( @@ -1331,8 +1307,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i32.nxv2i8( @@ -1355,8 +1331,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i32.nxv2i8( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i32.nxv4i8( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i32.nxv4i8( @@ -1427,8 +1403,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i32.nxv8i8( @@ -1451,8 +1427,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i32.nxv8i8( @@ -1474,11 +1450,9 @@ define @intrinsic_vamominu_v_nxv16i32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv16i32.nxv16i8( @@ -1500,11 +1474,9 @@ define @intrinsic_vamominu_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamominuei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv16i32.nxv16i8( @@ -1527,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv1i64.nxv1i8( @@ -1551,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamominuei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamominuei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv1i64.nxv1i8( @@ -1575,8 +1547,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv2i64.nxv2i8( @@ -1599,8 +1571,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamominuei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamominuei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv2i64.nxv2i8( @@ -1623,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vamominu_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv4i64.nxv4i8( @@ -1647,8 +1619,8 @@ ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamominuei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamominuei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv4i64.nxv4i8( @@ -1670,11 +1642,9 @@ define @intrinsic_vamominu_v_nxv8i64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamominu_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominuei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.nxv8i64.nxv8i8( @@ -1696,11 +1666,9 @@ define @intrinsic_vamominu_mask_v_nxv8i64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamominu_mask_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamominuei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamominuei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamominu.mask.nxv8i64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i32.nxv1i32( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i32.nxv1i32( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i32.nxv2i32( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i32.nxv2i32( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i32.nxv4i32( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i32.nxv4i32( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i32.nxv8i32( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i32.nxv8i32( @@ -202,11 +202,9 @@ define @intrinsic_vamoor_v_nxv16i32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv16i32.nxv16i32( @@ -228,11 +226,9 @@ define @intrinsic_vamoor_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv16i32.nxv16i32( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i32.nxv1i16( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i32.nxv1i16( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i32.nxv2i16( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i32.nxv2i16( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i32.nxv4i16( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i32.nxv4i16( @@ -399,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i32.nxv8i16( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i32.nxv8i16( @@ -446,11 +442,9 @@ define @intrinsic_vamoor_v_nxv16i32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv16i32.nxv16i16( @@ -472,11 +466,9 @@ define @intrinsic_vamoor_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv16i32.nxv16i16( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i32.nxv1i8( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i32.nxv1i8( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i32.nxv2i8( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i32.nxv2i8( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i32.nxv4i8( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i32.nxv4i8( @@ -643,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i32.nxv8i8( @@ -667,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i32.nxv8i8( @@ -690,11 +682,9 @@ define @intrinsic_vamoor_v_nxv16i32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv16i32.nxv16i8( @@ -716,11 +706,9 @@ define @intrinsic_vamoor_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv16i32.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoor-rv64.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i32.nxv1i64( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i32.nxv1i64( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoorei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i32.nxv2i64( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoorei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i32.nxv2i64( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoorei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i32.nxv4i64( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoorei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i32.nxv4i64( @@ -154,11 +154,9 @@ define @intrinsic_vamoor_v_nxv8i32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoorei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoorei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i32.nxv8i64( @@ -180,11 +178,9 @@ define @intrinsic_vamoor_mask_v_nxv8i32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoorei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoorei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i32.nxv8i64( @@ -207,8 +203,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoorei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i64.nxv1i64( @@ -231,8 +227,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoorei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i64.nxv1i64( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoorei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i64.nxv2i64( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoorei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i64.nxv2i64( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoorei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i64.nxv4i64( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoorei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i64.nxv4i64( @@ -350,11 +346,9 @@ define @intrinsic_vamoor_v_nxv8i64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoorei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoorei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i64.nxv8i64( @@ -376,11 +370,9 @@ define @intrinsic_vamoor_mask_v_nxv8i64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoorei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoorei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i64.nxv8i64( @@ -403,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i32.nxv1i32( @@ -427,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i32.nxv1i32( @@ -451,8 +443,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i32.nxv2i32( @@ -475,8 +467,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i32.nxv2i32( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i32.nxv4i32( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i32.nxv4i32( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i32.nxv8i32( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i32.nxv8i32( @@ -594,11 +586,9 @@ define @intrinsic_vamoor_v_nxv16i32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv16i32.nxv16i32( @@ -620,11 +610,9 @@ define @intrinsic_vamoor_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv16i32.nxv16i32( @@ -647,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i64.nxv1i32( @@ -671,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i64.nxv1i32( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i64.nxv2i32( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoorei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i64.nxv2i32( @@ -743,8 +731,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i64.nxv4i32( @@ -767,8 +755,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoorei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i64.nxv4i32( @@ -790,11 +778,9 @@ define @intrinsic_vamoor_v_nxv8i64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoorei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i64.nxv8i32( @@ -816,11 +802,9 @@ define @intrinsic_vamoor_mask_v_nxv8i64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoorei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoorei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i64.nxv8i32( @@ -843,8 +827,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i32.nxv1i16( @@ -867,8 +851,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i32.nxv1i16( @@ -891,8 +875,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i32.nxv2i16( @@ -915,8 +899,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i32.nxv2i16( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i32.nxv4i16( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i32.nxv4i16( @@ -987,8 +971,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i32.nxv8i16( @@ -1011,8 +995,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i32.nxv8i16( @@ -1034,11 +1018,9 @@ define @intrinsic_vamoor_v_nxv16i32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv16i32.nxv16i16( @@ -1060,11 +1042,9 @@ define @intrinsic_vamoor_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv16i32.nxv16i16( @@ -1087,8 +1067,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i64.nxv1i16( @@ -1111,8 +1091,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i64.nxv1i16( @@ -1135,8 +1115,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i64.nxv2i16( @@ -1159,8 +1139,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoorei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i64.nxv2i16( @@ -1183,8 +1163,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i64.nxv4i16( @@ -1207,8 +1187,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoorei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i64.nxv4i16( @@ -1230,11 +1210,9 @@ define @intrinsic_vamoor_v_nxv8i64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoorei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i64.nxv8i16( @@ -1256,11 +1234,9 @@ define @intrinsic_vamoor_mask_v_nxv8i64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoorei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoorei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i64.nxv8i16( @@ -1283,8 +1259,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i32.nxv1i8( @@ -1307,8 +1283,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i32.nxv1i8( @@ -1331,8 +1307,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i32.nxv2i8( @@ -1355,8 +1331,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i32.nxv2i8( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i32.nxv4i8( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i32.nxv4i8( @@ -1427,8 +1403,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i32.nxv8i8( @@ -1451,8 +1427,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i32.nxv8i8( @@ -1474,11 +1450,9 @@ define @intrinsic_vamoor_v_nxv16i32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv16i32.nxv16i8( @@ -1500,11 +1474,9 @@ define @intrinsic_vamoor_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoorei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv16i32.nxv16i8( @@ -1527,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv1i64.nxv1i8( @@ -1551,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv1i64.nxv1i8( @@ -1575,8 +1547,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv2i64.nxv2i8( @@ -1599,8 +1571,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoorei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoorei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv2i64.nxv2i8( @@ -1623,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vamoor_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv4i64.nxv4i8( @@ -1647,8 +1619,8 @@ ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoorei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoorei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv4i64.nxv4i8( @@ -1670,11 +1642,9 @@ define @intrinsic_vamoor_v_nxv8i64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoor_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoorei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.nxv8i64.nxv8i8( @@ -1696,11 +1666,9 @@ define @intrinsic_vamoor_mask_v_nxv8i64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoor_mask_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoorei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoorei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoor.mask.nxv8i64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv32.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i32.nxv1i32( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i32( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i32.nxv2i32( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i32( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i32.nxv4i32( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i32( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i32.nxv8i32( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i32( @@ -202,11 +202,9 @@ define @intrinsic_vamoswap_v_nxv16i32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16i32.nxv16i32( @@ -228,11 +226,9 @@ define @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i32( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f32.nxv1i32( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i32( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f32.nxv2i32( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i32( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f32.nxv4i32( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i32( @@ -399,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f32.nxv8i32( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i32( @@ -446,11 +442,9 @@ define @intrinsic_vamoswap_v_nxv16f32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16f32.nxv16i32( @@ -472,11 +466,9 @@ define @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i32( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f64.nxv1i32( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i32( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f64.nxv2i32( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i32( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f64.nxv4i32( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i32( @@ -642,11 +634,9 @@ define @intrinsic_vamoswap_v_nxv8f64_nxv8i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f64.nxv8i32( @@ -668,11 +658,9 @@ define @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i32( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i32.nxv1i16( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i16( @@ -743,8 +731,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i32.nxv2i16( @@ -767,8 +755,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i16( @@ -791,8 +779,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i32.nxv4i16( @@ -815,8 +803,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i16( @@ -839,8 +827,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i32.nxv8i16( @@ -863,8 +851,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i16( @@ -886,11 +874,9 @@ define @intrinsic_vamoswap_v_nxv16i32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16i32.nxv16i16( @@ -912,11 +898,9 @@ define @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i16( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f32.nxv1i16( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i16( @@ -987,8 +971,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f32.nxv2i16( @@ -1011,8 +995,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i16( @@ -1035,8 +1019,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f32.nxv4i16( @@ -1059,8 +1043,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i16( @@ -1083,8 +1067,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f32.nxv8i16( @@ -1107,8 +1091,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i16( @@ -1130,11 +1114,9 @@ define @intrinsic_vamoswap_v_nxv16f32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16f32.nxv16i16( @@ -1156,11 +1138,9 @@ define @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i16( @@ -1183,8 +1163,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f64.nxv1i16( @@ -1207,8 +1187,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i16( @@ -1231,8 +1211,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f64.nxv2i16( @@ -1255,8 +1235,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i16( @@ -1279,8 +1259,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f64.nxv4i16( @@ -1303,8 +1283,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i16( @@ -1326,11 +1306,9 @@ define @intrinsic_vamoswap_v_nxv8f64_nxv8i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f64.nxv8i16( @@ -1352,11 +1330,9 @@ define @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i16( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i32.nxv1i8( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i8( @@ -1427,8 +1403,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i32.nxv2i8( @@ -1451,8 +1427,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i8( @@ -1475,8 +1451,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i32.nxv4i8( @@ -1499,8 +1475,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i8( @@ -1523,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i32.nxv8i8( @@ -1547,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i8( @@ -1570,11 +1546,9 @@ define @intrinsic_vamoswap_v_nxv16i32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16i32.nxv16i8( @@ -1596,11 +1570,9 @@ define @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i8( @@ -1623,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f32.nxv1i8( @@ -1647,8 +1619,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i8( @@ -1671,8 +1643,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f32.nxv2i8( @@ -1695,8 +1667,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i8( @@ -1719,8 +1691,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f32.nxv4i8( @@ -1743,8 +1715,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i8( @@ -1767,8 +1739,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f32.nxv8i8( @@ -1791,8 +1763,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i8( @@ -1814,11 +1786,9 @@ define @intrinsic_vamoswap_v_nxv16f32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16f32.nxv16i8( @@ -1840,11 +1810,9 @@ define @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i8( @@ -1867,8 +1835,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f64.nxv1i8( @@ -1891,8 +1859,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i8( @@ -1915,8 +1883,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f64.nxv2i8( @@ -1939,8 +1907,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i8( @@ -1963,8 +1931,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f64.nxv4i8( @@ -1987,8 +1955,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i8( @@ -2010,11 +1978,9 @@ define @intrinsic_vamoswap_v_nxv8f64_nxv8i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f64.nxv8i8( @@ -2036,11 +2002,9 @@ define @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoswap-rv64.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i32.nxv1i64( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i64( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoswapei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i32.nxv2i64( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoswapei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i64( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoswapei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i32.nxv4i64( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoswapei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i64( @@ -154,11 +154,9 @@ define @intrinsic_vamoswap_v_nxv8i32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoswapei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i32.nxv8i64( @@ -180,11 +178,9 @@ define @intrinsic_vamoswap_mask_v_nxv8i32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoswapei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i64( @@ -207,8 +203,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i64.nxv1i64( @@ -231,8 +227,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i64( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i64.nxv2i64( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i64( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i64.nxv4i64( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i64( @@ -350,11 +346,9 @@ define @intrinsic_vamoswap_v_nxv8i64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i64.nxv8i64( @@ -376,11 +370,9 @@ define @intrinsic_vamoswap_mask_v_nxv8i64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i64( @@ -403,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f32.nxv1i64( @@ -427,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i64( @@ -451,8 +443,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoswapei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f32.nxv2i64( @@ -475,8 +467,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoswapei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i64( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoswapei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f32.nxv4i64( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoswapei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i64( @@ -546,11 +538,9 @@ define @intrinsic_vamoswap_v_nxv8f32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoswapei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f32.nxv8i64( @@ -572,11 +562,9 @@ define @intrinsic_vamoswap_mask_v_nxv8f32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoswapei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i64( @@ -599,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f64.nxv1i64( @@ -623,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i64( @@ -647,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f64.nxv2i64( @@ -671,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i64( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f64.nxv4i64( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i64( @@ -742,11 +730,9 @@ define @intrinsic_vamoswap_v_nxv8f64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f64.nxv8i64( @@ -768,11 +754,9 @@ define @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i64( @@ -795,8 +779,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i32.nxv1i32( @@ -819,8 +803,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i32( @@ -843,8 +827,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i32.nxv2i32( @@ -867,8 +851,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i32( @@ -891,8 +875,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i32.nxv4i32( @@ -915,8 +899,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i32( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i32.nxv8i32( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i32( @@ -986,11 +970,9 @@ define @intrinsic_vamoswap_v_nxv16i32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16i32.nxv16i32( @@ -1012,11 +994,9 @@ define @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i32( @@ -1039,8 +1019,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i64.nxv1i32( @@ -1063,8 +1043,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i32( @@ -1087,8 +1067,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i64.nxv2i32( @@ -1111,8 +1091,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i32( @@ -1135,8 +1115,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i64.nxv4i32( @@ -1159,8 +1139,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i32( @@ -1182,11 +1162,9 @@ define @intrinsic_vamoswap_v_nxv8i64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i64.nxv8i32( @@ -1208,11 +1186,9 @@ define @intrinsic_vamoswap_mask_v_nxv8i64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i32( @@ -1235,8 +1211,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f32.nxv1i32( @@ -1259,8 +1235,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i32( @@ -1283,8 +1259,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f32.nxv2i32( @@ -1307,8 +1283,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i32( @@ -1331,8 +1307,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f32.nxv4i32( @@ -1355,8 +1331,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i32( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f32.nxv8i32( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i32( @@ -1426,11 +1402,9 @@ define @intrinsic_vamoswap_v_nxv16f32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16f32.nxv16i32( @@ -1452,11 +1426,9 @@ define @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i32( @@ -1479,8 +1451,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f64.nxv1i32( @@ -1503,8 +1475,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i32( @@ -1527,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f64.nxv2i32( @@ -1551,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i32( @@ -1575,8 +1547,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f64.nxv4i32( @@ -1599,8 +1571,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i32( @@ -1622,11 +1594,9 @@ define @intrinsic_vamoswap_v_nxv8f64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f64.nxv8i32( @@ -1648,11 +1618,9 @@ define @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i32( @@ -1675,8 +1643,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i32.nxv1i16( @@ -1699,8 +1667,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i16( @@ -1723,8 +1691,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i32.nxv2i16( @@ -1747,8 +1715,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i16( @@ -1771,8 +1739,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i32.nxv4i16( @@ -1795,8 +1763,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i16( @@ -1819,8 +1787,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i32.nxv8i16( @@ -1843,8 +1811,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i16( @@ -1866,11 +1834,9 @@ define @intrinsic_vamoswap_v_nxv16i32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16i32.nxv16i16( @@ -1892,11 +1858,9 @@ define @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i16( @@ -1919,8 +1883,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i64.nxv1i16( @@ -1943,8 +1907,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i16( @@ -1967,8 +1931,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i64.nxv2i16( @@ -1991,8 +1955,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i16( @@ -2015,8 +1979,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i64.nxv4i16( @@ -2039,8 +2003,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i16( @@ -2062,11 +2026,9 @@ define @intrinsic_vamoswap_v_nxv8i64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i64.nxv8i16( @@ -2088,11 +2050,9 @@ define @intrinsic_vamoswap_mask_v_nxv8i64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i16( @@ -2115,8 +2075,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f32.nxv1i16( @@ -2139,8 +2099,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i16( @@ -2163,8 +2123,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f32.nxv2i16( @@ -2187,8 +2147,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i16( @@ -2211,8 +2171,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f32.nxv4i16( @@ -2235,8 +2195,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i16( @@ -2259,8 +2219,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f32.nxv8i16( @@ -2283,8 +2243,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i16( @@ -2306,11 +2266,9 @@ define @intrinsic_vamoswap_v_nxv16f32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16f32.nxv16i16( @@ -2332,11 +2290,9 @@ define @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i16( @@ -2359,8 +2315,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f64.nxv1i16( @@ -2383,8 +2339,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i16( @@ -2407,8 +2363,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f64.nxv2i16( @@ -2431,8 +2387,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i16( @@ -2455,8 +2411,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f64.nxv4i16( @@ -2479,8 +2435,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i16( @@ -2502,11 +2458,9 @@ define @intrinsic_vamoswap_v_nxv8f64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f64.nxv8i16( @@ -2528,11 +2482,9 @@ define @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i16( @@ -2555,8 +2507,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i32.nxv1i8( @@ -2579,8 +2531,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i32.nxv1i8( @@ -2603,8 +2555,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i32.nxv2i8( @@ -2627,8 +2579,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i32.nxv2i8( @@ -2651,8 +2603,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i32.nxv4i8( @@ -2675,8 +2627,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i32.nxv4i8( @@ -2699,8 +2651,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i32.nxv8i8( @@ -2723,8 +2675,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i32.nxv8i8( @@ -2746,11 +2698,9 @@ define @intrinsic_vamoswap_v_nxv16i32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16i32.nxv16i8( @@ -2772,11 +2722,9 @@ define @intrinsic_vamoswap_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16i32.nxv16i8( @@ -2799,8 +2747,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1i64.nxv1i8( @@ -2823,8 +2771,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1i64.nxv1i8( @@ -2847,8 +2795,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2i64.nxv2i8( @@ -2871,8 +2819,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2i64.nxv2i8( @@ -2895,8 +2843,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4i64.nxv4i8( @@ -2919,8 +2867,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4i64.nxv4i8( @@ -2942,11 +2890,9 @@ define @intrinsic_vamoswap_v_nxv8i64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8i64.nxv8i8( @@ -2968,11 +2914,9 @@ define @intrinsic_vamoswap_mask_v_nxv8i64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8i64.nxv8i8( @@ -2995,8 +2939,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f32.nxv1i8( @@ -3019,8 +2963,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f32.nxv1i8( @@ -3043,8 +2987,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f32.nxv2i8( @@ -3067,8 +3011,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f32.nxv2i8( @@ -3091,8 +3035,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f32.nxv4i8( @@ -3115,8 +3059,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f32.nxv4i8( @@ -3139,8 +3083,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f32.nxv8i8( @@ -3163,8 +3107,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f32.nxv8i8( @@ -3186,11 +3130,9 @@ define @intrinsic_vamoswap_v_nxv16f32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv16f32.nxv16i8( @@ -3212,11 +3154,9 @@ define @intrinsic_vamoswap_mask_v_nxv16f32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv16f32.nxv16i8( @@ -3239,8 +3179,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv1f64.nxv1i8( @@ -3263,8 +3203,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoswapei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoswapei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv1f64.nxv1i8( @@ -3287,8 +3227,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv2f64.nxv2i8( @@ -3311,8 +3251,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoswapei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoswapei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv2f64.nxv2i8( @@ -3335,8 +3275,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_v_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv4f64.nxv4i8( @@ -3359,8 +3299,8 @@ ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoswapei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoswapei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv4f64.nxv4i8( @@ -3382,11 +3322,9 @@ define @intrinsic_vamoswap_v_nxv8f64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_v_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.nxv8f64.nxv8i8( @@ -3408,11 +3346,9 @@ define @intrinsic_vamoswap_mask_v_nxv8f64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoswap_mask_v_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoswapei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoswapei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoswap.mask.nxv8f64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv32.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i32.nxv1i32( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i32( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i32.nxv2i32( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i32( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i32.nxv4i32( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i32( @@ -155,8 +155,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i32.nxv8i32( @@ -179,8 +179,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i32( @@ -202,11 +202,9 @@ define @intrinsic_vamoxor_v_nxv16i32_nxv16i32( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv16i32.nxv16i32( @@ -228,11 +226,9 @@ define @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i32( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i32.nxv1i16( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i16( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i32.nxv2i16( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i16( @@ -351,8 +347,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i32.nxv4i16( @@ -375,8 +371,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i16( @@ -399,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i32.nxv8i16( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i16( @@ -446,11 +442,9 @@ define @intrinsic_vamoxor_v_nxv16i32_nxv16i16( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv16i32.nxv16i16( @@ -472,11 +466,9 @@ define @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i16( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i32.nxv1i8( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i8( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i32.nxv2i8( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i8( @@ -595,8 +587,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i32.nxv4i8( @@ -619,8 +611,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i8( @@ -643,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i32.nxv8i8( @@ -667,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i8( @@ -690,11 +682,9 @@ define @intrinsic_vamoxor_v_nxv16i32_nxv16i8( *%0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv16i32.nxv16i8( @@ -716,11 +706,9 @@ define @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vamoxor-rv64.ll @@ -11,8 +11,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i32.nxv1i64( @@ -35,8 +35,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i64( @@ -59,8 +59,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoxorei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i32.nxv2i64( @@ -83,8 +83,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv1r.v v16, v18 +; CHECK-NEXT: vamoxorei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i64( @@ -107,8 +107,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoxorei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i32.nxv4i64( @@ -131,8 +131,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv2r.v v16, v20 +; CHECK-NEXT: vamoxorei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i64( @@ -154,11 +154,9 @@ define @intrinsic_vamoxor_v_nxv8i32_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei64.v v28, (a0), v16, v28 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoxorei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i32.nxv8i64( @@ -180,11 +178,9 @@ define @intrinsic_vamoxor_mask_v_nxv8i32_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei64.v v28, (a0), v16, v28, v0.t -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vamoxorei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i64( @@ -207,8 +203,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoxorei64.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei64.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i64.nxv1i64( @@ -231,8 +227,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoxorei64.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei64.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i64( @@ -255,8 +251,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoxorei64.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei64.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i64.nxv2i64( @@ -279,8 +275,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoxorei64.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei64.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i64( @@ -303,8 +299,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoxorei64.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei64.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i64.nxv4i64( @@ -327,8 +323,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoxorei64.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei64.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i64( @@ -350,11 +346,9 @@ define @intrinsic_vamoxor_v_nxv8i64_nxv8i64( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoxorei64.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoxorei64.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i64.nxv8i64( @@ -376,11 +370,9 @@ define @intrinsic_vamoxor_mask_v_nxv8i64_nxv8i64( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoxorei64.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoxorei64.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i64( @@ -403,8 +395,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i32.nxv1i32( @@ -427,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i32( @@ -451,8 +443,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i32.nxv2i32( @@ -475,8 +467,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i32( @@ -499,8 +491,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i32.nxv4i32( @@ -523,8 +515,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i32( @@ -547,8 +539,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i32.nxv8i32( @@ -571,8 +563,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i32( @@ -594,11 +586,9 @@ define @intrinsic_vamoxor_v_nxv16i32_nxv16i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv16i32.nxv16i32( @@ -620,11 +610,9 @@ define @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i32( @@ -647,8 +635,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i64.nxv1i32( @@ -671,8 +659,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoxorei32.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei32.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i32( @@ -695,8 +683,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei32.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i64.nxv2i32( @@ -719,8 +707,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoxorei32.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei32.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i32( @@ -743,8 +731,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei32.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i64.nxv4i32( @@ -767,8 +755,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoxorei32.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei32.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i32( @@ -790,11 +778,9 @@ define @intrinsic_vamoxor_v_nxv8i64_nxv8i32( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoxorei32.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i64.nxv8i32( @@ -816,11 +802,9 @@ define @intrinsic_vamoxor_mask_v_nxv8i64_nxv8i32( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoxorei32.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoxorei32.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i32( @@ -843,8 +827,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i32.nxv1i16( @@ -867,8 +851,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i16( @@ -891,8 +875,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i32.nxv2i16( @@ -915,8 +899,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i16( @@ -939,8 +923,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i32.nxv4i16( @@ -963,8 +947,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i16( @@ -987,8 +971,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i32.nxv8i16( @@ -1011,8 +995,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i16( @@ -1034,11 +1018,9 @@ define @intrinsic_vamoxor_v_nxv16i32_nxv16i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv16i32.nxv16i16( @@ -1060,11 +1042,9 @@ define @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i16( @@ -1087,8 +1067,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i64.nxv1i16( @@ -1111,8 +1091,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoxorei16.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei16.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i16( @@ -1135,8 +1115,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei16.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i64.nxv2i16( @@ -1159,8 +1139,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoxorei16.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei16.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i16( @@ -1183,8 +1163,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei16.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i64.nxv4i16( @@ -1207,8 +1187,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoxorei16.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei16.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i16( @@ -1230,11 +1210,9 @@ define @intrinsic_vamoxor_v_nxv8i64_nxv8i16( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoxorei16.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i64.nxv8i16( @@ -1256,11 +1234,9 @@ define @intrinsic_vamoxor_mask_v_nxv8i64_nxv8i16( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoxorei16.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoxorei16.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i16( @@ -1283,8 +1259,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i32.nxv1i8( @@ -1307,8 +1283,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i32.nxv1i8( @@ -1331,8 +1307,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i32.nxv2i8( @@ -1355,8 +1331,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i32.nxv2i8( @@ -1379,8 +1355,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i32.nxv4i8( @@ -1403,8 +1379,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i32.nxv4i8( @@ -1427,8 +1403,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i32.nxv8i8( @@ -1451,8 +1427,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i32.nxv8i8( @@ -1474,11 +1450,9 @@ define @intrinsic_vamoxor_v_nxv16i32_nxv16i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv16i32.nxv16i8( @@ -1500,11 +1474,9 @@ define @intrinsic_vamoxor_mask_v_nxv16i32_nxv16i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vamoxorei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv16i32.nxv16i8( @@ -1527,8 +1499,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17 -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9 +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv1i64.nxv1i8( @@ -1551,8 +1523,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vamoxorei8.v v17, (a0), v16, v17, v0.t -; CHECK-NEXT: vmv1r.v v16, v17 +; CHECK-NEXT: vamoxorei8.v v9, (a0), v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv1i64.nxv1i8( @@ -1575,8 +1547,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18 -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei8.v v10, (a0), v8, v10 +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv2i64.nxv2i8( @@ -1599,8 +1571,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vamoxorei8.v v18, (a0), v16, v18, v0.t -; CHECK-NEXT: vmv2r.v v16, v18 +; CHECK-NEXT: vamoxorei8.v v10, (a0), v8, v10, v0.t +; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv2i64.nxv2i8( @@ -1623,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20 -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei8.v v12, (a0), v8, v12 +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv4i64.nxv4i8( @@ -1647,8 +1619,8 @@ ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vamoxorei8.v v20, (a0), v16, v20, v0.t -; CHECK-NEXT: vmv4r.v v16, v20 +; CHECK-NEXT: vamoxorei8.v v12, (a0), v8, v12, v0.t +; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv4i64.nxv4i8( @@ -1670,11 +1642,9 @@ define @intrinsic_vamoxor_v_nxv8i64_nxv8i8( *%0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoxorei8.v v16, (a0), v8, v16 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.nxv8i64.nxv8i8( @@ -1696,11 +1666,9 @@ define @intrinsic_vamoxor_mask_v_nxv8i64_nxv8i8( *%0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vamoxor_mask_v_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vamoxorei8.v v8, (a0), v16, v8, v0.t -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vamoxorei8.v v16, (a0), v8, v16, v0.t +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vamoxor.mask.nxv8i64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vand.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vand.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vand.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vand.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vand.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vand.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vand.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vand.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vand.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vand.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vand_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vand_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vand_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vand_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vand_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vand.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vand_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vand.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vand_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vand.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vand_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vand_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vand_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vand_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vand.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vand_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vand.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vand_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vand.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vand_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vand_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vand_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vand.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vand_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vand.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vand_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vand.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vand_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vand_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vand_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vand_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vand_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vand.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vand_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vand.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vand_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vand.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vand_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vand_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vand_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vand_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vand.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vand_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vand.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vand_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vand.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vand_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vand_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vand_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vand.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vand_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vand.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vand_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vand.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vand.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vand.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vand.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vand.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vand.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vand.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vand.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vand.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vand.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vand.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vand_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vand_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vand.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vand_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vand_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vand.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vand_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vand_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vand.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vand_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vand.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vand.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vand_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vand_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vand_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vand_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vand_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vand.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vand_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vand.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vand_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vand.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vand_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vand_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vand_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vand_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vand.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vand_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vand.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vand_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vand.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vand_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vand_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vand_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vand.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vand_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vand.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vand_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vand.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vand_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vand.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vand_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vand.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vand_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vand.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vand_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vand_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vand.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vand.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vand.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vand.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vand_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vand_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vand_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vand_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vand_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vand.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vand_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vand.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vand_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vand.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vand_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vand_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vand_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vand_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vand.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vand_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vand.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vand_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vand.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vand_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vand_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vand_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vand.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vand_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vand.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vand_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vand.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vand_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vand_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vand.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vand_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vand_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vand.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vand_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vand_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vand.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vand_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vand_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vand.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vand.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vand_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vand.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vand.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vand_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vand_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -27,7 +27,7 @@ ; CHECK-LABEL: vand_vi_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -39,7 +39,7 @@ ; CHECK-LABEL: vand_vi_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -64,7 +64,7 @@ ; CHECK-LABEL: vand_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -74,7 +74,7 @@ ; CHECK-LABEL: vand_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -86,7 +86,7 @@ ; CHECK-LABEL: vand_vi_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK-LABEL: vand_vi_nxv2i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -123,7 +123,7 @@ ; CHECK-LABEL: vand_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -133,7 +133,7 @@ ; CHECK-LABEL: vand_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vand_vi_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vand_vi_nxv4i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -170,7 +170,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK-LABEL: vand_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -192,7 +192,7 @@ ; CHECK-LABEL: vand_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -204,7 +204,7 @@ ; CHECK-LABEL: vand_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -216,7 +216,7 @@ ; CHECK-LABEL: vand_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -229,7 +229,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -241,7 +241,7 @@ ; CHECK-LABEL: vand_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v18 +; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -251,7 +251,7 @@ ; CHECK-LABEL: vand_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -263,7 +263,7 @@ ; CHECK-LABEL: vand_vi_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -275,7 +275,7 @@ ; CHECK-LABEL: vand_vi_nxv16i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -288,7 +288,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +300,7 @@ ; CHECK-LABEL: vand_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v20 +; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -310,7 +310,7 @@ ; CHECK-LABEL: vand_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -322,7 +322,7 @@ ; CHECK-LABEL: vand_vi_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,7 +334,7 @@ ; CHECK-LABEL: vand_vi_nxv32i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -347,7 +347,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -358,9 +358,8 @@ define @vand_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vand_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vand.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -370,7 +369,7 @@ ; CHECK-LABEL: vand_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -382,7 +381,7 @@ ; CHECK-LABEL: vand_vi_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -394,7 +393,7 @@ ; CHECK-LABEL: vand_vi_nxv64i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -407,7 +406,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -419,7 +418,7 @@ ; CHECK-LABEL: vand_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -429,7 +428,7 @@ ; CHECK-LABEL: vand_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -441,7 +440,7 @@ ; CHECK-LABEL: vand_vi_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -453,7 +452,7 @@ ; CHECK-LABEL: vand_vi_nxv1i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -466,7 +465,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -478,7 +477,7 @@ ; CHECK-LABEL: vand_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -488,7 +487,7 @@ ; CHECK-LABEL: vand_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -500,7 +499,7 @@ ; CHECK-LABEL: vand_vi_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -512,7 +511,7 @@ ; CHECK-LABEL: vand_vi_nxv2i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -525,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -537,7 +536,7 @@ ; CHECK-LABEL: vand_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -547,7 +546,7 @@ ; CHECK-LABEL: vand_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -559,7 +558,7 @@ ; CHECK-LABEL: vand_vi_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -571,7 +570,7 @@ ; CHECK-LABEL: vand_vi_nxv4i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -584,7 +583,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -596,7 +595,7 @@ ; CHECK-LABEL: vand_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v18 +; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -606,7 +605,7 @@ ; CHECK-LABEL: vand_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -618,7 +617,7 @@ ; CHECK-LABEL: vand_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -630,7 +629,7 @@ ; CHECK-LABEL: vand_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -643,7 +642,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -655,7 +654,7 @@ ; CHECK-LABEL: vand_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v20 +; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -665,7 +664,7 @@ ; CHECK-LABEL: vand_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -677,7 +676,7 @@ ; CHECK-LABEL: vand_vi_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -689,7 +688,7 @@ ; CHECK-LABEL: vand_vi_nxv16i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -702,7 +701,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -713,9 +712,8 @@ define @vand_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vand_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vand.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -725,7 +723,7 @@ ; CHECK-LABEL: vand_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -737,7 +735,7 @@ ; CHECK-LABEL: vand_vi_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -749,7 +747,7 @@ ; CHECK-LABEL: vand_vi_nxv32i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -762,7 +760,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -774,7 +772,7 @@ ; CHECK-LABEL: vand_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -784,7 +782,7 @@ ; CHECK-LABEL: vand_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -796,7 +794,7 @@ ; CHECK-LABEL: vand_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -808,7 +806,7 @@ ; CHECK-LABEL: vand_vi_nxv1i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -821,7 +819,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -833,7 +831,7 @@ ; CHECK-LABEL: vand_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -843,7 +841,7 @@ ; CHECK-LABEL: vand_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -855,7 +853,7 @@ ; CHECK-LABEL: vand_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -867,7 +865,7 @@ ; CHECK-LABEL: vand_vi_nxv2i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -880,7 +878,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -892,7 +890,7 @@ ; CHECK-LABEL: vand_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v18 +; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -902,7 +900,7 @@ ; CHECK-LABEL: vand_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -914,7 +912,7 @@ ; CHECK-LABEL: vand_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -926,7 +924,7 @@ ; CHECK-LABEL: vand_vi_nxv4i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -939,7 +937,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -951,7 +949,7 @@ ; CHECK-LABEL: vand_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v20 +; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -961,7 +959,7 @@ ; CHECK-LABEL: vand_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -973,7 +971,7 @@ ; CHECK-LABEL: vand_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -985,7 +983,7 @@ ; CHECK-LABEL: vand_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -998,7 +996,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1009,9 +1007,8 @@ define @vand_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vand_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vand.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1021,7 +1018,7 @@ ; CHECK-LABEL: vand_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1033,7 +1030,7 @@ ; CHECK-LABEL: vand_vi_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1045,7 +1042,7 @@ ; CHECK-LABEL: vand_vi_nxv16i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1058,7 +1055,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1070,7 +1067,7 @@ ; CHECK-LABEL: vand_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1087,7 +1084,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vand.vv v16, v16, v25 +; CHECK-NEXT: vand.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1099,7 +1096,7 @@ ; CHECK-LABEL: vand_vi_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1111,7 +1108,7 @@ ; CHECK-LABEL: vand_vi_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1124,7 +1121,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1136,7 +1133,7 @@ ; CHECK-LABEL: vand_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v18 +; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1153,7 +1150,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vand.vv v16, v16, v26 +; CHECK-NEXT: vand.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1165,7 +1162,7 @@ ; CHECK-LABEL: vand_vi_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1177,7 +1174,7 @@ ; CHECK-LABEL: vand_vi_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1190,7 +1187,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1202,7 +1199,7 @@ ; CHECK-LABEL: vand_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v20 +; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1215,11 +1212,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vand.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vand.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1231,7 +1228,7 @@ ; CHECK-LABEL: vand_vi_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1243,7 +1240,7 @@ ; CHECK-LABEL: vand_vi_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1256,7 +1253,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1267,9 +1264,8 @@ define @vand_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vand_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vand.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1279,14 +1275,14 @@ ; CHECK-LABEL: vand_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vand.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1298,7 +1294,7 @@ ; CHECK-LABEL: vand_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1310,7 +1306,7 @@ ; CHECK-LABEL: vand_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1323,7 +1319,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vand_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vand_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -27,7 +27,7 @@ ; CHECK-LABEL: vand_vi_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -39,7 +39,7 @@ ; CHECK-LABEL: vand_vi_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -64,7 +64,7 @@ ; CHECK-LABEL: vand_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -74,7 +74,7 @@ ; CHECK-LABEL: vand_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -86,7 +86,7 @@ ; CHECK-LABEL: vand_vi_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK-LABEL: vand_vi_nxv2i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -123,7 +123,7 @@ ; CHECK-LABEL: vand_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -133,7 +133,7 @@ ; CHECK-LABEL: vand_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vand_vi_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vand_vi_nxv4i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -170,7 +170,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK-LABEL: vand_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -192,7 +192,7 @@ ; CHECK-LABEL: vand_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -204,7 +204,7 @@ ; CHECK-LABEL: vand_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -216,7 +216,7 @@ ; CHECK-LABEL: vand_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -229,7 +229,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -241,7 +241,7 @@ ; CHECK-LABEL: vand_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v18 +; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -251,7 +251,7 @@ ; CHECK-LABEL: vand_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -263,7 +263,7 @@ ; CHECK-LABEL: vand_vi_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -275,7 +275,7 @@ ; CHECK-LABEL: vand_vi_nxv16i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -288,7 +288,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +300,7 @@ ; CHECK-LABEL: vand_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v20 +; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -310,7 +310,7 @@ ; CHECK-LABEL: vand_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -322,7 +322,7 @@ ; CHECK-LABEL: vand_vi_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,7 +334,7 @@ ; CHECK-LABEL: vand_vi_nxv32i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -347,7 +347,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -358,9 +358,8 @@ define @vand_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vand_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vand.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -370,7 +369,7 @@ ; CHECK-LABEL: vand_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -382,7 +381,7 @@ ; CHECK-LABEL: vand_vi_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i8 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -394,7 +393,7 @@ ; CHECK-LABEL: vand_vi_nxv64i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -407,7 +406,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -419,7 +418,7 @@ ; CHECK-LABEL: vand_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -429,7 +428,7 @@ ; CHECK-LABEL: vand_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -441,7 +440,7 @@ ; CHECK-LABEL: vand_vi_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -453,7 +452,7 @@ ; CHECK-LABEL: vand_vi_nxv1i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -466,7 +465,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -478,7 +477,7 @@ ; CHECK-LABEL: vand_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -488,7 +487,7 @@ ; CHECK-LABEL: vand_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -500,7 +499,7 @@ ; CHECK-LABEL: vand_vi_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -512,7 +511,7 @@ ; CHECK-LABEL: vand_vi_nxv2i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -525,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -537,7 +536,7 @@ ; CHECK-LABEL: vand_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -547,7 +546,7 @@ ; CHECK-LABEL: vand_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -559,7 +558,7 @@ ; CHECK-LABEL: vand_vi_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -571,7 +570,7 @@ ; CHECK-LABEL: vand_vi_nxv4i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -584,7 +583,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -596,7 +595,7 @@ ; CHECK-LABEL: vand_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v18 +; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -606,7 +605,7 @@ ; CHECK-LABEL: vand_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -618,7 +617,7 @@ ; CHECK-LABEL: vand_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -630,7 +629,7 @@ ; CHECK-LABEL: vand_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -643,7 +642,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -655,7 +654,7 @@ ; CHECK-LABEL: vand_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v20 +; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -665,7 +664,7 @@ ; CHECK-LABEL: vand_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -677,7 +676,7 @@ ; CHECK-LABEL: vand_vi_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -689,7 +688,7 @@ ; CHECK-LABEL: vand_vi_nxv16i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -702,7 +701,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -713,9 +712,8 @@ define @vand_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vand_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vand.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -725,7 +723,7 @@ ; CHECK-LABEL: vand_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -737,7 +735,7 @@ ; CHECK-LABEL: vand_vi_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i16 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -749,7 +747,7 @@ ; CHECK-LABEL: vand_vi_nxv32i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -762,7 +760,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -774,7 +772,7 @@ ; CHECK-LABEL: vand_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -784,7 +782,7 @@ ; CHECK-LABEL: vand_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -796,7 +794,7 @@ ; CHECK-LABEL: vand_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -808,7 +806,7 @@ ; CHECK-LABEL: vand_vi_nxv1i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -821,7 +819,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -833,7 +831,7 @@ ; CHECK-LABEL: vand_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -843,7 +841,7 @@ ; CHECK-LABEL: vand_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -855,7 +853,7 @@ ; CHECK-LABEL: vand_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -867,7 +865,7 @@ ; CHECK-LABEL: vand_vi_nxv2i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -880,7 +878,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -892,7 +890,7 @@ ; CHECK-LABEL: vand_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v18 +; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -902,7 +900,7 @@ ; CHECK-LABEL: vand_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -914,7 +912,7 @@ ; CHECK-LABEL: vand_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -926,7 +924,7 @@ ; CHECK-LABEL: vand_vi_nxv4i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -939,7 +937,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -951,7 +949,7 @@ ; CHECK-LABEL: vand_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v20 +; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -961,7 +959,7 @@ ; CHECK-LABEL: vand_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -973,7 +971,7 @@ ; CHECK-LABEL: vand_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -985,7 +983,7 @@ ; CHECK-LABEL: vand_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -998,7 +996,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1009,9 +1007,8 @@ define @vand_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vand_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vand.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1021,7 +1018,7 @@ ; CHECK-LABEL: vand_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1033,7 +1030,7 @@ ; CHECK-LABEL: vand_vi_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i32 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1045,7 +1042,7 @@ ; CHECK-LABEL: vand_vi_nxv16i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1058,7 +1055,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1070,7 +1067,7 @@ ; CHECK-LABEL: vand_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v17 +; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1080,7 +1077,7 @@ ; CHECK-LABEL: vand_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1092,7 +1089,7 @@ ; CHECK-LABEL: vand_vi_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1104,7 +1101,7 @@ ; CHECK-LABEL: vand_vi_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1117,7 +1114,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1129,7 +1126,7 @@ ; CHECK-LABEL: vand_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v18 +; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1139,7 +1136,7 @@ ; CHECK-LABEL: vand_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1151,7 +1148,7 @@ ; CHECK-LABEL: vand_vi_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1163,7 +1160,7 @@ ; CHECK-LABEL: vand_vi_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1176,7 +1173,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1188,7 +1185,7 @@ ; CHECK-LABEL: vand_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vv v16, v16, v20 +; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1198,7 +1195,7 @@ ; CHECK-LABEL: vand_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1210,7 +1207,7 @@ ; CHECK-LABEL: vand_vi_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1222,7 +1219,7 @@ ; CHECK-LABEL: vand_vi_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1235,7 +1232,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1246,9 +1243,8 @@ define @vand_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vand_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vand.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -1258,7 +1254,7 @@ ; CHECK-LABEL: vand_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1270,7 +1266,7 @@ ; CHECK-LABEL: vand_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, -10 +; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret %head = insertelement undef, i64 -10, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1282,7 +1278,7 @@ ; CHECK-LABEL: vand_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vand.vi v16, v16, 8 +; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1295,7 +1291,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vand.vx v16, v16, a0 +; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vasub.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vasub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vasub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vasub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vasub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vasub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vasub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vasub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vasub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vasub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vasub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vasub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vasub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vasub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vasub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vasub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vasub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vasub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vasub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vasub.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vasub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vasub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vasub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vasub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vasub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vasub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vasub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vasub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vasub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vasub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vasub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vasub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vasub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vasub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vasub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vasub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vasub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vasub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vasub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vasub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vasub_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vasub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasub.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vasub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasub.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vasubu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vasubu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vasubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vasubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vasubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vasubu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vasubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vasubu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1i8( @@ -33,7 +33,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2i8( @@ -55,7 +55,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4i8( @@ -77,7 +77,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8i8( @@ -99,7 +99,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16i8( @@ -121,7 +121,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv32i8( @@ -142,10 +142,8 @@ define @intrinsic_vcompress_vm_nxv64i8_nxv64i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv64i8( @@ -167,7 +165,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1i16( @@ -189,7 +187,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2i16( @@ -211,7 +209,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4i16( @@ -233,7 +231,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8i16( @@ -255,7 +253,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16i16( @@ -276,10 +274,8 @@ define @intrinsic_vcompress_vm_nxv32i16_nxv32i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv32i16( @@ -301,7 +297,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1i32( @@ -323,7 +319,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2i32( @@ -345,7 +341,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4i32( @@ -367,7 +363,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8i32( @@ -388,10 +384,8 @@ define @intrinsic_vcompress_vm_nxv16i32_nxv16i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16i32( @@ -413,7 +407,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1f16( @@ -435,7 +429,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2f16( @@ -457,7 +451,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4f16( @@ -479,7 +473,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8f16( @@ -501,7 +495,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16f16( @@ -522,10 +516,8 @@ define @intrinsic_vcompress_vm_nxv32f16_nxv32f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv32f16( @@ -547,7 +539,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1f32( @@ -569,7 +561,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2f32( @@ -591,7 +583,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4f32( @@ -613,7 +605,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8f32( @@ -634,10 +626,8 @@ define @intrinsic_vcompress_vm_nxv16f32_nxv16f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16f32( @@ -659,7 +649,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1f64( @@ -681,7 +671,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2f64( @@ -703,7 +693,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4f64( @@ -724,10 +714,8 @@ define @intrinsic_vcompress_vm_nxv8f64_nxv8f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8f64( @@ -744,8 +732,8 @@ ; CHECK-LABEL: intrinsic_vcompress_um_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu -; CHECK-NEXT: vcompress.vm v25, v16, v0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vcompress.vm v25, v8, v0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1i8( @@ -33,7 +33,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2i8( @@ -55,7 +55,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4i8( @@ -77,7 +77,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8i8( @@ -99,7 +99,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16i8( @@ -121,7 +121,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv32i8( @@ -142,10 +142,8 @@ define @intrinsic_vcompress_vm_nxv64i8_nxv64i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv64i8( @@ -167,7 +165,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1i16( @@ -189,7 +187,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2i16( @@ -211,7 +209,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4i16( @@ -233,7 +231,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8i16( @@ -255,7 +253,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16i16( @@ -276,10 +274,8 @@ define @intrinsic_vcompress_vm_nxv32i16_nxv32i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv32i16( @@ -301,7 +297,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1i32( @@ -323,7 +319,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2i32( @@ -345,7 +341,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4i32( @@ -367,7 +363,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8i32( @@ -388,10 +384,8 @@ define @intrinsic_vcompress_vm_nxv16i32_nxv16i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16i32( @@ -413,7 +407,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1i64( @@ -435,7 +429,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2i64( @@ -457,7 +451,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4i64( @@ -478,10 +472,8 @@ define @intrinsic_vcompress_vm_nxv8i64_nxv8i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8i64( @@ -503,7 +495,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1f16( @@ -525,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2f16( @@ -547,7 +539,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4f16( @@ -569,7 +561,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8f16( @@ -591,7 +583,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16f16( @@ -612,10 +604,8 @@ define @intrinsic_vcompress_vm_nxv32f16_nxv32f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv32f16( @@ -637,7 +627,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1f32( @@ -659,7 +649,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2f32( @@ -681,7 +671,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4f32( @@ -703,7 +693,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8f32( @@ -724,10 +714,8 @@ define @intrinsic_vcompress_vm_nxv16f32_nxv16f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv16f32( @@ -749,7 +737,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vcompress.vm v16, v17, v0 +; CHECK-NEXT: vcompress.vm v8, v9, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1f64( @@ -771,7 +759,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vcompress.vm v16, v18, v0 +; CHECK-NEXT: vcompress.vm v8, v10, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv2f64( @@ -793,7 +781,7 @@ ; CHECK-LABEL: intrinsic_vcompress_vm_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vcompress.vm v16, v20, v0 +; CHECK-NEXT: vcompress.vm v8, v12, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv4f64( @@ -814,10 +802,8 @@ define @intrinsic_vcompress_vm_nxv8f64_nxv8f64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vcompress_vm_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vcompress.vm v16, v8, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vcompress.vm v8, v16, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv8f64( @@ -834,8 +820,8 @@ ; CHECK-LABEL: intrinsic_vcompress_um_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu -; CHECK-NEXT: vcompress.vm v25, v16, v0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vcompress.vm v25, v8, v0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vcompress.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vdiv.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vdiv_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vdiv_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vdiv_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vdiv_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vdiv_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vdiv_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vdiv_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vdiv_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vdiv_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vdiv_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vdiv_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vdiv_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vdiv_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vdiv_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vdiv_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vdiv_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vdiv_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vdiv_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vdiv_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vdiv_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vdiv_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vdiv_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vdiv_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vdiv_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vdiv_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vdiv_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vdiv.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vdiv_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vdiv_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vdiv_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vdiv_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vdiv_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vdiv_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vdiv.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vdiv_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vdiv_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vdiv_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vdiv_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vdiv_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vdiv_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vdiv.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vdiv.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vdiv_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vdiv_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vdiv_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vdiv_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vdiv_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vdiv_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vdiv_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vdiv_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vdiv_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vdiv_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vdiv_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vdiv_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vdiv_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vdiv_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vdiv_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vdiv_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vdiv_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vdiv_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vdiv_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vdiv_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vdiv_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vdiv_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vdiv_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vdiv_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vdiv_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vdiv_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vdiv_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vdiv_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vdiv_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vdiv_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vdiv.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vdiv_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vdiv_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vdiv_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vdiv_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vdiv_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vdiv_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vdiv.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vdiv_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vdiv_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vdiv_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vdiv_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vdiv_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vdiv.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vdiv_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vdiv.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vdiv_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vdiv.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vdiv_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vdiv.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vdiv_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vdiv.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdiv.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vdiv_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vdiv.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdiv_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vdiv.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdiv.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vdiv_iv_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmv.v.i v16, 0 +; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i8 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -64,7 +64,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -74,7 +74,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -87,7 +87,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -109,7 +109,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -134,7 +134,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -144,7 +144,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -169,7 +169,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v18 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -179,7 +179,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -192,7 +192,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -204,7 +204,7 @@ ; CHECK-LABEL: vdiv_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v20 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -214,7 +214,7 @@ ; CHECK-LABEL: vdiv_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -227,7 +227,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -238,9 +238,8 @@ define @vdiv_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vdiv_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vdivu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -250,7 +249,7 @@ ; CHECK-LABEL: vdiv_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -263,7 +262,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -275,7 +274,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -285,7 +284,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -298,7 +297,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -320,7 +319,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -333,7 +332,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -345,7 +344,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -355,7 +354,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -368,7 +367,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -380,7 +379,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v18 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -390,7 +389,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -403,7 +402,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -415,7 +414,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v20 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -425,7 +424,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -438,7 +437,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,9 +448,8 @@ define @vdiv_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vdiv_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vdivu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -461,7 +459,7 @@ ; CHECK-LABEL: vdiv_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -474,7 +472,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -486,7 +484,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -496,7 +494,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -509,7 +507,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -521,7 +519,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -531,7 +529,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -544,7 +542,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -556,7 +554,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v18 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -566,7 +564,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -579,7 +577,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -591,7 +589,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v20 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -601,7 +599,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -614,7 +612,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -625,9 +623,8 @@ define @vdiv_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vdiv_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vdivu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -637,7 +634,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -650,7 +647,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -662,7 +659,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -679,7 +676,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vdivu.vv v16, v16, v25 +; CHECK-NEXT: vdivu.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -704,7 +701,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v18 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -721,7 +718,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vdivu.vv v16, v16, v26 +; CHECK-NEXT: vdivu.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -734,7 +731,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -746,7 +743,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v20 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -759,11 +756,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vdivu.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vdivu.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -776,7 +773,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -787,9 +784,8 @@ define @vdiv_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vdiv_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vdivu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -799,14 +795,14 @@ ; CHECK-LABEL: vdiv_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vdivu.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -819,7 +815,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v18 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vdiv_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v20 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vdiv_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vdiv_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vdiv_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vdivu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vdiv_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v18 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vdiv_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v20 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vdiv_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vdiv_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vdivu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vdiv_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v18 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vdiv_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v20 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vdiv_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vdiv_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vdivu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vdiv_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vdiv_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v17 +; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -648,7 +645,7 @@ ; CHECK-LABEL: vdiv_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -661,7 +658,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -673,7 +670,7 @@ ; CHECK-LABEL: vdiv_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v18 +; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -683,7 +680,7 @@ ; CHECK-LABEL: vdiv_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -696,7 +693,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -708,7 +705,7 @@ ; CHECK-LABEL: vdiv_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vdivu.vv v16, v16, v20 +; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -718,7 +715,7 @@ ; CHECK-LABEL: vdiv_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -731,7 +728,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -742,9 +739,8 @@ define @vdiv_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vdiv_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vdivu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sdiv %va, %vb ret %vc @@ -754,7 +750,7 @@ ; CHECK-LABEL: vdiv_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -767,7 +763,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vdivu.vx v16, v16, a0 +; CHECK-NEXT: vdivu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vdivu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vdivu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vdivu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vdivu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vdivu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vdivu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vdivu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vdivu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vdivu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vdivu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vdivu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vdivu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vdivu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vdivu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vdivu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vdivu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vdivu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vdivu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vdivu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vdivu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vdivu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vdivu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vdivu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vdivu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vdivu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vdivu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vdivu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vdivu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vdivu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vdivu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vdivu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vdivu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vdivu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vdivu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vdivu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vdivu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vdivu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vdivu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vdivu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vdivu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vdivu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vdivu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vdivu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vdivu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vdivu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vdivu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vdivu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vdivu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vdivu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vdivu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vdivu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vdivu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vdivu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vdivu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vdivu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vdivu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vdivu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vdivu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vdivu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vdivu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vdivu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vdivu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vdivu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vdivu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vdivu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vdivu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vdivu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vdivu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vdivu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vdivu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vdivu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vdivu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vdivu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vdivu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vdivu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vdivu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vdivu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vdivu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vdivu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vdivu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vdivu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vdivu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vdivu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vdivu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vdivu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vdivu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vdivu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vdivu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vdivu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vdivu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vdivu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vdivu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vdivu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vdivu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vdivu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vdivu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vdivu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vdivu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vdivu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vdivu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vdivu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vdivu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vdivu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vdivu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vdivu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vdivu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vdivu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vdivu_iv_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmv.v.i v16, 0 +; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: ret %head = insertelement undef, i8 0, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -64,7 +64,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -74,7 +74,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -87,7 +87,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -109,7 +109,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -134,7 +134,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -144,7 +144,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -169,7 +169,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v18 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -179,7 +179,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -192,7 +192,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -204,7 +204,7 @@ ; CHECK-LABEL: vdivu_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v20 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -214,7 +214,7 @@ ; CHECK-LABEL: vdivu_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -227,7 +227,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -238,9 +238,8 @@ define @vdivu_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -250,7 +249,7 @@ ; CHECK-LABEL: vdivu_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -263,7 +262,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -275,7 +274,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -285,7 +284,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -298,7 +297,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -320,7 +319,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -333,7 +332,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -345,7 +344,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -355,7 +354,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -368,7 +367,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -380,7 +379,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v18 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -390,7 +389,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -403,7 +402,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -415,7 +414,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v20 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -425,7 +424,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -438,7 +437,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,9 +448,8 @@ define @vdivu_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -461,7 +459,7 @@ ; CHECK-LABEL: vdivu_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -474,7 +472,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -486,7 +484,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -496,7 +494,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -509,7 +507,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -521,7 +519,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -531,7 +529,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -544,7 +542,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -556,7 +554,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v18 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -566,7 +564,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -579,7 +577,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -591,7 +589,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v20 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -601,7 +599,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -614,7 +612,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -625,9 +623,8 @@ define @vdivu_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -637,7 +634,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -650,7 +647,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -662,7 +659,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -679,7 +676,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vdiv.vv v16, v16, v25 +; CHECK-NEXT: vdiv.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -704,7 +701,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v18 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -721,7 +718,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vdiv.vv v16, v16, v26 +; CHECK-NEXT: vdiv.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -734,7 +731,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -746,7 +743,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v20 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -759,11 +756,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vdiv.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vdiv.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -776,7 +773,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -787,9 +784,8 @@ define @vdivu_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -799,14 +795,14 @@ ; CHECK-LABEL: vdivu_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vdiv.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -819,7 +815,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v18 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vdivu_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v20 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vdivu_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vdivu_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vdivu_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v18 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vdivu_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v20 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vdivu_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vdivu_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v18 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vdivu_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v20 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vdivu_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vdivu_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vdivu_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v17 +; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -648,7 +645,7 @@ ; CHECK-LABEL: vdivu_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -661,7 +658,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -673,7 +670,7 @@ ; CHECK-LABEL: vdivu_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v18 +; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -683,7 +680,7 @@ ; CHECK-LABEL: vdivu_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -696,7 +693,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -708,7 +705,7 @@ ; CHECK-LABEL: vdivu_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vdiv.vv v16, v16, v20 +; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -718,7 +715,7 @@ ; CHECK-LABEL: vdivu_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -731,7 +728,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -742,9 +739,8 @@ define @vdivu_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vdivu_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = udiv %va, %vb ret %vc @@ -754,7 +750,7 @@ ; CHECK-LABEL: vdivu_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -767,7 +763,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vdiv.vx v16, v16, a0 +; CHECK-NEXT: vdiv.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll @@ -5,8 +5,8 @@ ; CHECK-LABEL: vsext_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -16,8 +16,8 @@ ; CHECK-LABEL: vzext_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -27,8 +27,8 @@ ; CHECK-LABEL: vsext_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -38,8 +38,8 @@ ; CHECK-LABEL: vzext_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -49,8 +49,8 @@ ; CHECK-LABEL: vsext_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsext.vf8 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf8 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -60,8 +60,8 @@ ; CHECK-LABEL: vzext_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vzext.vf8 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf8 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -71,8 +71,8 @@ ; CHECK-LABEL: vsext_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -82,8 +82,8 @@ ; CHECK-LABEL: vzext_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -93,8 +93,8 @@ ; CHECK-LABEL: vsext_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -104,8 +104,8 @@ ; CHECK-LABEL: vzext_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -115,8 +115,8 @@ ; CHECK-LABEL: vsext_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsext.vf8 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf8 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -126,8 +126,8 @@ ; CHECK-LABEL: vzext_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vzext.vf8 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf8 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -137,8 +137,8 @@ ; CHECK-LABEL: vsext_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -148,8 +148,8 @@ ; CHECK-LABEL: vzext_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -159,8 +159,8 @@ ; CHECK-LABEL: vsext_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -170,8 +170,8 @@ ; CHECK-LABEL: vzext_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vzext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -181,8 +181,8 @@ ; CHECK-LABEL: vsext_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsext.vf8 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf8 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -192,8 +192,8 @@ ; CHECK-LABEL: vzext_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vzext.vf8 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf8 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -203,8 +203,8 @@ ; CHECK-LABEL: vsext_nxv8i8_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -214,8 +214,8 @@ ; CHECK-LABEL: vzext_nxv8i8_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -225,8 +225,8 @@ ; CHECK-LABEL: vsext_nxv8i8_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -236,8 +236,8 @@ ; CHECK-LABEL: vzext_nxv8i8_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vzext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -247,8 +247,8 @@ ; CHECK-LABEL: vsext_nxv8i8_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsext.vf8 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf8 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -258,8 +258,8 @@ ; CHECK-LABEL: vzext_nxv8i8_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vzext.vf8 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf8 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -269,8 +269,8 @@ ; CHECK-LABEL: vsext_nxv16i8_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -280,8 +280,8 @@ ; CHECK-LABEL: vzext_nxv16i8_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -291,8 +291,8 @@ ; CHECK-LABEL: vsext_nxv16i8_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -302,8 +302,8 @@ ; CHECK-LABEL: vzext_nxv16i8_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vzext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -313,8 +313,8 @@ ; CHECK-LABEL: vsext_nxv32i8_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -324,8 +324,8 @@ ; CHECK-LABEL: vzext_nxv32i8_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -335,8 +335,8 @@ ; CHECK-LABEL: vsext_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -346,8 +346,8 @@ ; CHECK-LABEL: vzext_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -357,8 +357,8 @@ ; CHECK-LABEL: vsext_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -368,8 +368,8 @@ ; CHECK-LABEL: vzext_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -379,8 +379,8 @@ ; CHECK-LABEL: vsext_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -390,8 +390,8 @@ ; CHECK-LABEL: vzext_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -401,8 +401,8 @@ ; CHECK-LABEL: vsext_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -412,8 +412,8 @@ ; CHECK-LABEL: vzext_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vzext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -423,8 +423,8 @@ ; CHECK-LABEL: vsext_nxv4i16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -434,8 +434,8 @@ ; CHECK-LABEL: vzext_nxv4i16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -445,8 +445,8 @@ ; CHECK-LABEL: vsext_nxv4i16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -456,8 +456,8 @@ ; CHECK-LABEL: vzext_nxv4i16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vzext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -467,8 +467,8 @@ ; CHECK-LABEL: vsext_nxv8i16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -478,8 +478,8 @@ ; CHECK-LABEL: vzext_nxv8i16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -489,8 +489,8 @@ ; CHECK-LABEL: vsext_nxv8i16_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -500,8 +500,8 @@ ; CHECK-LABEL: vzext_nxv8i16_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vzext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -511,8 +511,8 @@ ; CHECK-LABEL: vsext_nxv16i16_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -522,8 +522,8 @@ ; CHECK-LABEL: vzext_nxv16i16_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -533,8 +533,8 @@ ; CHECK-LABEL: vsext_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -544,8 +544,8 @@ ; CHECK-LABEL: vzext_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -555,8 +555,8 @@ ; CHECK-LABEL: vsext_nxv2i32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -566,8 +566,8 @@ ; CHECK-LABEL: vzext_nxv2i32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -577,8 +577,8 @@ ; CHECK-LABEL: vsext_nxv4i32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -588,8 +588,8 @@ ; CHECK-LABEL: vzext_nxv4i32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -599,8 +599,8 @@ ; CHECK-LABEL: vsext_nxv8i32_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -610,8 +610,8 @@ ; CHECK-LABEL: vzext_nxv8i32_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll @@ -5,8 +5,8 @@ ; CHECK-LABEL: vsext_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -16,8 +16,8 @@ ; CHECK-LABEL: vzext_nxv1i8_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -27,8 +27,8 @@ ; CHECK-LABEL: vsext_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -38,8 +38,8 @@ ; CHECK-LABEL: vzext_nxv1i8_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -49,8 +49,8 @@ ; CHECK-LABEL: vsext_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsext.vf8 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf8 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -60,8 +60,8 @@ ; CHECK-LABEL: vzext_nxv1i8_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vzext.vf8 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf8 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -71,8 +71,8 @@ ; CHECK-LABEL: vsext_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -82,8 +82,8 @@ ; CHECK-LABEL: vzext_nxv2i8_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -93,8 +93,8 @@ ; CHECK-LABEL: vsext_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -104,8 +104,8 @@ ; CHECK-LABEL: vzext_nxv2i8_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -115,8 +115,8 @@ ; CHECK-LABEL: vsext_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsext.vf8 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf8 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -126,8 +126,8 @@ ; CHECK-LABEL: vzext_nxv2i8_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vzext.vf8 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf8 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -137,8 +137,8 @@ ; CHECK-LABEL: vsext_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -148,8 +148,8 @@ ; CHECK-LABEL: vzext_nxv4i8_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -159,8 +159,8 @@ ; CHECK-LABEL: vsext_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -170,8 +170,8 @@ ; CHECK-LABEL: vzext_nxv4i8_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vzext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -181,8 +181,8 @@ ; CHECK-LABEL: vsext_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsext.vf8 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf8 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -192,8 +192,8 @@ ; CHECK-LABEL: vzext_nxv4i8_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vzext.vf8 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf8 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -203,8 +203,8 @@ ; CHECK-LABEL: vsext_nxv8i8_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -214,8 +214,8 @@ ; CHECK-LABEL: vzext_nxv8i8_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -225,8 +225,8 @@ ; CHECK-LABEL: vsext_nxv8i8_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -236,8 +236,8 @@ ; CHECK-LABEL: vzext_nxv8i8_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vzext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -247,8 +247,8 @@ ; CHECK-LABEL: vsext_nxv8i8_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsext.vf8 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf8 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -258,8 +258,8 @@ ; CHECK-LABEL: vzext_nxv8i8_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vzext.vf8 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf8 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -269,8 +269,8 @@ ; CHECK-LABEL: vsext_nxv16i8_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -280,8 +280,8 @@ ; CHECK-LABEL: vzext_nxv16i8_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -291,8 +291,8 @@ ; CHECK-LABEL: vsext_nxv16i8_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -302,8 +302,8 @@ ; CHECK-LABEL: vzext_nxv16i8_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vzext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -313,8 +313,8 @@ ; CHECK-LABEL: vsext_nxv32i8_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -324,8 +324,8 @@ ; CHECK-LABEL: vzext_nxv32i8_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -335,8 +335,8 @@ ; CHECK-LABEL: vsext_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -346,8 +346,8 @@ ; CHECK-LABEL: vzext_nxv1i16_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -357,8 +357,8 @@ ; CHECK-LABEL: vsext_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -368,8 +368,8 @@ ; CHECK-LABEL: vzext_nxv1i16_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -379,8 +379,8 @@ ; CHECK-LABEL: vsext_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -390,8 +390,8 @@ ; CHECK-LABEL: vzext_nxv2i16_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -401,8 +401,8 @@ ; CHECK-LABEL: vsext_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -412,8 +412,8 @@ ; CHECK-LABEL: vzext_nxv2i16_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vzext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -423,8 +423,8 @@ ; CHECK-LABEL: vsext_nxv4i16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -434,8 +434,8 @@ ; CHECK-LABEL: vzext_nxv4i16_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -445,8 +445,8 @@ ; CHECK-LABEL: vsext_nxv4i16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -456,8 +456,8 @@ ; CHECK-LABEL: vzext_nxv4i16_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vzext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -467,8 +467,8 @@ ; CHECK-LABEL: vsext_nxv8i16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -478,8 +478,8 @@ ; CHECK-LABEL: vzext_nxv8i16_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -489,8 +489,8 @@ ; CHECK-LABEL: vsext_nxv8i16_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -500,8 +500,8 @@ ; CHECK-LABEL: vzext_nxv8i16_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vzext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -511,8 +511,8 @@ ; CHECK-LABEL: vsext_nxv16i16_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -522,8 +522,8 @@ ; CHECK-LABEL: vzext_nxv16i16_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -533,8 +533,8 @@ ; CHECK-LABEL: vsext_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -544,8 +544,8 @@ ; CHECK-LABEL: vzext_nxv1i32_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -555,8 +555,8 @@ ; CHECK-LABEL: vsext_nxv2i32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -566,8 +566,8 @@ ; CHECK-LABEL: vzext_nxv2i32_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -577,8 +577,8 @@ ; CHECK-LABEL: vsext_nxv4i32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -588,8 +588,8 @@ ; CHECK-LABEL: vzext_nxv4i32_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %evec = zext %va to ret %evec @@ -599,8 +599,8 @@ ; CHECK-LABEL: vsext_nxv8i32_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = sext %va to ret %evec @@ -610,8 +610,8 @@ ; CHECK-LABEL: vzext_nxv8i32_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret %evec = zext %va to ret %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv1f16.nxv1f16( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv2f16.nxv2f16( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv2f16.nxv2f16( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv4f16.nxv4f16( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv4f16.nxv4f16( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v18 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv8f16.nxv8f16( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv8f16.nxv8f16( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v20 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv16f16.nxv16f16( @@ -207,10 +207,8 @@ define @intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv16f16.nxv16f16( @@ -231,10 +229,8 @@ define @intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv32f16.nxv32f16( @@ -255,11 +251,10 @@ define @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfadd.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16( @@ -281,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv1f32.nxv1f32( @@ -303,7 +298,7 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv1f32.nxv1f32( @@ -325,7 +320,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv2f32.nxv2f32( @@ -347,7 +342,7 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32( @@ -369,7 +364,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v18 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( @@ -391,7 +386,7 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv4f32.nxv4f32( @@ -413,7 +408,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v20 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv8f32.nxv8f32( @@ -434,10 +429,8 @@ define @intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv8f32.nxv8f32( @@ -458,10 +451,8 @@ define @intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv16f32.nxv16f32( @@ -482,11 +473,10 @@ define @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfadd.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32( @@ -508,7 +498,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv1f64.nxv1f64( @@ -530,7 +520,7 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64( @@ -552,7 +542,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v18 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv2f64.nxv2f64( @@ -574,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv2f64.nxv2f64( @@ -596,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v20 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv4f64.nxv4f64( @@ -617,10 +607,8 @@ define @intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv4f64.nxv4f64( @@ -641,10 +629,8 @@ define @intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv8f64.nxv8f64( @@ -665,11 +651,10 @@ define @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfadd.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64( @@ -692,7 +677,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv1f16.f16( @@ -715,7 +700,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfadd.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv1f16.f16( @@ -738,7 +723,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv2f16.f16( @@ -761,7 +746,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfadd.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv2f16.f16( @@ -784,7 +769,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv4f16.f16( @@ -807,7 +792,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfadd.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv4f16.f16( @@ -830,7 +815,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv8f16.f16( @@ -853,7 +838,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfadd.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv8f16.f16( @@ -876,7 +861,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv16f16.f16( @@ -899,7 +884,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfadd.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv16f16.f16( @@ -922,7 +907,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv32f16.f16( @@ -943,11 +928,9 @@ define @intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfadd.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfadd.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv32f16.f16( @@ -970,7 +953,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv1f32.f32( @@ -993,7 +976,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfadd.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv1f32.f32( @@ -1016,7 +999,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv2f32.f32( @@ -1039,7 +1022,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfadd.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv2f32.f32( @@ -1062,7 +1045,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv4f32.f32( @@ -1085,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfadd.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv4f32.f32( @@ -1108,7 +1091,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv8f32.f32( @@ -1131,7 +1114,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfadd.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv8f32.f32( @@ -1154,7 +1137,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.nxv16f32.f32( @@ -1175,11 +1158,9 @@ define @intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfadd.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfadd.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfadd.mask.nxv16f32.f32( @@ -1205,7 +1186,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1232,7 +1213,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfadd.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1259,7 +1240,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1286,7 +1267,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfadd.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1313,7 +1294,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1340,7 +1321,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfadd.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfadd.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1367,7 +1348,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, ft0 +; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1390,13 +1371,11 @@ ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfadd.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfadd.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s @@ -7,10 +8,12 @@ i64); define @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv1f16.nxv1f16( %0, %1, @@ -27,10 +30,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16( %0, %1, @@ -47,10 +52,12 @@ i64); define @intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv2f16.nxv2f16( %0, %1, @@ -67,10 +74,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv2f16.nxv2f16( %0, %1, @@ -87,10 +96,12 @@ i64); define @intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv4f16.nxv4f16( %0, %1, @@ -107,10 +118,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv4f16.nxv4f16( %0, %1, @@ -127,10 +140,12 @@ i64); define @intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv8f16.nxv8f16( %0, %1, @@ -147,10 +162,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv8f16.nxv8f16( %0, %1, @@ -167,10 +184,12 @@ i64); define @intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv16f16.nxv16f16( %0, %1, @@ -187,10 +206,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv16f16.nxv16f16( %0, %1, @@ -207,10 +228,12 @@ i64); define @intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv32f16.nxv32f16( %0, %1, @@ -227,10 +250,14 @@ i64); define @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16( %0, %1, @@ -247,10 +274,12 @@ i64); define @intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv1f32.nxv1f32( %0, %1, @@ -267,10 +296,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv1f32.nxv1f32( %0, %1, @@ -287,10 +318,12 @@ i64); define @intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv2f32.nxv2f32( %0, %1, @@ -307,10 +340,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32( %0, %1, @@ -327,10 +362,12 @@ i64); define @intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( %0, %1, @@ -347,10 +384,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv4f32.nxv4f32( %0, %1, @@ -367,10 +406,12 @@ i64); define @intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv8f32.nxv8f32( %0, %1, @@ -387,10 +428,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv8f32.nxv8f32( %0, %1, @@ -407,10 +450,12 @@ i64); define @intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv16f32.nxv16f32( %0, %1, @@ -427,10 +472,14 @@ i64); define @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32( %0, %1, @@ -447,10 +496,12 @@ i64); define @intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv1f64.nxv1f64( %0, %1, @@ -467,10 +518,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64( %0, %1, @@ -487,10 +540,12 @@ i64); define @intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv2f64.nxv2f64( %0, %1, @@ -507,10 +562,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv2f64.nxv2f64( %0, %1, @@ -527,10 +584,12 @@ i64); define @intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv4f64.nxv4f64( %0, %1, @@ -547,10 +606,12 @@ i64); define @intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv4f64.nxv4f64( %0, %1, @@ -567,10 +628,12 @@ i64); define @intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfadd.nxv8f64.nxv8f64( %0, %1, @@ -587,10 +650,14 @@ i64); define @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64( %0, %1, @@ -607,10 +674,13 @@ i64); define @intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv1f16.f16( %0, half %1, @@ -627,10 +697,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv1f16.f16( %0, %1, @@ -647,10 +720,13 @@ i64); define @intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv2f16.f16( %0, half %1, @@ -667,10 +743,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv2f16.f16( %0, %1, @@ -687,10 +766,13 @@ i64); define @intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv4f16.f16( %0, half %1, @@ -707,10 +789,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv4f16.f16( %0, %1, @@ -727,10 +812,13 @@ i64); define @intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv8f16.f16( %0, half %1, @@ -747,10 +835,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfadd.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv8f16.f16( %0, %1, @@ -767,10 +858,13 @@ i64); define @intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv16f16.f16( %0, half %1, @@ -787,10 +881,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfadd.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv16f16.f16( %0, %1, @@ -807,10 +904,13 @@ i64); define @intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv32f16.f16( %0, half %1, @@ -827,10 +927,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfadd.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv32f16.f16( %0, %1, @@ -847,10 +950,13 @@ i64); define @intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv1f32.f32( %0, float %1, @@ -867,10 +973,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv1f32.f32( %0, %1, @@ -887,10 +996,13 @@ i64); define @intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv2f32.f32( %0, float %1, @@ -907,10 +1019,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv2f32.f32( %0, %1, @@ -927,10 +1042,13 @@ i64); define @intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv4f32.f32( %0, float %1, @@ -947,10 +1065,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfadd.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv4f32.f32( %0, %1, @@ -967,10 +1088,13 @@ i64); define @intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv8f32.f32( %0, float %1, @@ -987,10 +1111,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfadd.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv8f32.f32( %0, %1, @@ -1007,10 +1134,13 @@ i64); define @intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv16f32.f32( %0, float %1, @@ -1027,10 +1157,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfadd.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv16f32.f32( %0, %1, @@ -1047,10 +1180,13 @@ i64); define @intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv1f64.f64( %0, double %1, @@ -1067,10 +1203,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv1f64.f64( %0, %1, @@ -1087,10 +1226,13 @@ i64); define @intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv2f64.f64( %0, double %1, @@ -1107,10 +1249,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfadd.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv2f64.f64( %0, %1, @@ -1127,10 +1272,13 @@ i64); define @intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv4f64.f64( %0, double %1, @@ -1147,10 +1295,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfadd.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv4f64.f64( %0, %1, @@ -1167,10 +1318,13 @@ i64); define @intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfadd.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfadd.nxv8f64.f64( %0, double %1, @@ -1187,10 +1341,13 @@ i64); define @intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfadd.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfadd.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfadd_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfadd_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfadd_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfadd_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v18 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK-LABEL: vfadd_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v20 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,9 +133,8 @@ define @vfadd_vv_nxv32f16( %va, %vb) { ; CHECK-LABEL: vfadd_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -146,7 +145,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -158,7 +157,7 @@ ; CHECK-LABEL: vfadd_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -168,7 +167,7 @@ ; CHECK-LABEL: vfadd_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +179,7 @@ ; CHECK-LABEL: vfadd_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -190,7 +189,7 @@ ; CHECK-LABEL: vfadd_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -202,7 +201,7 @@ ; CHECK-LABEL: vfadd_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v18 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -212,7 +211,7 @@ ; CHECK-LABEL: vfadd_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +223,7 @@ ; CHECK-LABEL: vfadd_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v20 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -234,7 +233,7 @@ ; CHECK-LABEL: vfadd_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -246,7 +245,7 @@ ; CHECK-LABEL: vfadd_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,9 +256,8 @@ define @vfadd_vv_nxv16f32( %va, %vb) { ; CHECK-LABEL: vfadd_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -269,7 +267,7 @@ ; CHECK-LABEL: vfadd_vf_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +279,7 @@ ; CHECK-LABEL: vfadd_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -291,7 +289,7 @@ ; CHECK-LABEL: vfadd_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -303,7 +301,7 @@ ; CHECK-LABEL: vfadd_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v18 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -313,7 +311,7 @@ ; CHECK-LABEL: vfadd_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -325,7 +323,7 @@ ; CHECK-LABEL: vfadd_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v20 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -335,7 +333,7 @@ ; CHECK-LABEL: vfadd_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,9 +344,8 @@ define @vfadd_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: vfadd_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -358,7 +355,7 @@ ; CHECK-LABEL: vfadd_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -370,7 +367,7 @@ ; CHECK-LABEL: vfadd_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfadd_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfadd_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfadd_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfadd_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v18 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK-LABEL: vfadd_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v20 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,9 +133,8 @@ define @vfadd_vv_nxv32f16( %va, %vb) { ; CHECK-LABEL: vfadd_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -146,7 +145,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -158,7 +157,7 @@ ; CHECK-LABEL: vfadd_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -168,7 +167,7 @@ ; CHECK-LABEL: vfadd_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +179,7 @@ ; CHECK-LABEL: vfadd_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -190,7 +189,7 @@ ; CHECK-LABEL: vfadd_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -202,7 +201,7 @@ ; CHECK-LABEL: vfadd_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v18 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -212,7 +211,7 @@ ; CHECK-LABEL: vfadd_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +223,7 @@ ; CHECK-LABEL: vfadd_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v20 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -234,7 +233,7 @@ ; CHECK-LABEL: vfadd_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -246,7 +245,7 @@ ; CHECK-LABEL: vfadd_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,9 +256,8 @@ define @vfadd_vv_nxv16f32( %va, %vb) { ; CHECK-LABEL: vfadd_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -269,7 +267,7 @@ ; CHECK-LABEL: vfadd_vf_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +279,7 @@ ; CHECK-LABEL: vfadd_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v17 +; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -291,7 +289,7 @@ ; CHECK-LABEL: vfadd_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -303,7 +301,7 @@ ; CHECK-LABEL: vfadd_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v18 +; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -313,7 +311,7 @@ ; CHECK-LABEL: vfadd_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -325,7 +323,7 @@ ; CHECK-LABEL: vfadd_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfadd.vv v16, v16, v20 +; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -335,7 +333,7 @@ ; CHECK-LABEL: vfadd_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,9 +344,8 @@ define @vfadd_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: vfadd_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vfadd.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fadd %va, %vb ret %vc @@ -358,7 +355,7 @@ ; CHECK-LABEL: vfadd_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -370,7 +367,7 @@ ; CHECK-LABEL: vfadd_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfadd.vf v16, v16, fa0 +; CHECK-NEXT: vfadd.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfclass-rv32.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -31,7 +31,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -55,7 +55,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -77,7 +77,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -101,7 +101,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -123,7 +123,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -147,7 +147,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfclass.v v16, v18, v0.t +; CHECK-NEXT: vfclass.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -193,7 +193,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -215,7 +215,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vfclass.v v16, v20, v0.t +; CHECK-NEXT: vfclass.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -239,7 +239,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -260,10 +260,8 @@ define @intrinsic_vfclass_mask_v_nxv32i16_nxv32f16( ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vfclass.v v16, v8, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfclass.v v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -287,7 +285,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -309,7 +307,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -333,7 +331,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -355,7 +353,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -379,7 +377,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -401,7 +399,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfclass.v v16, v18, v0.t +; CHECK-NEXT: vfclass.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -425,7 +423,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -447,7 +445,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vfclass.v v16, v20, v0.t +; CHECK-NEXT: vfclass.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -471,7 +469,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i32 %1) nounwind { @@ -492,10 +490,8 @@ define @intrinsic_vfclass_mask_v_nxv16i32_nxv16f32( ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vfclass.v v16, v8, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfclass.v v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfclass-rv64.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -31,7 +31,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -55,7 +55,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -77,7 +77,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -101,7 +101,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -123,7 +123,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -147,7 +147,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfclass.v v16, v18, v0.t +; CHECK-NEXT: vfclass.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -193,7 +193,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -215,7 +215,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vfclass.v v16, v20, v0.t +; CHECK-NEXT: vfclass.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -239,7 +239,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -260,10 +260,8 @@ define @intrinsic_vfclass_mask_v_nxv32i16_nxv32f16( ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vfclass.v v16, v8, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfclass.v v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -287,7 +285,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -309,7 +307,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -333,7 +331,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -355,7 +353,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -379,7 +377,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -401,7 +399,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfclass.v v16, v18, v0.t +; CHECK-NEXT: vfclass.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -425,7 +423,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -447,7 +445,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vfclass.v v16, v20, v0.t +; CHECK-NEXT: vfclass.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -471,7 +469,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -492,10 +490,8 @@ define @intrinsic_vfclass_mask_v_nxv16i32_nxv16f32( ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vfclass.v v16, v8, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfclass.v v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -519,7 +515,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -541,7 +537,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfclass.v v16, v17, v0.t +; CHECK-NEXT: vfclass.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -565,7 +561,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -587,7 +583,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfclass.v v16, v18, v0.t +; CHECK-NEXT: vfclass.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -611,7 +607,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -633,7 +629,7 @@ ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vfclass.v v16, v20, v0.t +; CHECK-NEXT: vfclass.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -657,7 +653,7 @@ ; CHECK-LABEL: intrinsic_vfclass_v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vfclass.v v16, v16 +; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -678,10 +674,8 @@ define @intrinsic_vfclass_mask_v_nxv8i64_nxv8f64( ; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vfclass.v v16, v8, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vfclass.v v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( @@ -5,10 +6,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( %0, i32 %1) @@ -23,10 +26,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16( %0, %1, @@ -41,10 +46,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16( %0, i32 %1) @@ -59,10 +66,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16( %0, %1, @@ -77,10 +86,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16( %0, i32 %1) @@ -95,10 +106,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16( %0, %1, @@ -113,10 +126,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16( %0, i32 %1) @@ -131,10 +146,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16( %0, %1, @@ -149,10 +166,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16( %0, i32 %1) @@ -167,10 +186,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16( %0, %1, @@ -185,10 +206,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16( %0, i32 %1) @@ -203,10 +226,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16( %0, %1, @@ -221,10 +246,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32( %0, i32 %1) @@ -239,10 +266,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32( %0, %1, @@ -257,10 +286,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32( %0, i32 %1) @@ -275,10 +306,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32( %0, %1, @@ -293,10 +326,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32( %0, i32 %1) @@ -311,10 +346,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32( %0, %1, @@ -329,10 +366,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32( %0, i32 %1) @@ -347,10 +386,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32( %0, %1, @@ -365,10 +406,12 @@ i32); define @intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32( %0, i32 %1) @@ -383,10 +426,12 @@ i32); define @intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( @@ -5,10 +6,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( %0, i64 %1) @@ -23,10 +26,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16( %0, %1, @@ -41,10 +46,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16( %0, i64 %1) @@ -59,10 +66,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16( %0, %1, @@ -77,10 +86,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16( %0, i64 %1) @@ -95,10 +106,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16( %0, %1, @@ -113,10 +126,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16( %0, i64 %1) @@ -131,10 +146,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16( %0, %1, @@ -149,10 +166,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16( %0, i64 %1) @@ -167,10 +186,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16( %0, %1, @@ -185,10 +206,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16( %0, i64 %1) @@ -203,10 +226,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16( %0, %1, @@ -221,10 +246,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32( %0, i64 %1) @@ -239,10 +266,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32( %0, %1, @@ -257,10 +286,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32( %0, i64 %1) @@ -275,10 +306,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32( %0, %1, @@ -293,10 +326,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32( %0, i64 %1) @@ -311,10 +346,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32( %0, %1, @@ -329,10 +366,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32( %0, i64 %1) @@ -347,10 +386,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32( %0, %1, @@ -365,10 +406,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32( %0, i64 %1) @@ -383,10 +426,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32( %0, %1, @@ -401,10 +446,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64( %0, i64 %1) @@ -419,10 +466,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv1f64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64( %0, %1, @@ -437,10 +486,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64( %0, i64 %1) @@ -455,10 +506,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv2f64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64( %0, %1, @@ -473,10 +526,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64( %0, i64 %1) @@ -491,10 +546,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv4f64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64( %0, %1, @@ -509,10 +566,12 @@ i64); define @intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64( %0, i64 %1) @@ -527,10 +586,12 @@ i64); define @intrinsic_vfcvt_mask_f.x.v_nxv8f64_nxv8i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( @@ -5,10 +6,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( %0, i32 %1) @@ -23,10 +26,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16( %0, %1, @@ -41,10 +46,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16( %0, i32 %1) @@ -59,10 +66,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16( %0, %1, @@ -77,10 +86,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16( %0, i32 %1) @@ -95,10 +106,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16( %0, %1, @@ -113,10 +126,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16( %0, i32 %1) @@ -131,10 +146,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16( %0, %1, @@ -149,10 +166,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16( %0, i32 %1) @@ -167,10 +186,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16( %0, %1, @@ -185,10 +206,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16( %0, i32 %1) @@ -203,10 +226,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16( %0, %1, @@ -221,10 +246,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32( %0, i32 %1) @@ -239,10 +266,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32( %0, %1, @@ -257,10 +286,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32( %0, i32 %1) @@ -275,10 +306,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32( %0, %1, @@ -293,10 +326,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32( %0, i32 %1) @@ -311,10 +346,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32( %0, %1, @@ -329,10 +366,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32( %0, i32 %1) @@ -347,10 +386,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32( %0, %1, @@ -365,10 +406,12 @@ i32); define @intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32( %0, i32 %1) @@ -383,10 +426,12 @@ i32); define @intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( @@ -5,10 +6,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( %0, i64 %1) @@ -23,10 +26,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16( %0, %1, @@ -41,10 +46,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16( %0, i64 %1) @@ -59,10 +66,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16( %0, %1, @@ -77,10 +86,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16( %0, i64 %1) @@ -95,10 +106,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16( %0, %1, @@ -113,10 +126,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16( %0, i64 %1) @@ -131,10 +146,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16( %0, %1, @@ -149,10 +166,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16( %0, i64 %1) @@ -167,10 +186,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16( %0, %1, @@ -185,10 +206,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16( %0, i64 %1) @@ -203,10 +226,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16( %0, %1, @@ -221,10 +246,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32( %0, i64 %1) @@ -239,10 +266,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32( %0, %1, @@ -257,10 +286,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32( %0, i64 %1) @@ -275,10 +306,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32( %0, %1, @@ -293,10 +326,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32( %0, i64 %1) @@ -311,10 +346,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32( %0, %1, @@ -329,10 +366,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32( %0, i64 %1) @@ -347,10 +386,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32( %0, %1, @@ -365,10 +406,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32( %0, i64 %1) @@ -383,10 +426,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32( %0, %1, @@ -401,10 +446,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64( %0, i64 %1) @@ -419,10 +466,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv1f64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64( %0, %1, @@ -437,10 +486,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64( %0, i64 %1) @@ -455,10 +506,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv2f64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64( %0, %1, @@ -473,10 +526,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64( %0, i64 %1) @@ -491,10 +546,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv4f64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64( %0, %1, @@ -509,10 +566,12 @@ i64); define @intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64( %0, i64 %1) @@ -527,10 +586,12 @@ i64); define @intrinsic_vfcvt_mask_f.xu.v_nxv8f64_nxv8i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16( @@ -5,10 +6,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16( %0, i32 %1) @@ -23,10 +26,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i16_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i16.nxv1f16( %0, %1, @@ -41,10 +46,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16( %0, i32 %1) @@ -59,10 +66,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i16_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i16.nxv2f16( %0, %1, @@ -77,10 +86,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16( %0, i32 %1) @@ -95,10 +106,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i16.nxv4f16( %0, %1, @@ -113,10 +126,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16( %0, i32 %1) @@ -131,10 +146,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i16.nxv8f16( %0, %1, @@ -149,10 +166,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16( %0, i32 %1) @@ -167,10 +186,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i16.nxv16f16( %0, %1, @@ -185,10 +206,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16( %0, i32 %1) @@ -203,10 +226,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv32i16_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv32i16.nxv32f16( %0, %1, @@ -221,10 +246,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32( %0, i32 %1) @@ -239,10 +266,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i32_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i32.nxv1f32( %0, %1, @@ -257,10 +286,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32( %0, i32 %1) @@ -275,10 +306,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i32.nxv2f32( %0, %1, @@ -293,10 +326,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32( %0, i32 %1) @@ -311,10 +346,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i32.nxv4f32( %0, %1, @@ -329,10 +366,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32( %0, i32 %1) @@ -347,10 +386,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i32.nxv8f32( %0, %1, @@ -365,10 +406,12 @@ i32); define @intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32( %0, i32 %1) @@ -383,10 +426,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i32_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i32.nxv16f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16( @@ -5,10 +6,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16( %0, i64 %1) @@ -23,10 +26,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i16_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i16.nxv1f16( %0, %1, @@ -41,10 +46,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i16.nxv2f16( %0, i64 %1) @@ -59,10 +66,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i16_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i16.nxv2f16( %0, %1, @@ -77,10 +86,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i16.nxv4f16( %0, i64 %1) @@ -95,10 +106,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i16.nxv4f16( %0, %1, @@ -113,10 +126,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i16.nxv8f16( %0, i64 %1) @@ -131,10 +146,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i16.nxv8f16( %0, %1, @@ -149,10 +166,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i16.nxv16f16( %0, i64 %1) @@ -167,10 +186,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i16.nxv16f16( %0, %1, @@ -185,10 +206,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv32i16.nxv32f16( %0, i64 %1) @@ -203,10 +226,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv32i16_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv32i16.nxv32f16( %0, %1, @@ -221,10 +246,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i32.nxv1f32( %0, i64 %1) @@ -239,10 +266,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i32_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i32.nxv1f32( %0, %1, @@ -257,10 +286,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i32.nxv2f32( %0, i64 %1) @@ -275,10 +306,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i32.nxv2f32( %0, %1, @@ -293,10 +326,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i32.nxv4f32( %0, i64 %1) @@ -311,10 +346,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i32.nxv4f32( %0, %1, @@ -329,10 +366,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i32.nxv8f32( %0, i64 %1) @@ -347,10 +386,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i32.nxv8f32( %0, %1, @@ -365,10 +406,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv16i32.nxv16f32( %0, i64 %1) @@ -383,10 +426,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i32_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv16i32.nxv16f32( %0, %1, @@ -401,10 +446,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv1i64_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv1i64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i64.nxv1f64( %0, i64 %1) @@ -419,10 +466,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv1i64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv1i64.nxv1f64( %0, %1, @@ -437,10 +486,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv2i64_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv2i64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv2i64.nxv2f64( %0, i64 %1) @@ -455,10 +506,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv2i64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv2i64.nxv2f64( %0, %1, @@ -473,10 +526,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv4i64_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv4i64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv4i64.nxv4f64( %0, i64 %1) @@ -491,10 +546,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv4i64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv4i64.nxv4f64( %0, %1, @@ -509,10 +566,12 @@ i64); define @intrinsic_vfcvt_rtz.x.f.v_nxv8i64_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.x.f.v_nxv8i64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.x.f.v.nxv8i64.nxv8f64( %0, i64 %1) @@ -527,10 +586,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i64_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.x.f.v_nxv8i64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.x.f.v.mask.nxv8i64.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16( @@ -5,10 +6,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16( %0, i32 %1) @@ -23,10 +26,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i16_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i16.nxv1f16( %0, %1, @@ -41,10 +46,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16( %0, i32 %1) @@ -59,10 +66,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i16_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i16.nxv2f16( %0, %1, @@ -77,10 +86,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16( %0, i32 %1) @@ -95,10 +106,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i16.nxv4f16( %0, %1, @@ -113,10 +126,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16( %0, i32 %1) @@ -131,10 +146,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i16.nxv8f16( %0, %1, @@ -149,10 +166,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16( %0, i32 %1) @@ -167,10 +186,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i16.nxv16f16( %0, %1, @@ -185,10 +206,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16( %0, i32 %1) @@ -203,10 +226,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv32i16_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv32i16.nxv32f16( %0, %1, @@ -221,10 +246,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32( %0, i32 %1) @@ -239,10 +266,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f32( %0, %1, @@ -257,10 +286,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32( %0, i32 %1) @@ -275,10 +306,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f32( %0, %1, @@ -293,10 +326,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32( %0, i32 %1) @@ -311,10 +346,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f32( %0, %1, @@ -329,10 +366,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32( %0, i32 %1) @@ -347,10 +386,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f32( %0, %1, @@ -365,10 +406,12 @@ i32); define @intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32( %0, i32 %1) @@ -383,10 +426,12 @@ i32); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16( @@ -5,10 +6,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16( %0, i64 %1) @@ -23,10 +26,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i16_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i16.nxv1f16( %0, %1, @@ -41,10 +46,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i16.nxv2f16( %0, i64 %1) @@ -59,10 +66,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i16_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i16.nxv2f16( %0, %1, @@ -77,10 +86,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i16.nxv4f16( %0, i64 %1) @@ -95,10 +106,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i16.nxv4f16( %0, %1, @@ -113,10 +126,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i16.nxv8f16( %0, i64 %1) @@ -131,10 +146,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i16.nxv8f16( %0, %1, @@ -149,10 +166,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i16.nxv16f16( %0, i64 %1) @@ -167,10 +186,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i16.nxv16f16( %0, %1, @@ -185,10 +206,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv32i16.nxv32f16( %0, i64 %1) @@ -203,10 +226,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv32i16_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv32i16.nxv32f16( %0, %1, @@ -221,10 +246,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i32.nxv1f32( %0, i64 %1) @@ -239,10 +266,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f32( %0, %1, @@ -257,10 +286,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i32.nxv2f32( %0, i64 %1) @@ -275,10 +306,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f32( %0, %1, @@ -293,10 +326,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i32.nxv4f32( %0, i64 %1) @@ -311,10 +346,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f32( %0, %1, @@ -329,10 +366,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i32.nxv8f32( %0, i64 %1) @@ -347,10 +386,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f32( %0, %1, @@ -365,10 +406,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv16i32.nxv16f32( %0, i64 %1) @@ -383,10 +426,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f32( %0, %1, @@ -401,10 +446,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv1i64_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv1i64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i64.nxv1f64( %0, i64 %1) @@ -419,10 +466,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv1i64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f64( %0, %1, @@ -437,10 +486,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv2i64_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv2i64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv2i64.nxv2f64( %0, i64 %1) @@ -455,10 +506,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv2i64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f64( %0, %1, @@ -473,10 +526,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv4i64_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv4i64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv4i64.nxv4f64( %0, i64 %1) @@ -491,10 +546,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv4i64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f64( %0, %1, @@ -509,10 +566,12 @@ i64); define @intrinsic_vfcvt_rtz.xu.f.v_nxv8i64_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_rtz.xu.f.v_nxv8i64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.nxv8i64.nxv8f64( %0, i64 %1) @@ -527,10 +586,12 @@ i64); define @intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i64_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_rtz.xu.f.v_nxv8i64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( @@ -5,10 +6,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( %0, i32 %1) @@ -23,10 +26,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16( %0, %1, @@ -41,10 +46,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16( %0, i32 %1) @@ -59,10 +66,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16( %0, %1, @@ -77,10 +86,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16( %0, i32 %1) @@ -95,10 +106,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16( %0, %1, @@ -113,10 +126,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16( %0, i32 %1) @@ -131,10 +146,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16( %0, %1, @@ -149,10 +166,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16( %0, i32 %1) @@ -167,10 +186,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16( %0, %1, @@ -185,10 +206,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16( %0, i32 %1) @@ -203,10 +226,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16( %0, %1, @@ -221,10 +246,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32( %0, i32 %1) @@ -239,10 +266,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32( %0, %1, @@ -257,10 +286,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32( %0, i32 %1) @@ -275,10 +306,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32( %0, %1, @@ -293,10 +326,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32( %0, i32 %1) @@ -311,10 +346,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32( %0, %1, @@ -329,10 +366,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32( %0, i32 %1) @@ -347,10 +386,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32( %0, %1, @@ -365,10 +406,12 @@ i32); define @intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32( %0, i32 %1) @@ -383,10 +426,12 @@ i32); define @intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( @@ -5,10 +6,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( %0, i64 %1) @@ -23,10 +26,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16( %0, %1, @@ -41,10 +46,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16( %0, i64 %1) @@ -59,10 +66,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16( %0, %1, @@ -77,10 +86,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16( %0, i64 %1) @@ -95,10 +106,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16( %0, %1, @@ -113,10 +126,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16( %0, i64 %1) @@ -131,10 +146,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16( %0, %1, @@ -149,10 +166,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16( %0, i64 %1) @@ -167,10 +186,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16( %0, %1, @@ -185,10 +206,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16( %0, i64 %1) @@ -203,10 +226,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16( %0, %1, @@ -221,10 +246,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32( %0, i64 %1) @@ -239,10 +266,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32( %0, %1, @@ -257,10 +286,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32( %0, i64 %1) @@ -275,10 +306,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32( %0, %1, @@ -293,10 +326,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32( %0, i64 %1) @@ -311,10 +346,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32( %0, %1, @@ -329,10 +366,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32( %0, i64 %1) @@ -347,10 +386,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32( %0, %1, @@ -365,10 +406,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32( %0, i64 %1) @@ -383,10 +426,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32( %0, %1, @@ -401,10 +446,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64( %0, i64 %1) @@ -419,10 +466,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv1i64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64( %0, %1, @@ -437,10 +486,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64( %0, i64 %1) @@ -455,10 +506,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv2i64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64( %0, %1, @@ -473,10 +526,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64( %0, i64 %1) @@ -491,10 +546,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv4i64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64( %0, %1, @@ -509,10 +566,12 @@ i64); define @intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64( %0, i64 %1) @@ -527,10 +586,12 @@ i64); define @intrinsic_vfcvt_mask_x.f.v_nxv8i64_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( @@ -5,10 +6,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( %0, i32 %1) @@ -23,10 +26,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16( %0, %1, @@ -41,10 +46,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16( %0, i32 %1) @@ -59,10 +66,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16( %0, %1, @@ -77,10 +86,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16( %0, i32 %1) @@ -95,10 +106,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16( %0, %1, @@ -113,10 +126,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16( %0, i32 %1) @@ -131,10 +146,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16( %0, %1, @@ -149,10 +166,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16( %0, i32 %1) @@ -167,10 +186,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16( %0, %1, @@ -185,10 +206,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16( %0, i32 %1) @@ -203,10 +226,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16( %0, %1, @@ -221,10 +246,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32( %0, i32 %1) @@ -239,10 +266,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32( %0, %1, @@ -257,10 +286,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32( %0, i32 %1) @@ -275,10 +306,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32( %0, %1, @@ -293,10 +326,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32( %0, i32 %1) @@ -311,10 +346,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32( %0, %1, @@ -329,10 +366,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32( %0, i32 %1) @@ -347,10 +386,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32( %0, %1, @@ -365,10 +406,12 @@ i32); define @intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32( %0, i32 %1) @@ -383,10 +426,12 @@ i32); define @intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( @@ -5,10 +6,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( %0, i64 %1) @@ -23,10 +26,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16( %0, %1, @@ -41,10 +46,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16( %0, i64 %1) @@ -59,10 +66,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16( %0, %1, @@ -77,10 +86,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16( %0, i64 %1) @@ -95,10 +106,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16( %0, %1, @@ -113,10 +126,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16( %0, i64 %1) @@ -131,10 +146,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16( %0, %1, @@ -149,10 +166,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16( %0, i64 %1) @@ -167,10 +186,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16( %0, %1, @@ -185,10 +206,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16( %0, i64 %1) @@ -203,10 +226,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16( %0, %1, @@ -221,10 +246,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32( %0, i64 %1) @@ -239,10 +266,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32( %0, %1, @@ -257,10 +286,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32( %0, i64 %1) @@ -275,10 +306,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32( %0, %1, @@ -293,10 +326,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32( %0, i64 %1) @@ -311,10 +346,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32( %0, %1, @@ -329,10 +366,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32( %0, i64 %1) @@ -347,10 +386,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32( %0, %1, @@ -365,10 +406,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32( %0, i64 %1) @@ -383,10 +426,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32( %0, %1, @@ -401,10 +446,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64( %0, i64 %1) @@ -419,10 +466,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv1i64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64( %0, %1, @@ -437,10 +486,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64( %0, i64 %1) @@ -455,10 +506,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv2i64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64( %0, %1, @@ -473,10 +526,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64( %0, i64 %1) @@ -491,10 +546,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv4i64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64( %0, %1, @@ -509,10 +566,12 @@ i64); define @intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64( %0, i64 %1) @@ -527,10 +586,12 @@ i64); define @intrinsic_vfcvt_mask_xu.f.v_nxv8i64_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f16.nxv1f16( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f16.nxv2f16( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f16.nxv4f16( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v18 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f16.nxv8f16( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v20 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16( @@ -207,10 +207,8 @@ define @intrinsic_vfdiv_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f16.nxv16f16( @@ -231,10 +229,8 @@ define @intrinsic_vfdiv_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv32f16.nxv32f16( @@ -255,11 +251,10 @@ define @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv32f16.nxv32f16( @@ -281,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv1f32.nxv1f32( @@ -303,7 +298,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f32.nxv1f32( @@ -325,7 +320,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv2f32.nxv2f32( @@ -347,7 +342,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f32.nxv2f32( @@ -369,7 +364,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v18 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv4f32.nxv4f32( @@ -391,7 +386,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f32.nxv4f32( @@ -413,7 +408,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v20 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv8f32.nxv8f32( @@ -434,10 +429,8 @@ define @intrinsic_vfdiv_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f32.nxv8f32( @@ -458,10 +451,8 @@ define @intrinsic_vfdiv_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv16f32.nxv16f32( @@ -482,11 +473,10 @@ define @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f32.nxv16f32( @@ -508,7 +498,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv1f64.nxv1f64( @@ -530,7 +520,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f64.nxv1f64( @@ -552,7 +542,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v18 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv2f64.nxv2f64( @@ -574,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f64.nxv2f64( @@ -596,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v20 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv4f64.nxv4f64( @@ -617,10 +607,8 @@ define @intrinsic_vfdiv_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f64.nxv4f64( @@ -641,10 +629,8 @@ define @intrinsic_vfdiv_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv8f64.nxv8f64( @@ -665,11 +651,10 @@ define @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfdiv.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f64.nxv8f64( @@ -692,7 +677,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv1f16.f16( @@ -715,7 +700,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f16.f16( @@ -738,7 +723,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv2f16.f16( @@ -761,7 +746,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f16.f16( @@ -784,7 +769,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv4f16.f16( @@ -807,7 +792,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f16.f16( @@ -830,7 +815,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv8f16.f16( @@ -853,7 +838,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f16.f16( @@ -876,7 +861,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv16f16.f16( @@ -899,7 +884,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f16.f16( @@ -922,7 +907,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv32f16.f16( @@ -943,11 +928,9 @@ define @intrinsic_vfdiv_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv32f16.f16( @@ -970,7 +953,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv1f32.f32( @@ -993,7 +976,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f32.f32( @@ -1016,7 +999,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv2f32.f32( @@ -1039,7 +1022,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f32.f32( @@ -1062,7 +1045,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv4f32.f32( @@ -1085,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f32.f32( @@ -1108,7 +1091,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv8f32.f32( @@ -1131,7 +1114,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f32.f32( @@ -1154,7 +1137,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.nxv16f32.f32( @@ -1175,11 +1158,9 @@ define @intrinsic_vfdiv_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f32.f32( @@ -1205,7 +1186,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1232,7 +1213,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1259,7 +1240,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1286,7 +1267,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1313,7 +1294,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1340,7 +1321,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfdiv.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1367,7 +1348,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1390,13 +1371,11 @@ ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfdiv.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfdiv.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vfdiv_vv_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv1f16( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv1f16( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vfdiv_vv_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv2f16( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv2f16( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vfdiv_vv_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv4f16( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv4f16( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vfdiv_vv_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv8f16( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv8f16( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vfdiv_vv_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv16f16( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv16f16( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vfdiv_vv_nxv32f16_nxv32f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv32f16( %0, %1, @@ -226,10 +249,14 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv32f16( %0, %1, @@ -246,10 +273,12 @@ i64); define @intrinsic_vfdiv_vv_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv1f32( %0, %1, @@ -266,10 +295,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv1f32( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vfdiv_vv_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv2f32( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv2f32( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vfdiv_vv_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv4f32( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv4f32( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vfdiv_vv_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv8f32( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv8f32( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vfdiv_vv_nxv16f32_nxv16f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv16f32( %0, %1, @@ -426,10 +471,14 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv16f32( %0, %1, @@ -446,10 +495,12 @@ i64); define @intrinsic_vfdiv_vv_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv1f64( %0, %1, @@ -466,10 +517,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv1f64( %0, %1, @@ -486,10 +539,12 @@ i64); define @intrinsic_vfdiv_vv_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv2f64( %0, %1, @@ -506,10 +561,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv2f64( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vfdiv_vv_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv4f64( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv4f64( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vfdiv_vv_nxv8f64_nxv8f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv8f64( %0, %1, @@ -586,10 +649,14 @@ i64); define @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfdiv.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv8f64( %0, %1, @@ -606,10 +673,13 @@ i64); define @intrinsic_vfdiv_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv1f16.f16( %0, half %1, @@ -626,10 +696,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv1f16.f16( %0, %1, @@ -646,10 +719,13 @@ i64); define @intrinsic_vfdiv_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv2f16.f16( %0, half %1, @@ -666,10 +742,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv2f16.f16( %0, %1, @@ -686,10 +765,13 @@ i64); define @intrinsic_vfdiv_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv4f16.f16( %0, half %1, @@ -706,10 +788,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv4f16.f16( %0, %1, @@ -726,10 +811,13 @@ i64); define @intrinsic_vfdiv_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv8f16.f16( %0, half %1, @@ -746,10 +834,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv8f16.f16( %0, %1, @@ -766,10 +857,13 @@ i64); define @intrinsic_vfdiv_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv16f16.f16( %0, half %1, @@ -786,10 +880,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv16f16.f16( %0, %1, @@ -806,10 +903,13 @@ i64); define @intrinsic_vfdiv_vf_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv32f16.f16( %0, half %1, @@ -826,10 +926,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv32f16.f16( %0, %1, @@ -846,10 +949,13 @@ i64); define @intrinsic_vfdiv_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv1f32.f32( %0, float %1, @@ -866,10 +972,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv1f32.f32( %0, %1, @@ -886,10 +995,13 @@ i64); define @intrinsic_vfdiv_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv2f32.f32( %0, float %1, @@ -906,10 +1018,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv2f32.f32( %0, %1, @@ -926,10 +1041,13 @@ i64); define @intrinsic_vfdiv_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv4f32.f32( %0, float %1, @@ -946,10 +1064,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv4f32.f32( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vfdiv_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv8f32.f32( %0, float %1, @@ -986,10 +1110,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv8f32.f32( %0, %1, @@ -1006,10 +1133,13 @@ i64); define @intrinsic_vfdiv_vf_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv16f32.f32( %0, float %1, @@ -1026,10 +1156,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv16f32.f32( %0, %1, @@ -1046,10 +1179,13 @@ i64); define @intrinsic_vfdiv_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv1f64.f64( %0, double %1, @@ -1066,10 +1202,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv1f64.f64( %0, %1, @@ -1086,10 +1225,13 @@ i64); define @intrinsic_vfdiv_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv2f64.f64( %0, double %1, @@ -1106,10 +1248,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv2f64.f64( %0, %1, @@ -1126,10 +1271,13 @@ i64); define @intrinsic_vfdiv_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv4f64.f64( %0, double %1, @@ -1146,10 +1294,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv4f64.f64( %0, %1, @@ -1166,10 +1317,13 @@ i64); define @intrinsic_vfdiv_vf_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfdiv.nxv8f64.f64( %0, double %1, @@ -1186,10 +1340,13 @@ i64); define @intrinsic_vfdiv_mask_vf_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfdiv.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfdiv.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v18 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v20 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,9 +133,8 @@ define @vfdiv_vv_nxv32f16( %va, %vb) { ; CHECK-LABEL: vfdiv_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vfdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -146,7 +145,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -158,7 +157,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -168,7 +167,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +179,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -190,7 +189,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -202,7 +201,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v18 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -212,7 +211,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +223,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v20 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -234,7 +233,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -246,7 +245,7 @@ ; CHECK-LABEL: vfdiv_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,9 +256,8 @@ define @vfdiv_vv_nxv16f32( %va, %vb) { ; CHECK-LABEL: vfdiv_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vfdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -269,7 +267,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +279,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -291,7 +289,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -303,7 +301,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v18 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -313,7 +311,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -325,7 +323,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v20 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -335,7 +333,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,9 +344,8 @@ define @vfdiv_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: vfdiv_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vfdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -358,7 +355,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -370,7 +367,7 @@ ; CHECK-LABEL: vfdiv_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v18 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v20 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,9 +133,8 @@ define @vfdiv_vv_nxv32f16( %va, %vb) { ; CHECK-LABEL: vfdiv_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vfdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -146,7 +145,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -158,7 +157,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -168,7 +167,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +179,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -190,7 +189,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -202,7 +201,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v18 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -212,7 +211,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +223,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v20 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -234,7 +233,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -246,7 +245,7 @@ ; CHECK-LABEL: vfdiv_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,9 +256,8 @@ define @vfdiv_vv_nxv16f32( %va, %vb) { ; CHECK-LABEL: vfdiv_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vfdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -269,7 +267,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +279,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v17 +; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -291,7 +289,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -303,7 +301,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v18 +; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -313,7 +311,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -325,7 +323,7 @@ ; CHECK-LABEL: vfdiv_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfdiv.vv v16, v16, v20 +; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -335,7 +333,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,9 +344,8 @@ define @vfdiv_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: vfdiv_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vfdiv.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fdiv %va, %vb ret %vc @@ -358,7 +355,7 @@ ; CHECK-LABEL: vfdiv_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -370,7 +367,7 @@ ; CHECK-LABEL: vfdiv_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, fa0 +; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare i32 @llvm.riscv.vfirst.i32.nxv1i1( @@ -5,10 +6,12 @@ i32); define i32 @intrinsic_vfirst_m_i32_nxv1i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vfirst.i32.nxv1i1( %0, i32 %1) @@ -22,10 +25,14 @@ i32); define i32 @intrinsic_vfirst_mask_m_i32_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv1i1( %0, %1, @@ -39,10 +46,12 @@ i32); define i32 @intrinsic_vfirst_m_i32_nxv2i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vfirst.i32.nxv2i1( %0, i32 %1) @@ -56,10 +65,14 @@ i32); define i32 @intrinsic_vfirst_mask_m_i32_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv2i1( %0, %1, @@ -73,10 +86,12 @@ i32); define i32 @intrinsic_vfirst_m_i32_nxv4i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vfirst.i32.nxv4i1( %0, i32 %1) @@ -90,10 +105,14 @@ i32); define i32 @intrinsic_vfirst_mask_m_i32_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv4i1( %0, %1, @@ -107,10 +126,12 @@ i32); define i32 @intrinsic_vfirst_m_i32_nxv8i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vfirst.i32.nxv8i1( %0, i32 %1) @@ -124,10 +145,14 @@ i32); define i32 @intrinsic_vfirst_mask_m_i32_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv8i1( %0, %1, @@ -141,10 +166,12 @@ i32); define i32 @intrinsic_vfirst_m_i32_nxv16i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vfirst.i32.nxv16i1( %0, i32 %1) @@ -158,10 +185,14 @@ i32); define i32 @intrinsic_vfirst_mask_m_i32_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv16i1( %0, %1, @@ -175,10 +206,12 @@ i32); define i32 @intrinsic_vfirst_m_i32_nxv32i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vfirst.i32.nxv32i1( %0, i32 %1) @@ -192,10 +225,14 @@ i32); define i32 @intrinsic_vfirst_mask_m_i32_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv32i1( %0, %1, @@ -209,10 +246,12 @@ i32); define i32 @intrinsic_vfirst_m_i32_nxv64i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i32_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vfirst.i32.nxv64i1( %0, i32 %1) @@ -226,10 +265,14 @@ i32); define i32 @intrinsic_vfirst_mask_m_i32_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i32_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vfirst.mask.i32.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare i64 @llvm.riscv.vfirst.i64.nxv1i1( @@ -5,10 +6,12 @@ i64); define i64 @intrinsic_vfirst_m_i64_nxv1i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vfirst.i64.nxv1i1( %0, i64 %1) @@ -22,10 +25,14 @@ i64); define i64 @intrinsic_vfirst_mask_m_i64_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv1i1( %0, %1, @@ -39,10 +46,12 @@ i64); define i64 @intrinsic_vfirst_m_i64_nxv2i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vfirst.i64.nxv2i1( %0, i64 %1) @@ -56,10 +65,14 @@ i64); define i64 @intrinsic_vfirst_mask_m_i64_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv2i1( %0, %1, @@ -73,10 +86,12 @@ i64); define i64 @intrinsic_vfirst_m_i64_nxv4i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vfirst.i64.nxv4i1( %0, i64 %1) @@ -90,10 +105,14 @@ i64); define i64 @intrinsic_vfirst_mask_m_i64_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv4i1( %0, %1, @@ -107,10 +126,12 @@ i64); define i64 @intrinsic_vfirst_m_i64_nxv8i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vfirst.i64.nxv8i1( %0, i64 %1) @@ -124,10 +145,14 @@ i64); define i64 @intrinsic_vfirst_mask_m_i64_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv8i1( %0, %1, @@ -141,10 +166,12 @@ i64); define i64 @intrinsic_vfirst_m_i64_nxv16i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vfirst.i64.nxv16i1( %0, i64 %1) @@ -158,10 +185,14 @@ i64); define i64 @intrinsic_vfirst_mask_m_i64_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv16i1( %0, %1, @@ -175,10 +206,12 @@ i64); define i64 @intrinsic_vfirst_m_i64_nxv32i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vfirst.i64.nxv32i1( %0, i64 %1) @@ -192,10 +225,14 @@ i64); define i64 @intrinsic_vfirst_mask_m_i64_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv32i1( %0, %1, @@ -209,10 +246,12 @@ i64); define i64 @intrinsic_vfirst_m_i64_nxv64i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vfirst.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vfirst.i64.nxv64i1( %0, i64 %1) @@ -226,10 +265,14 @@ i64); define i64 @intrinsic_vfirst_mask_m_i64_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vfirst.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu -; CHECK: vfirst.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20 +; CHECK-NEXT: vfmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20 +; CHECK-NEXT: vfmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20 +; CHECK-NEXT: vfmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f32.f32( @@ -1011,7 +999,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1039,7 +1027,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1067,7 +1055,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfmacc.vf v8, ft0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1095,7 +1083,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1123,7 +1111,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfmacc.vf v8, ft0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1151,7 +1139,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20 +; CHECK-NEXT: vfmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20 +; CHECK-NEXT: vfmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18 +; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20 +; CHECK-NEXT: vfmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f32.f32( @@ -1008,7 +996,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv1f64.f64( @@ -1032,7 +1020,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f64.f64( @@ -1056,7 +1044,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv2f64.f64( @@ -1080,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f64.f64( @@ -1104,7 +1092,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.nxv4f64.f64( @@ -1128,7 +1116,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20 +; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20 +; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20 +; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f32.f32( @@ -1011,7 +999,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1039,7 +1027,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1067,7 +1055,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfmadd.vf v8, ft0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1095,7 +1083,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1123,7 +1111,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfmadd.vf v8, ft0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1151,7 +1139,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20 +; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20 +; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18 +; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20 +; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f32.f32( @@ -1008,7 +996,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv1f64.f64( @@ -1032,7 +1020,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f64.f64( @@ -1056,7 +1044,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv2f64.f64( @@ -1080,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f64.f64( @@ -1104,7 +1092,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.nxv4f64.f64( @@ -1128,7 +1116,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v17 +; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv1f16.nxv1f16( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmax.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v17 +; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv2f16.nxv2f16( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmax.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v17 +; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv4f16.nxv4f16( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmax.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v18 +; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv8f16.nxv8f16( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmax.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmax.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v20 +; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv16f16.nxv16f16( @@ -207,10 +207,8 @@ define @intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmax.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmax.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16( @@ -231,10 +229,8 @@ define @intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv32f16.nxv32f16( @@ -255,11 +251,10 @@ define @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfmax.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16( @@ -281,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v17 +; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv1f32.nxv1f32( @@ -303,7 +298,7 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmax.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32( @@ -325,7 +320,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v17 +; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv2f32.nxv2f32( @@ -347,7 +342,7 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmax.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32( @@ -369,7 +364,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v18 +; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv4f32.nxv4f32( @@ -391,7 +386,7 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmax.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmax.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32( @@ -413,7 +408,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v20 +; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv8f32.nxv8f32( @@ -434,10 +429,8 @@ define @intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmax.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmax.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32( @@ -458,10 +451,8 @@ define @intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv16f32.nxv16f32( @@ -482,11 +473,10 @@ define @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfmax.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32( @@ -508,7 +498,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v17 +; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv1f64.nxv1f64( @@ -530,7 +520,7 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmax.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv1f64.nxv1f64( @@ -552,7 +542,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v18 +; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv2f64.nxv2f64( @@ -574,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmax.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmax.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv2f64.nxv2f64( @@ -596,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v20 +; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv4f64.nxv4f64( @@ -617,10 +607,8 @@ define @intrinsic_vfmax_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmax.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmax.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv4f64.nxv4f64( @@ -641,10 +629,8 @@ define @intrinsic_vfmax_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv8f64.nxv8f64( @@ -665,11 +651,10 @@ define @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfmax.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64( @@ -692,7 +677,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv1f16.f16( @@ -715,7 +700,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmax.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv1f16.f16( @@ -738,7 +723,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv2f16.f16( @@ -761,7 +746,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmax.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv2f16.f16( @@ -784,7 +769,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv4f16.f16( @@ -807,7 +792,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmax.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv4f16.f16( @@ -830,7 +815,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv8f16.f16( @@ -853,7 +838,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmax.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv8f16.f16( @@ -876,7 +861,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv16f16.f16( @@ -899,7 +884,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmax.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv16f16.f16( @@ -922,7 +907,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv32f16.f16( @@ -943,11 +928,9 @@ define @intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfmax.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmax.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv32f16.f16( @@ -970,7 +953,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv1f32.f32( @@ -993,7 +976,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmax.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv1f32.f32( @@ -1016,7 +999,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv2f32.f32( @@ -1039,7 +1022,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmax.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv2f32.f32( @@ -1062,7 +1045,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv4f32.f32( @@ -1085,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmax.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv4f32.f32( @@ -1108,7 +1091,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv8f32.f32( @@ -1131,7 +1114,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmax.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv8f32.f32( @@ -1154,7 +1137,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.nxv16f32.f32( @@ -1175,11 +1158,9 @@ define @intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfmax.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmax.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmax.mask.nxv16f32.f32( @@ -1205,7 +1186,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1232,7 +1213,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmax.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1259,7 +1240,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1286,7 +1267,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmax.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1313,7 +1294,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1340,7 +1321,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmax.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfmax.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1367,7 +1348,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfmax.vf v16, v16, ft0 +; CHECK-NEXT: vfmax.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1390,13 +1371,11 @@ ; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfmax.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfmax.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfmax.nxv1f16.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv1f16.nxv1f16( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv2f16.nxv2f16( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv4f16.nxv4f16( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv8f16.nxv8f16( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv16f16.nxv16f16( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv32f16.nxv32f16( %0, %1, @@ -226,10 +249,14 @@ i64); define @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16( %0, %1, @@ -246,10 +273,12 @@ i64); define @intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv1f32.nxv1f32( %0, %1, @@ -266,10 +295,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv2f32.nxv2f32( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv4f32.nxv4f32( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv8f32.nxv8f32( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv16f32.nxv16f32( %0, %1, @@ -426,10 +471,14 @@ i64); define @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32( %0, %1, @@ -446,10 +495,12 @@ i64); define @intrinsic_vfmax_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv1f64.nxv1f64( %0, %1, @@ -466,10 +517,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv1f64.nxv1f64( %0, %1, @@ -486,10 +539,12 @@ i64); define @intrinsic_vfmax_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv2f64.nxv2f64( %0, %1, @@ -506,10 +561,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv2f64.nxv2f64( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vfmax_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv4f64.nxv4f64( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vfmax_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv4f64.nxv4f64( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vfmax_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmax.nxv8f64.nxv8f64( %0, %1, @@ -586,10 +649,14 @@ i64); define @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64( %0, %1, @@ -606,10 +673,13 @@ i64); define @intrinsic_vfmax_vf_nxv1f16_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv1f16.f16( %0, half %1, @@ -626,10 +696,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv1f16.f16( %0, %1, @@ -646,10 +719,13 @@ i64); define @intrinsic_vfmax_vf_nxv2f16_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv2f16.f16( %0, half %1, @@ -666,10 +742,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv2f16.f16( %0, %1, @@ -686,10 +765,13 @@ i64); define @intrinsic_vfmax_vf_nxv4f16_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv4f16.f16( %0, half %1, @@ -706,10 +788,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv4f16.f16( %0, %1, @@ -726,10 +811,13 @@ i64); define @intrinsic_vfmax_vf_nxv8f16_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv8f16.f16( %0, half %1, @@ -746,10 +834,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfmax.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv8f16.f16( %0, %1, @@ -766,10 +857,13 @@ i64); define @intrinsic_vfmax_vf_nxv16f16_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv16f16.f16( %0, half %1, @@ -786,10 +880,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfmax.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv16f16.f16( %0, %1, @@ -806,10 +903,13 @@ i64); define @intrinsic_vfmax_vf_nxv32f16_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv32f16.f16( %0, half %1, @@ -826,10 +926,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmax.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv32f16.f16( %0, %1, @@ -846,10 +949,13 @@ i64); define @intrinsic_vfmax_vf_nxv1f32_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv1f32.f32( %0, float %1, @@ -866,10 +972,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv1f32.f32( %0, %1, @@ -886,10 +995,13 @@ i64); define @intrinsic_vfmax_vf_nxv2f32_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv2f32.f32( %0, float %1, @@ -906,10 +1018,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv2f32.f32( %0, %1, @@ -926,10 +1041,13 @@ i64); define @intrinsic_vfmax_vf_nxv4f32_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv4f32.f32( %0, float %1, @@ -946,10 +1064,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfmax.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv4f32.f32( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vfmax_vf_nxv8f32_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv8f32.f32( %0, float %1, @@ -986,10 +1110,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfmax.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv8f32.f32( %0, %1, @@ -1006,10 +1133,13 @@ i64); define @intrinsic_vfmax_vf_nxv16f32_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv16f32.f32( %0, float %1, @@ -1026,10 +1156,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmax.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv16f32.f32( %0, %1, @@ -1046,10 +1179,13 @@ i64); define @intrinsic_vfmax_vf_nxv1f64_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv1f64.f64( %0, double %1, @@ -1066,10 +1202,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfmax.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv1f64.f64( %0, %1, @@ -1086,10 +1225,13 @@ i64); define @intrinsic_vfmax_vf_nxv2f64_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv2f64.f64( %0, double %1, @@ -1106,10 +1248,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfmax.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv2f64.f64( %0, %1, @@ -1126,10 +1271,13 @@ i64); define @intrinsic_vfmax_vf_nxv4f64_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv4f64.f64( %0, double %1, @@ -1146,10 +1294,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfmax.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv4f64.f64( %0, %1, @@ -1166,10 +1317,13 @@ i64); define @intrinsic_vfmax_vf_nxv8f64_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfmax.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmax.nxv8f64.f64( %0, double %1, @@ -1186,10 +1340,13 @@ i64); define @intrinsic_vfmax_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfmax.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmax.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfmerge.nxv1f16.nxv1f16( @@ -7,10 +8,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f16.nxv1f16( %0, %1, @@ -27,10 +30,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f16.f16( %0, half %1, @@ -47,10 +53,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f16.nxv2f16( %0, %1, @@ -67,10 +75,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f16.f16( %0, half %1, @@ -87,10 +98,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f16.nxv4f16( %0, %1, @@ -107,10 +120,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f16.f16( %0, half %1, @@ -127,10 +143,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f16.nxv8f16( %0, %1, @@ -147,10 +165,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f16.f16( %0, half %1, @@ -167,10 +188,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv16f16.nxv16f16( %0, %1, @@ -187,10 +210,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv16f16.f16( %0, half %1, @@ -207,10 +233,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv32f16.nxv32f16( %0, %1, @@ -227,10 +255,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv32f16.f16( %0, half %1, @@ -247,10 +278,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f32.nxv1f32( %0, %1, @@ -267,10 +300,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32( %0, float %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f32.f32( %0, float %1, @@ -287,10 +323,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f32.nxv2f32( %0, %1, @@ -307,10 +345,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32( %0, float %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f32.f32( %0, float %1, @@ -327,10 +368,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f32.nxv4f32( %0, %1, @@ -347,10 +390,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32( %0, float %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f32.f32( %0, float %1, @@ -367,10 +413,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f32.nxv8f32( %0, %1, @@ -387,10 +435,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32( %0, float %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f32.f32( %0, float %1, @@ -407,10 +458,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv16f32.nxv16f32( %0, %1, @@ -427,10 +480,13 @@ i32); define @intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32( %0, float %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv16f32.f32( %0, float %1, @@ -447,10 +503,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f64.nxv1f64( %0, %1, @@ -467,10 +525,17 @@ i32); define @intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64( %0, double %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: fld ft0, 8(sp) +; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f64.f64( %0, double %1, @@ -487,10 +552,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f64.nxv2f64( %0, %1, @@ -507,10 +574,17 @@ i32); define @intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64( %0, double %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: fld ft0, 8(sp) +; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f64.f64( %0, double %1, @@ -527,10 +601,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f64.nxv4f64( %0, %1, @@ -547,10 +623,17 @@ i32); define @intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64( %0, double %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: fld ft0, 8(sp) +; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f64.f64( %0, double %1, @@ -567,10 +650,12 @@ i32); define @intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f64.nxv8f64( %0, %1, @@ -587,10 +672,17 @@ i32); define @intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64( %0, double %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) +; CHECK-NEXT: fld ft0, 8(sp) +; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f64.f64( %0, double %1, @@ -601,10 +693,12 @@ } define @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv1f16.f16( %0, half zeroinitializer, @@ -615,10 +709,12 @@ } define @intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv2f16.f16( %0, half zeroinitializer, @@ -629,10 +725,12 @@ } define @intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv4f16.f16( %0, half zeroinitializer, @@ -643,10 +741,12 @@ } define @intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv8f16.f16( %0, half zeroinitializer, @@ -657,10 +757,12 @@ } define @intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv16f16.f16( %0, half zeroinitializer, @@ -671,10 +773,12 @@ } define @intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv32f16.f16( %0, half zeroinitializer, @@ -685,10 +789,12 @@ } define @intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv1f32.f32( %0, float zeroinitializer, @@ -699,10 +805,12 @@ } define @intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv2f32.f32( %0, float zeroinitializer, @@ -713,10 +821,12 @@ } define @intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv4f32.f32( %0, float zeroinitializer, @@ -727,10 +837,12 @@ } define @intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv8f32.f32( %0, float zeroinitializer, @@ -741,10 +853,12 @@ } define @intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv16f32.f32( %0, float zeroinitializer, @@ -755,10 +869,12 @@ } define @intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv1f64.f64( %0, double zeroinitializer, @@ -769,10 +885,12 @@ } define @intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv2f64.f64( %0, double zeroinitializer, @@ -783,10 +901,12 @@ } define @intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv4f64.f64( %0, double zeroinitializer, @@ -797,10 +917,12 @@ } define @intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv8f64.f64( %0, double zeroinitializer, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfmerge.nxv1f16.nxv1f16( @@ -7,10 +8,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f16.nxv1f16( %0, %1, @@ -27,10 +30,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16( %0, half %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f16.f16( %0, half %1, @@ -47,10 +53,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f16.nxv2f16( %0, %1, @@ -67,10 +75,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16( %0, half %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f16.f16( %0, half %1, @@ -87,10 +98,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f16.nxv4f16( %0, %1, @@ -107,10 +120,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16( %0, half %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f16.f16( %0, half %1, @@ -127,10 +143,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f16.nxv8f16( %0, %1, @@ -147,10 +165,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16( %0, half %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f16.f16( %0, half %1, @@ -167,10 +188,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv16f16.nxv16f16( %0, %1, @@ -187,10 +210,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16( %0, half %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv16f16.f16( %0, half %1, @@ -207,10 +233,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv32f16.nxv32f16( %0, %1, @@ -227,10 +255,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16( %0, half %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv32f16.f16( %0, half %1, @@ -247,10 +278,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f32.nxv1f32( %0, %1, @@ -267,10 +300,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32( %0, float %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f32.f32( %0, float %1, @@ -287,10 +323,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f32.nxv2f32( %0, %1, @@ -307,10 +345,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32( %0, float %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f32.f32( %0, float %1, @@ -327,10 +368,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f32.nxv4f32( %0, %1, @@ -347,10 +390,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32( %0, float %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f32.f32( %0, float %1, @@ -367,10 +413,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f32.nxv8f32( %0, %1, @@ -387,10 +435,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32( %0, float %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f32.f32( %0, float %1, @@ -407,10 +458,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv16f32.nxv16f32( %0, %1, @@ -427,10 +480,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32( %0, float %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv16f32.f32( %0, float %1, @@ -447,10 +503,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f64.nxv1f64( %0, %1, @@ -467,10 +525,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64( %0, double %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv1f64.f64( %0, double %1, @@ -487,10 +548,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f64.nxv2f64( %0, %1, @@ -507,10 +570,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64( %0, double %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv2f64.f64( %0, double %1, @@ -527,10 +593,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f64.nxv4f64( %0, %1, @@ -547,10 +615,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64( %0, double %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv4f64.f64( %0, double %1, @@ -567,10 +638,12 @@ i64); define @intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f64.nxv8f64( %0, %1, @@ -587,10 +660,13 @@ i64); define @intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64( %0, double %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfmerge.vfm v8, v8, ft0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8 -; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0 %a = call @llvm.riscv.vfmerge.nxv8f64.f64( %0, double %1, @@ -601,10 +677,12 @@ } define @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv1f16.f16( %0, half zeroinitializer, @@ -615,10 +693,12 @@ } define @intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv2f16.f16( %0, half zeroinitializer, @@ -629,10 +709,12 @@ } define @intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv4f16.f16( %0, half zeroinitializer, @@ -643,10 +725,12 @@ } define @intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv8f16.f16( %0, half zeroinitializer, @@ -657,10 +741,12 @@ } define @intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv16f16.f16( %0, half zeroinitializer, @@ -671,10 +757,12 @@ } define @intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv32f16.f16( %0, half zeroinitializer, @@ -685,10 +773,12 @@ } define @intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv1f32.f32( %0, float zeroinitializer, @@ -699,10 +789,12 @@ } define @intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv2f32.f32( %0, float zeroinitializer, @@ -713,10 +805,12 @@ } define @intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv4f32.f32( %0, float zeroinitializer, @@ -727,10 +821,12 @@ } define @intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv8f32.f32( %0, float zeroinitializer, @@ -741,10 +837,12 @@ } define @intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv16f32.f32( %0, float zeroinitializer, @@ -755,10 +853,12 @@ } define @intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv1f64.f64( %0, double zeroinitializer, @@ -769,10 +869,12 @@ } define @intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv2f64.f64( %0, double zeroinitializer, @@ -783,10 +885,12 @@ } define @intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv4f64.f64( %0, double zeroinitializer, @@ -797,10 +901,12 @@ } define @intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0 %a = call @llvm.riscv.vfmerge.nxv8f64.f64( %0, double zeroinitializer, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v17 +; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv1f16.nxv1f16( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmin.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv1f16.nxv1f16( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v17 +; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv2f16.nxv2f16( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmin.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv2f16.nxv2f16( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v17 +; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv4f16.nxv4f16( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmin.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv4f16.nxv4f16( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v18 +; CHECK-NEXT: vfmin.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv8f16.nxv8f16( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmin.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmin.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv8f16.nxv8f16( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v20 +; CHECK-NEXT: vfmin.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv16f16.nxv16f16( @@ -207,10 +207,8 @@ define @intrinsic_vfmin_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmin.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmin.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv16f16.nxv16f16( @@ -231,10 +229,8 @@ define @intrinsic_vfmin_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmin_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv32f16.nxv32f16( @@ -255,11 +251,10 @@ define @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfmin.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16( @@ -281,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v17 +; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv1f32.nxv1f32( @@ -303,7 +298,7 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmin.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv1f32.nxv1f32( @@ -325,7 +320,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v17 +; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv2f32.nxv2f32( @@ -347,7 +342,7 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmin.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv2f32.nxv2f32( @@ -369,7 +364,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v18 +; CHECK-NEXT: vfmin.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv4f32.nxv4f32( @@ -391,7 +386,7 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmin.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmin.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv4f32.nxv4f32( @@ -413,7 +408,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v20 +; CHECK-NEXT: vfmin.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv8f32.nxv8f32( @@ -434,10 +429,8 @@ define @intrinsic_vfmin_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmin.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmin.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv8f32.nxv8f32( @@ -458,10 +451,8 @@ define @intrinsic_vfmin_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv16f32.nxv16f32( @@ -482,11 +473,10 @@ define @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfmin.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32( @@ -508,7 +498,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v17 +; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv1f64.nxv1f64( @@ -530,7 +520,7 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmin.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv1f64.nxv1f64( @@ -552,7 +542,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v18 +; CHECK-NEXT: vfmin.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv2f64.nxv2f64( @@ -574,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmin.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmin.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv2f64.nxv2f64( @@ -596,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v20 +; CHECK-NEXT: vfmin.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv4f64.nxv4f64( @@ -617,10 +607,8 @@ define @intrinsic_vfmin_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmin.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmin.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv4f64.nxv4f64( @@ -641,10 +629,8 @@ define @intrinsic_vfmin_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv8f64.nxv8f64( @@ -665,11 +651,10 @@ define @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfmin.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64( @@ -692,7 +677,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv1f16.f16( @@ -715,7 +700,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmin.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv1f16.f16( @@ -738,7 +723,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv2f16.f16( @@ -761,7 +746,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmin.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv2f16.f16( @@ -784,7 +769,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv4f16.f16( @@ -807,7 +792,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmin.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv4f16.f16( @@ -830,7 +815,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv8f16.f16( @@ -853,7 +838,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmin.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv8f16.f16( @@ -876,7 +861,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv16f16.f16( @@ -899,7 +884,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmin.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv16f16.f16( @@ -922,7 +907,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv32f16.f16( @@ -943,11 +928,9 @@ define @intrinsic_vfmin_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfmin.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmin.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv32f16.f16( @@ -970,7 +953,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv1f32.f32( @@ -993,7 +976,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmin.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv1f32.f32( @@ -1016,7 +999,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv2f32.f32( @@ -1039,7 +1022,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmin.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv2f32.f32( @@ -1062,7 +1045,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv4f32.f32( @@ -1085,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmin.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv4f32.f32( @@ -1108,7 +1091,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv8f32.f32( @@ -1131,7 +1114,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmin.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv8f32.f32( @@ -1154,7 +1137,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.nxv16f32.f32( @@ -1175,11 +1158,9 @@ define @intrinsic_vfmin_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfmin.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmin.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmin.mask.nxv16f32.f32( @@ -1205,7 +1186,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1232,7 +1213,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmin.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1259,7 +1240,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1286,7 +1267,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmin.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1313,7 +1294,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1340,7 +1321,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmin.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfmin.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1367,7 +1348,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfmin.vf v16, v16, ft0 +; CHECK-NEXT: vfmin.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1390,13 +1371,11 @@ ; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfmin.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfmin.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfmin.nxv1f16.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv1f16.nxv1f16( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv1f16.nxv1f16( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vfmin_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv2f16.nxv2f16( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv2f16.nxv2f16( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vfmin_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv4f16.nxv4f16( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv4f16.nxv4f16( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vfmin_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv8f16.nxv8f16( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv8f16.nxv8f16( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vfmin_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv16f16.nxv16f16( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv16f16.nxv16f16( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vfmin_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv32f16.nxv32f16( %0, %1, @@ -226,10 +249,14 @@ i64); define @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16( %0, %1, @@ -246,10 +273,12 @@ i64); define @intrinsic_vfmin_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv1f32.nxv1f32( %0, %1, @@ -266,10 +295,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv1f32.nxv1f32( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vfmin_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv2f32.nxv2f32( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv2f32.nxv2f32( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vfmin_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv4f32.nxv4f32( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv4f32.nxv4f32( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vfmin_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv8f32.nxv8f32( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv8f32.nxv8f32( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vfmin_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv16f32.nxv16f32( %0, %1, @@ -426,10 +471,14 @@ i64); define @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32( %0, %1, @@ -446,10 +495,12 @@ i64); define @intrinsic_vfmin_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv1f64.nxv1f64( %0, %1, @@ -466,10 +517,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv1f64.nxv1f64( %0, %1, @@ -486,10 +539,12 @@ i64); define @intrinsic_vfmin_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv2f64.nxv2f64( %0, %1, @@ -506,10 +561,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv2f64.nxv2f64( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vfmin_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv4f64.nxv4f64( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vfmin_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv4f64.nxv4f64( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vfmin_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmin.nxv8f64.nxv8f64( %0, %1, @@ -586,10 +649,14 @@ i64); define @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64( %0, %1, @@ -606,10 +673,13 @@ i64); define @intrinsic_vfmin_vf_nxv1f16_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv1f16.f16( %0, half %1, @@ -626,10 +696,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv1f16.f16( %0, %1, @@ -646,10 +719,13 @@ i64); define @intrinsic_vfmin_vf_nxv2f16_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv2f16.f16( %0, half %1, @@ -666,10 +742,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv2f16.f16( %0, %1, @@ -686,10 +765,13 @@ i64); define @intrinsic_vfmin_vf_nxv4f16_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv4f16.f16( %0, half %1, @@ -706,10 +788,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv4f16.f16( %0, %1, @@ -726,10 +811,13 @@ i64); define @intrinsic_vfmin_vf_nxv8f16_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv8f16.f16( %0, half %1, @@ -746,10 +834,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfmin.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv8f16.f16( %0, %1, @@ -766,10 +857,13 @@ i64); define @intrinsic_vfmin_vf_nxv16f16_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv16f16.f16( %0, half %1, @@ -786,10 +880,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfmin.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv16f16.f16( %0, %1, @@ -806,10 +903,13 @@ i64); define @intrinsic_vfmin_vf_nxv32f16_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv32f16.f16( %0, half %1, @@ -826,10 +926,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmin.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv32f16.f16( %0, %1, @@ -846,10 +949,13 @@ i64); define @intrinsic_vfmin_vf_nxv1f32_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv1f32.f32( %0, float %1, @@ -866,10 +972,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv1f32.f32( %0, %1, @@ -886,10 +995,13 @@ i64); define @intrinsic_vfmin_vf_nxv2f32_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv2f32.f32( %0, float %1, @@ -906,10 +1018,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv2f32.f32( %0, %1, @@ -926,10 +1041,13 @@ i64); define @intrinsic_vfmin_vf_nxv4f32_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv4f32.f32( %0, float %1, @@ -946,10 +1064,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfmin.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv4f32.f32( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vfmin_vf_nxv8f32_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv8f32.f32( %0, float %1, @@ -986,10 +1110,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfmin.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv8f32.f32( %0, %1, @@ -1006,10 +1133,13 @@ i64); define @intrinsic_vfmin_vf_nxv16f32_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv16f32.f32( %0, float %1, @@ -1026,10 +1156,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmin.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv16f32.f32( %0, %1, @@ -1046,10 +1179,13 @@ i64); define @intrinsic_vfmin_vf_nxv1f64_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv1f64.f64( %0, double %1, @@ -1066,10 +1202,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfmin.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv1f64.f64( %0, %1, @@ -1086,10 +1225,13 @@ i64); define @intrinsic_vfmin_vf_nxv2f64_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv2f64.f64( %0, double %1, @@ -1106,10 +1248,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfmin.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv2f64.f64( %0, %1, @@ -1126,10 +1271,13 @@ i64); define @intrinsic_vfmin_vf_nxv4f64_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv4f64.f64( %0, double %1, @@ -1146,10 +1294,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfmin.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv4f64.f64( %0, %1, @@ -1166,10 +1317,13 @@ i64); define @intrinsic_vfmin_vf_nxv8f64_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfmin.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}} %a = call @llvm.riscv.vfmin.nxv8f64.f64( %0, double %1, @@ -1186,10 +1340,13 @@ i64); define @intrinsic_vfmin_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfmin.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t %a = call @llvm.riscv.vfmin.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20 +; CHECK-NEXT: vfmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20 +; CHECK-NEXT: vfmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20 +; CHECK-NEXT: vfmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f32.f32( @@ -1011,7 +999,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1039,7 +1027,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1067,7 +1055,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfmsac.vf v8, ft0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1095,7 +1083,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1123,7 +1111,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfmsac.vf v8, ft0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1151,7 +1139,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20 +; CHECK-NEXT: vfmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20 +; CHECK-NEXT: vfmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18 +; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20 +; CHECK-NEXT: vfmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f32.f32( @@ -1008,7 +996,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv1f64.f64( @@ -1032,7 +1020,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f64.f64( @@ -1056,7 +1044,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv2f64.f64( @@ -1080,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f64.f64( @@ -1104,7 +1092,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.nxv4f64.f64( @@ -1128,7 +1116,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20 +; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20 +; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20 +; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f32.f32( @@ -1011,7 +999,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1039,7 +1027,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1067,7 +1055,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfmsub.vf v8, ft0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1095,7 +1083,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1123,7 +1111,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfmsub.vf v8, ft0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1151,7 +1139,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20 +; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20 +; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18 +; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20 +; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f32.f32( @@ -1008,7 +996,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv1f64.f64( @@ -1032,7 +1020,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f64.f64( @@ -1056,7 +1044,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv2f64.f64( @@ -1080,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f64.f64( @@ -1104,7 +1092,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.nxv4f64.f64( @@ -1128,7 +1116,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv1f16.nxv1f16( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfmul.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv1f16.nxv1f16( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv2f16.nxv2f16( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfmul.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv2f16.nxv2f16( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv4f16.nxv4f16( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfmul.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv4f16.nxv4f16( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v18 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv8f16.nxv8f16( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfmul.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv8f16.nxv8f16( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v20 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv16f16.nxv16f16( @@ -207,10 +207,8 @@ define @intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmul.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv16f16.nxv16f16( @@ -231,10 +229,8 @@ define @intrinsic_vfmul_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv32f16.nxv32f16( @@ -255,11 +251,10 @@ define @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfmul.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv32f16.nxv32f16( @@ -281,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv1f32.nxv1f32( @@ -303,7 +298,7 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfmul.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv1f32.nxv1f32( @@ -325,7 +320,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv2f32.nxv2f32( @@ -347,7 +342,7 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfmul.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv2f32.nxv2f32( @@ -369,7 +364,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v18 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv4f32.nxv4f32( @@ -391,7 +386,7 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfmul.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv4f32.nxv4f32( @@ -413,7 +408,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v20 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv8f32.nxv8f32( @@ -434,10 +429,8 @@ define @intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmul.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv8f32.nxv8f32( @@ -458,10 +451,8 @@ define @intrinsic_vfmul_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv16f32.nxv16f32( @@ -482,11 +473,10 @@ define @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfmul.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv16f32.nxv16f32( @@ -508,7 +498,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv1f64.nxv1f64( @@ -530,7 +520,7 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfmul.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv1f64.nxv1f64( @@ -552,7 +542,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v18 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv2f64.nxv2f64( @@ -574,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfmul.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv2f64.nxv2f64( @@ -596,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v20 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv4f64.nxv4f64( @@ -617,10 +607,8 @@ define @intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfmul.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv4f64.nxv4f64( @@ -641,10 +629,8 @@ define @intrinsic_vfmul_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv8f64.nxv8f64( @@ -665,11 +651,10 @@ define @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfmul.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv8f64.nxv8f64( @@ -692,7 +677,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv1f16.f16( @@ -715,7 +700,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfmul.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv1f16.f16( @@ -738,7 +723,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv2f16.f16( @@ -761,7 +746,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfmul.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv2f16.f16( @@ -784,7 +769,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv4f16.f16( @@ -807,7 +792,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfmul.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv4f16.f16( @@ -830,7 +815,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv8f16.f16( @@ -853,7 +838,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfmul.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv8f16.f16( @@ -876,7 +861,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv16f16.f16( @@ -899,7 +884,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfmul.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv16f16.f16( @@ -922,7 +907,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv32f16.f16( @@ -943,11 +928,9 @@ define @intrinsic_vfmul_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfmul.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmul.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv32f16.f16( @@ -970,7 +953,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv1f32.f32( @@ -993,7 +976,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfmul.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv1f32.f32( @@ -1016,7 +999,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv2f32.f32( @@ -1039,7 +1022,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfmul.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv2f32.f32( @@ -1062,7 +1045,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv4f32.f32( @@ -1085,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfmul.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv4f32.f32( @@ -1108,7 +1091,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv8f32.f32( @@ -1131,7 +1114,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfmul.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv8f32.f32( @@ -1154,7 +1137,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.nxv16f32.f32( @@ -1175,11 +1158,9 @@ define @intrinsic_vfmul_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfmul.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmul.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfmul.mask.nxv16f32.f32( @@ -1205,7 +1186,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1232,7 +1213,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfmul.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1259,7 +1240,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1286,7 +1267,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfmul.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1313,7 +1294,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1340,7 +1321,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfmul.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfmul.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1367,7 +1348,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, ft0 +; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1390,13 +1371,11 @@ ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfmul.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfmul.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfmul.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vfmul_vv_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv1f16( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv1f16( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vfmul_vv_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv2f16( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv2f16( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vfmul_vv_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv4f16( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv4f16( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vfmul_vv_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv8f16( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv8f16( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vfmul_vv_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv16f16( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv16f16( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vfmul_vv_nxv32f16_nxv32f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv32f16( %0, %1, @@ -226,10 +249,14 @@ i64); define @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv32f16( %0, %1, @@ -246,10 +273,12 @@ i64); define @intrinsic_vfmul_vv_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv1f32( %0, %1, @@ -266,10 +295,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv1f32( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vfmul_vv_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv2f32( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv2f32( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vfmul_vv_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv4f32( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv4f32( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vfmul_vv_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv8f32( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv8f32( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vfmul_vv_nxv16f32_nxv16f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv16f32( %0, %1, @@ -426,10 +471,14 @@ i64); define @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv16f32( %0, %1, @@ -446,10 +495,12 @@ i64); define @intrinsic_vfmul_vv_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv1f64( %0, %1, @@ -466,10 +517,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv1f64( %0, %1, @@ -486,10 +539,12 @@ i64); define @intrinsic_vfmul_vv_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv2f64( %0, %1, @@ -506,10 +561,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv2f64( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vfmul_vv_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv4f64( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv4f64( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vfmul_vv_nxv8f64_nxv8f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfmul.nxv8f64( %0, %1, @@ -586,10 +649,14 @@ i64); define @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv8f64( %0, %1, @@ -606,10 +673,13 @@ i64); define @intrinsic_vfmul_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv1f16.f16( %0, half %1, @@ -626,10 +696,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv1f16.f16( %0, %1, @@ -646,10 +719,13 @@ i64); define @intrinsic_vfmul_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv2f16.f16( %0, half %1, @@ -666,10 +742,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv2f16.f16( %0, %1, @@ -686,10 +765,13 @@ i64); define @intrinsic_vfmul_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv4f16.f16( %0, half %1, @@ -706,10 +788,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv4f16.f16( %0, %1, @@ -726,10 +811,13 @@ i64); define @intrinsic_vfmul_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv8f16.f16( %0, half %1, @@ -746,10 +834,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfmul.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv8f16.f16( %0, %1, @@ -766,10 +857,13 @@ i64); define @intrinsic_vfmul_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv16f16.f16( %0, half %1, @@ -786,10 +880,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfmul.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv16f16.f16( %0, %1, @@ -806,10 +903,13 @@ i64); define @intrinsic_vfmul_vf_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv32f16.f16( %0, half %1, @@ -826,10 +926,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfmul.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv32f16.f16( %0, %1, @@ -846,10 +949,13 @@ i64); define @intrinsic_vfmul_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv1f32.f32( %0, float %1, @@ -866,10 +972,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv1f32.f32( %0, %1, @@ -886,10 +995,13 @@ i64); define @intrinsic_vfmul_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv2f32.f32( %0, float %1, @@ -906,10 +1018,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv2f32.f32( %0, %1, @@ -926,10 +1041,13 @@ i64); define @intrinsic_vfmul_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv4f32.f32( %0, float %1, @@ -946,10 +1064,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfmul.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv4f32.f32( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vfmul_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv8f32.f32( %0, float %1, @@ -986,10 +1110,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfmul.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv8f32.f32( %0, %1, @@ -1006,10 +1133,13 @@ i64); define @intrinsic_vfmul_vf_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv16f32.f32( %0, float %1, @@ -1026,10 +1156,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfmul.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv16f32.f32( %0, %1, @@ -1046,10 +1179,13 @@ i64); define @intrinsic_vfmul_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv1f64.f64( %0, double %1, @@ -1066,10 +1202,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv1f64.f64( %0, %1, @@ -1086,10 +1225,13 @@ i64); define @intrinsic_vfmul_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv2f64.f64( %0, double %1, @@ -1106,10 +1248,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfmul.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv2f64.f64( %0, %1, @@ -1126,10 +1271,13 @@ i64); define @intrinsic_vfmul_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv4f64.f64( %0, double %1, @@ -1146,10 +1294,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfmul.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv4f64.f64( %0, %1, @@ -1166,10 +1317,13 @@ i64); define @intrinsic_vfmul_vf_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfmul.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfmul.nxv8f64.f64( %0, double %1, @@ -1186,10 +1340,13 @@ i64); define @intrinsic_vfmul_mask_vf_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfmul.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfmul.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfmul_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfmul_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfmul_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfmul_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v18 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK-LABEL: vfmul_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v20 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,9 +133,8 @@ define @vfmul_vv_nxv32f16( %va, %vb) { ; CHECK-LABEL: vfmul_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vfmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -146,7 +145,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -158,7 +157,7 @@ ; CHECK-LABEL: vfmul_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -168,7 +167,7 @@ ; CHECK-LABEL: vfmul_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +179,7 @@ ; CHECK-LABEL: vfmul_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -190,7 +189,7 @@ ; CHECK-LABEL: vfmul_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -202,7 +201,7 @@ ; CHECK-LABEL: vfmul_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v18 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -212,7 +211,7 @@ ; CHECK-LABEL: vfmul_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +223,7 @@ ; CHECK-LABEL: vfmul_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v20 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -234,7 +233,7 @@ ; CHECK-LABEL: vfmul_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -246,7 +245,7 @@ ; CHECK-LABEL: vfmul_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,9 +256,8 @@ define @vfmul_vv_nxv16f32( %va, %vb) { ; CHECK-LABEL: vfmul_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vfmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -269,7 +267,7 @@ ; CHECK-LABEL: vfmul_vf_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +279,7 @@ ; CHECK-LABEL: vfmul_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -291,7 +289,7 @@ ; CHECK-LABEL: vfmul_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -303,7 +301,7 @@ ; CHECK-LABEL: vfmul_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v18 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -313,7 +311,7 @@ ; CHECK-LABEL: vfmul_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -325,7 +323,7 @@ ; CHECK-LABEL: vfmul_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v20 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -335,7 +333,7 @@ ; CHECK-LABEL: vfmul_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,9 +344,8 @@ define @vfmul_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: vfmul_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vfmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -358,7 +355,7 @@ ; CHECK-LABEL: vfmul_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -370,7 +367,7 @@ ; CHECK-LABEL: vfmul_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfmul_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfmul_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfmul_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfmul_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v18 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK-LABEL: vfmul_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v20 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,9 +133,8 @@ define @vfmul_vv_nxv32f16( %va, %vb) { ; CHECK-LABEL: vfmul_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vfmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -146,7 +145,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -158,7 +157,7 @@ ; CHECK-LABEL: vfmul_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -168,7 +167,7 @@ ; CHECK-LABEL: vfmul_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +179,7 @@ ; CHECK-LABEL: vfmul_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -190,7 +189,7 @@ ; CHECK-LABEL: vfmul_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -202,7 +201,7 @@ ; CHECK-LABEL: vfmul_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v18 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -212,7 +211,7 @@ ; CHECK-LABEL: vfmul_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +223,7 @@ ; CHECK-LABEL: vfmul_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v20 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -234,7 +233,7 @@ ; CHECK-LABEL: vfmul_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -246,7 +245,7 @@ ; CHECK-LABEL: vfmul_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,9 +256,8 @@ define @vfmul_vv_nxv16f32( %va, %vb) { ; CHECK-LABEL: vfmul_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vfmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -269,7 +267,7 @@ ; CHECK-LABEL: vfmul_vf_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +279,7 @@ ; CHECK-LABEL: vfmul_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v17 +; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -291,7 +289,7 @@ ; CHECK-LABEL: vfmul_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -303,7 +301,7 @@ ; CHECK-LABEL: vfmul_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v18 +; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -313,7 +311,7 @@ ; CHECK-LABEL: vfmul_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -325,7 +323,7 @@ ; CHECK-LABEL: vfmul_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfmul.vv v16, v16, v20 +; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -335,7 +333,7 @@ ; CHECK-LABEL: vfmul_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,9 +344,8 @@ define @vfmul_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: vfmul_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vfmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fmul %va, %vb ret %vc @@ -358,7 +355,7 @@ ; CHECK-LABEL: vfmul_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -370,7 +367,7 @@ ; CHECK-LABEL: vfmul_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmul.vf v16, v16, fa0 +; CHECK-NEXT: vfmul.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll @@ -8,7 +8,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: @@ -22,7 +22,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: @@ -36,7 +36,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: @@ -50,7 +50,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: @@ -64,7 +64,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: @@ -78,7 +78,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: # kill: def $f10_h killed $f10_h killed $f10_f ; CHECK-NEXT: ret entry: @@ -92,7 +92,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret entry: %a = call float @llvm.riscv.vfmv.f.s.nxv1f32( %0) @@ -105,7 +105,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret entry: %a = call float @llvm.riscv.vfmv.f.s.nxv2f32( %0) @@ -118,7 +118,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m2,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret entry: %a = call float @llvm.riscv.vfmv.f.s.nxv4f32( %0) @@ -131,7 +131,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m4,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret entry: %a = call float @llvm.riscv.vfmv.f.s.nxv8f32( %0) @@ -144,7 +144,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m8,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret entry: %a = call float @llvm.riscv.vfmv.f.s.nxv16f32( %0) @@ -157,7 +157,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret entry: %a = call double @llvm.riscv.vfmv.f.s.nxv1f64( %0) @@ -170,7 +170,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e64,m2,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret entry: %a = call double @llvm.riscv.vfmv.f.s.nxv2f64( %0) @@ -183,7 +183,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e64,m4,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret entry: %a = call double @llvm.riscv.vfmv.f.s.nxv4f64( %0) @@ -196,7 +196,7 @@ ; CHECK-LABEL: intrinsic_vfmv.f.s_s_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmv.f.s fa0, v16 +; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret entry: %a = call double @llvm.riscv.vfmv.f.s.nxv8f64( %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll @@ -8,7 +8,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv1f16( %0, half %1, i32 %2) @@ -22,7 +22,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv2f16( %0, half %1, i32 %2) @@ -36,7 +36,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv4f16( %0, half %1, i32 %2) @@ -50,7 +50,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv8f16( %0, half %1, i32 %2) @@ -64,7 +64,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv16f16( %0, half %1, i32 %2) @@ -78,7 +78,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv32f16( %0, half %1, i32 %2) @@ -91,7 +91,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv1f32( %0, float %1, i32 %2) @@ -104,7 +104,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv2f32( %0, float %1, i32 %2) @@ -117,7 +117,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv4f32( %0, float %1, i32 %2) @@ -130,7 +130,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv8f32( %0, float %1, i32 %2) @@ -143,7 +143,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv16f32( %0, float %1, i32 %2) @@ -156,7 +156,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv1f64( %0, double %1, i32 %2) @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv2f64( %0, double %1, i32 %2) @@ -182,7 +182,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv4f64( %0, double %1, i32 %2) @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv8f64( %0, double %1, i32 %2) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll @@ -8,7 +8,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv1f16( %0, half %1, i64 %2) @@ -22,7 +22,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv2f16( %0, half %1, i64 %2) @@ -36,7 +36,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv4f16( %0, half %1, i64 %2) @@ -50,7 +50,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv8f16( %0, half %1, i64 %2) @@ -64,7 +64,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv16f16( %0, half %1, i64 %2) @@ -78,7 +78,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv32f16( %0, half %1, i64 %2) @@ -91,7 +91,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv1f32( %0, float %1, i64 %2) @@ -104,7 +104,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv2f32( %0, float %1, i64 %2) @@ -117,7 +117,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv4f32( %0, float %1, i64 %2) @@ -130,7 +130,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv8f32( %0, float %1, i64 %2) @@ -143,7 +143,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv16f32( %0, float %1, i64 %2) @@ -156,7 +156,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv1f64( %0, double %1, i64 %2) @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv2f64( %0, double %1, i64 %2) @@ -182,7 +182,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv4f64( %0, double %1, i64 %2) @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vfmv.s.f v16, fa0 +; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmv.s.f.nxv8f64( %0, double %1, i64 %2) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfmv.v.f.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfmv.v.f_f_nxv1f16(half %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv1f16( half %0, i32 %1) @@ -21,10 +25,13 @@ i32); define @intrinsic_vfmv.v.f_f_nxv2f16(half %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv2f16( half %0, i32 %1) @@ -37,10 +44,13 @@ i32); define @intrinsic_vfmv.v.f_f_nxv4f16(half %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16 -; CHECK: vsetvli {{.*}}, a0, e16,m1,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv4f16( half %0, i32 %1) @@ -53,10 +63,13 @@ i32); define @intrinsic_vfmv.v.f_f_nxv8f16(half %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16 -; CHECK: vsetvli {{.*}}, a0, e16,m2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv8f16( half %0, i32 %1) @@ -69,10 +82,13 @@ i32); define @intrinsic_vfmv.v.f_f_nxv16f16(half %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16 -; CHECK: vsetvli {{.*}}, a0, e16,m4,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv16f16( half %0, i32 %1) @@ -85,10 +101,13 @@ i32); define @intrinsic_vfmv.v.f_f_nxv32f16(half %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16 -; CHECK: vsetvli {{.*}}, a0, e16,m8,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv32f16( half %0, i32 %1) @@ -101,10 +120,12 @@ i32); define @intrinsic_vfmv.v.f_f_nxv1f32(float %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv1f32( float %0, i32 %1) @@ -117,10 +138,12 @@ i32); define @intrinsic_vfmv.v.f_f_nxv2f32(float %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32 -; CHECK: vsetvli {{.*}}, a0, e32,m1,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv2f32( float %0, i32 %1) @@ -133,10 +156,12 @@ i32); define @intrinsic_vfmv.v.f_f_nxv4f32(float %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32 -; CHECK: vsetvli {{.*}}, a0, e32,m2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv4f32( float %0, i32 %1) @@ -149,10 +174,12 @@ i32); define @intrinsic_vfmv.v.f_f_nxv8f32(float %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32 -; CHECK: vsetvli {{.*}}, a0, e32,m4,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv8f32( float %0, i32 %1) @@ -165,10 +192,12 @@ i32); define @intrinsic_vfmv.v.f_f_nxv16f32(float %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32 -; CHECK: vsetvli {{.*}}, a0, e32,m8,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv16f32( float %0, i32 %1) @@ -181,10 +210,12 @@ i32); define @intrinsic_vfmv.v.f_f_nxv1f64(double %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64 -; CHECK: vsetvli {{.*}}, a0, e64,m1,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv1f64( double %0, i32 %1) @@ -197,10 +228,12 @@ i32); define @intrinsic_vfmv.v.f_f_nxv2f64(double %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64 -; CHECK: vsetvli {{.*}}, a0, e64,m2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv2f64( double %0, i32 %1) @@ -213,10 +246,12 @@ i32); define @intrinsic_vfmv.v.f_f_nxv4f64(double %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64 -; CHECK: vsetvli {{.*}}, a0, e64,m4,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv4f64( double %0, i32 %1) @@ -229,10 +264,12 @@ i32); define @intrinsic_vfmv.v.f_f_nxv8f64(double %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64 -; CHECK: vsetvli {{.*}}, a0, e64,m8,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv8f64( double %0, i32 %1) @@ -241,10 +278,12 @@ } define @intrinsic_vfmv.v.f_zero_nxv1f16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv1f16( half 0.0, i32 %0) @@ -253,10 +292,12 @@ } define @intrinsic_vmv.v.i_zero_nxv2f16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv2f16( half 0.0, i32 %0) @@ -265,10 +306,12 @@ } define @intrinsic_vmv.v.i_zero_nxv4f16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f16 -; CHECK: vsetvli {{.*}}, a0, e16,m1,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv4f16( half 0.0, i32 %0) @@ -277,10 +320,12 @@ } define @intrinsic_vmv.v.i_zero_nxv8f16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f16 -; CHECK: vsetvli {{.*}}, a0, e16,m2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv8f16( half 0.0, i32 %0) @@ -289,10 +334,12 @@ } define @intrinsic_vmv.v.i_zero_nxv16f16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f16 -; CHECK: vsetvli {{.*}}, a0, e16,m4,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv16f16( half 0.0, i32 %0) @@ -301,10 +348,12 @@ } define @intrinsic_vmv.v.i_zero_nxv32f16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv32f16 -; CHECK: vsetvli {{.*}}, a0, e16,m8,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv32f16( half 0.0, i32 %0) @@ -313,10 +362,12 @@ } define @intrinsic_vmv.v.i_zero_nxv1f32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv1f32( float 0.0, i32 %0) @@ -325,10 +376,12 @@ } define @intrinsic_vmv.v.i_zero_nxv2f32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f32 -; CHECK: vsetvli {{.*}}, a0, e32,m1,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv2f32( float 0.0, i32 %0) @@ -337,10 +390,12 @@ } define @intrinsic_vmv.v.i_zero_nxv4f32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f32 -; CHECK: vsetvli {{.*}}, a0, e32,m2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv4f32( float 0.0, i32 %0) @@ -349,10 +404,12 @@ } define @intrinsic_vmv.v.i_zero_nxv8f32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f32 -; CHECK: vsetvli {{.*}}, a0, e32,m4,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv8f32( float 0.0, i32 %0) @@ -361,10 +418,12 @@ } define @intrinsic_vmv.v.i_zero_nxv16f32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f32 -; CHECK: vsetvli {{.*}}, a0, e32,m8,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv16f32( float 0.0, i32 %0) @@ -373,10 +432,12 @@ } define @intrinsic_vmv.v.i_zero_nxv1f64(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f64 -; CHECK: vsetvli {{.*}}, a0, e64,m1,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv1f64( double 0.0, i32 %0) @@ -385,10 +446,12 @@ } define @intrinsic_vmv.v.i_zero_nxv2f64(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f64 -; CHECK: vsetvli {{.*}}, a0, e64,m2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv2f64( double 0.0, i32 %0) @@ -397,10 +460,12 @@ } define @intrinsic_vmv.v.i_zero_nxv4f64(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f64 -; CHECK: vsetvli {{.*}}, a0, e64,m4,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv4f64( double 0.0, i32 %0) @@ -409,10 +474,12 @@ } define @intrinsic_vmv.v.i_zero_nxv8f64(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f64 -; CHECK: vsetvli {{.*}}, a0, e64,m8,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv8f64( double 0.0, i32 %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfmv.v.f.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfmv.v.f_f_nxv1f16(half %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv1f16( half %0, i64 %1) @@ -21,10 +25,13 @@ i64); define @intrinsic_vfmv.v.f_f_nxv2f16(half %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv2f16( half %0, i64 %1) @@ -37,10 +44,13 @@ i64); define @intrinsic_vfmv.v.f_f_nxv4f16(half %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16 -; CHECK: vsetvli {{.*}}, a0, e16,m1,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv4f16( half %0, i64 %1) @@ -53,10 +63,13 @@ i64); define @intrinsic_vfmv.v.f_f_nxv8f16(half %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16 -; CHECK: vsetvli {{.*}}, a0, e16,m2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv8f16( half %0, i64 %1) @@ -69,10 +82,13 @@ i64); define @intrinsic_vfmv.v.f_f_nxv16f16(half %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16 -; CHECK: vsetvli {{.*}}, a0, e16,m4,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv16f16( half %0, i64 %1) @@ -85,10 +101,13 @@ i64); define @intrinsic_vfmv.v.f_f_nxv32f16(half %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16 -; CHECK: vsetvli {{.*}}, a0, e16,m8,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv32f16( half %0, i64 %1) @@ -101,10 +120,12 @@ i64); define @intrinsic_vfmv.v.f_f_nxv1f32(float %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv1f32( float %0, i64 %1) @@ -117,10 +138,12 @@ i64); define @intrinsic_vfmv.v.f_f_nxv2f32(float %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32 -; CHECK: vsetvli {{.*}}, a0, e32,m1,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv2f32( float %0, i64 %1) @@ -133,10 +156,12 @@ i64); define @intrinsic_vfmv.v.f_f_nxv4f32(float %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32 -; CHECK: vsetvli {{.*}}, a0, e32,m2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv4f32( float %0, i64 %1) @@ -149,10 +174,12 @@ i64); define @intrinsic_vfmv.v.f_f_nxv8f32(float %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32 -; CHECK: vsetvli {{.*}}, a0, e32,m4,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv8f32( float %0, i64 %1) @@ -165,10 +192,12 @@ i64); define @intrinsic_vfmv.v.f_f_nxv16f32(float %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32 -; CHECK: vsetvli {{.*}}, a0, e32,m8,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv16f32( float %0, i64 %1) @@ -181,10 +210,12 @@ i64); define @intrinsic_vfmv.v.f_f_nxv1f64(double %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64 -; CHECK: vsetvli {{.*}}, a0, e64,m1,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv1f64( double %0, i64 %1) @@ -197,10 +228,12 @@ i64); define @intrinsic_vfmv.v.f_f_nxv2f64(double %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64 -; CHECK: vsetvli {{.*}}, a0, e64,m2,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv2f64( double %0, i64 %1) @@ -213,10 +246,12 @@ i64); define @intrinsic_vfmv.v.f_f_nxv4f64(double %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64 -; CHECK: vsetvli {{.*}}, a0, e64,m4,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv4f64( double %0, i64 %1) @@ -229,10 +264,12 @@ i64); define @intrinsic_vfmv.v.f_f_nxv8f64(double %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64 -; CHECK: vsetvli {{.*}}, a0, e64,m8,ta,mu -; CHECK: vfmv.v.f {{v[0-9]+}}, fa0 %a = call @llvm.riscv.vfmv.v.f.nxv8f64( double %0, i64 %1) @@ -241,10 +278,12 @@ } define @intrinsic_vfmv.v.f_zero_nxv1f16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv1f16( half 0.0, i64 %0) @@ -253,10 +292,12 @@ } define @intrinsic_vmv.v.i_zero_nxv2f16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv2f16( half 0.0, i64 %0) @@ -265,10 +306,12 @@ } define @intrinsic_vmv.v.i_zero_nxv4f16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f16 -; CHECK: vsetvli {{.*}}, a0, e16,m1,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv4f16( half 0.0, i64 %0) @@ -277,10 +320,12 @@ } define @intrinsic_vmv.v.i_zero_nxv8f16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f16 -; CHECK: vsetvli {{.*}}, a0, e16,m2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv8f16( half 0.0, i64 %0) @@ -289,10 +334,12 @@ } define @intrinsic_vmv.v.i_zero_nxv16f16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f16 -; CHECK: vsetvli {{.*}}, a0, e16,m4,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv16f16( half 0.0, i64 %0) @@ -301,10 +348,12 @@ } define @intrinsic_vmv.v.i_zero_nxv32f16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv32f16 -; CHECK: vsetvli {{.*}}, a0, e16,m8,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv32f16( half 0.0, i64 %0) @@ -313,10 +362,12 @@ } define @intrinsic_vmv.v.i_zero_nxv1f32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv1f32( float 0.0, i64 %0) @@ -325,10 +376,12 @@ } define @intrinsic_vmv.v.i_zero_nxv2f32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f32 -; CHECK: vsetvli {{.*}}, a0, e32,m1,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv2f32( float 0.0, i64 %0) @@ -337,10 +390,12 @@ } define @intrinsic_vmv.v.i_zero_nxv4f32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f32 -; CHECK: vsetvli {{.*}}, a0, e32,m2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv4f32( float 0.0, i64 %0) @@ -349,10 +404,12 @@ } define @intrinsic_vmv.v.i_zero_nxv8f32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f32 -; CHECK: vsetvli {{.*}}, a0, e32,m4,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv8f32( float 0.0, i64 %0) @@ -361,10 +418,12 @@ } define @intrinsic_vmv.v.i_zero_nxv16f32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv16f32 -; CHECK: vsetvli {{.*}}, a0, e32,m8,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv16f32( float 0.0, i64 %0) @@ -373,10 +432,12 @@ } define @intrinsic_vmv.v.i_zero_nxv1f64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv1f64 -; CHECK: vsetvli {{.*}}, a0, e64,m1,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv1f64( double 0.0, i64 %0) @@ -385,10 +446,12 @@ } define @intrinsic_vmv.v.i_zero_nxv2f64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv2f64 -; CHECK: vsetvli {{.*}}, a0, e64,m2,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv2f64( double 0.0, i64 %0) @@ -397,10 +460,12 @@ } define @intrinsic_vmv.v.i_zero_nxv4f64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv4f64 -; CHECK: vsetvli {{.*}}, a0, e64,m4,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv4f64( double 0.0, i64 %0) @@ -409,10 +474,12 @@ } define @intrinsic_vmv.v.i_zero_nxv8f64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.i_zero_nxv8f64 -; CHECK: vsetvli {{.*}}, a0, e64,m8,ta,mu -; CHECK: vmv.v.i {{v[0-9]+}}, 0 %a = call @llvm.riscv.vfmv.v.f.nxv8f64( double 0.0, i64 %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32( %0, %1, @@ -185,10 +211,13 @@ i32); define @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64( %0, i32 %1) @@ -203,10 +232,12 @@ i32); define @intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64( %0, %1, @@ -221,10 +252,13 @@ i32); define @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64( %0, i32 %1) @@ -239,10 +273,12 @@ i32); define @intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64( %0, %1, @@ -257,10 +293,13 @@ i32); define @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64( %0, i32 %1) @@ -275,10 +314,12 @@ i32); define @intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64( %0, %1, @@ -293,10 +334,13 @@ i32); define @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64( %0, i32 %1) @@ -311,10 +355,12 @@ i32); define @intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.f.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfncvt_mask_f.x.w_nxv1f32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfncvt_mask_f.x.w_nxv2f32_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f32_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f32_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfncvt_mask_f.x.w_nxv4f32_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f32_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f32_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.f.x.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfncvt_mask_f.x.w_nxv8f32_nxv8i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f32_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.f.x.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f32_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.f.x.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfncvt_mask_f.xu.w_nxv1f32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfncvt_mask_f.xu.w_nxv2f32_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f32_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f32_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfncvt_mask_f.xu.w_nxv4f32_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f32_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f32_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.f.xu.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfncvt_mask_f.xu.w_nxv8f32_nxv8i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f32_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f32_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.f.xu.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv1f16_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv2f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv4f16_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f16.nxv4f32( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv8f16_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f16.nxv8f32( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv16f16_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv16f16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv16f16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16f16.nxv16f32( %0, %1, @@ -185,10 +211,13 @@ i32); define @intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64( %0, i32 %1) @@ -203,10 +232,12 @@ i32); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv1f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f32.nxv1f64( %0, %1, @@ -221,10 +252,13 @@ i32); define @intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64( %0, i32 %1) @@ -239,10 +273,12 @@ i32); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv2f32_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f32.nxv2f64( %0, %1, @@ -257,10 +293,13 @@ i32); define @intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64( %0, i32 %1) @@ -275,10 +314,12 @@ i32); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv4f32_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f32.nxv4f64( %0, %1, @@ -293,10 +334,13 @@ i32); define @intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64( %0, i32 %1) @@ -311,10 +355,12 @@ i32); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv8f32_nxv8f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv1f16_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f16.nxv1f32( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f16.nxv2f32( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv2f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f16.nxv2f32( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f16.nxv4f32( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv4f16_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f16.nxv4f32( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f16.nxv8f32( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv8f16_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f16.nxv8f32( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv16f16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv16f16.nxv16f32( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv16f16_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv16f16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv16f16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv16f16.nxv16f32( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv1f32.nxv1f64( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv1f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv1f32.nxv1f64( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv2f32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv2f32.nxv2f64( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv2f32_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv2f32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv2f32.nxv2f64( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv4f32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv4f32.nxv4f64( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv4f32_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv4f32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv4f32.nxv4f64( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rod.f.f.w_nxv8f32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rod.f.f.w.nxv8f32.nxv8f64( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfncvt_mask_rod.f.f.w_nxv8f32_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.rod.f.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rod.f.f.w_nxv8f32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.rod.f.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rod.f.f.w.mask.nxv8f32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i8_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i8.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i8_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i8.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i8_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i8.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i8_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i8.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i8_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i8.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16( %0, i32 %1) @@ -203,10 +232,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv32i8_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv32i8.nxv32f16( %0, %1, @@ -221,10 +252,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32( %0, i32 %1) @@ -239,10 +273,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i16_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i16.nxv1f32( %0, %1, @@ -257,10 +293,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32( %0, i32 %1) @@ -275,10 +314,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i16.nxv2f32( %0, %1, @@ -293,10 +334,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32( %0, i32 %1) @@ -311,10 +355,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i16_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i16.nxv4f32( %0, %1, @@ -329,10 +375,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32( %0, i32 %1) @@ -347,10 +396,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i16_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i16.nxv8f32( %0, %1, @@ -365,10 +416,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32( %0, i32 %1) @@ -383,10 +437,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i16_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i16.nxv16f32( %0, %1, @@ -401,10 +457,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64( %0, i32 %1) @@ -419,10 +478,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i32.nxv1f64( %0, %1, @@ -437,10 +498,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64( %0, i32 %1) @@ -455,10 +519,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i32_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i32.nxv2f64( %0, %1, @@ -473,10 +539,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64( %0, i32 %1) @@ -491,10 +560,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i32_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i32.nxv4f64( %0, %1, @@ -509,10 +580,13 @@ i32); define @intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64( %0, i32 %1) @@ -527,10 +601,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i32_nxv8f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i8_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i8.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i8.nxv2f16( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i8_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i8.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i8.nxv4f16( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i8_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i8.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i8.nxv8f16( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i8_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i8.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i8.nxv16f16( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i8_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i8.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv32i8.nxv32f16( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv32i8_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv32i8.nxv32f16( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i16.nxv1f32( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i16_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i16.nxv1f32( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i16.nxv2f32( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i16.nxv2f32( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i16.nxv4f32( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i16_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i16.nxv4f32( %0, %1, @@ -329,10 +375,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i16.nxv8f32( %0, i64 %1) @@ -347,10 +396,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i16_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i16.nxv8f32( %0, %1, @@ -365,10 +416,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv16i16.nxv16f32( %0, i64 %1) @@ -383,10 +437,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i16_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv16i16.nxv16f32( %0, %1, @@ -401,10 +457,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i32.nxv1f64( %0, i64 %1) @@ -419,10 +478,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv1i32.nxv1f64( %0, %1, @@ -437,10 +498,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv2i32.nxv2f64( %0, i64 %1) @@ -455,10 +519,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i32_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv2i32.nxv2f64( %0, %1, @@ -473,10 +539,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv4i32.nxv4f64( %0, i64 %1) @@ -491,10 +560,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i32_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv4i32.nxv4f64( %0, %1, @@ -509,10 +580,13 @@ i64); define @intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.x.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.x.f.w.nxv8i32.nxv8f64( %0, i64 %1) @@ -527,10 +601,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i32_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.x.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.rtz.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.x.f.w.mask.nxv8i32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i8_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i8.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i8_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i8.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i8_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i8.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i8_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i8.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i8_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i8.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16( %0, i32 %1) @@ -203,10 +232,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv32i8_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv32i8.nxv32f16( %0, %1, @@ -221,10 +252,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32( %0, i32 %1) @@ -239,10 +273,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i16_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i16.nxv1f32( %0, %1, @@ -257,10 +293,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32( %0, i32 %1) @@ -275,10 +314,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i16.nxv2f32( %0, %1, @@ -293,10 +334,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32( %0, i32 %1) @@ -311,10 +355,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i16_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i16.nxv4f32( %0, %1, @@ -329,10 +375,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32( %0, i32 %1) @@ -347,10 +396,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i16_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i16.nxv8f32( %0, %1, @@ -365,10 +416,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32( %0, i32 %1) @@ -383,10 +437,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i16_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i16.nxv16f32( %0, %1, @@ -401,10 +457,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64( %0, i32 %1) @@ -419,10 +478,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i32.nxv1f64( %0, %1, @@ -437,10 +498,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64( %0, i32 %1) @@ -455,10 +519,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i32_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i32.nxv2f64( %0, %1, @@ -473,10 +539,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64( %0, i32 %1) @@ -491,10 +560,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i32_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i32.nxv4f64( %0, %1, @@ -509,10 +580,13 @@ i32); define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64( %0, i32 %1) @@ -527,10 +601,12 @@ i32); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i32_nxv8f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i8_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i8.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i8.nxv2f16( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i8_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i8.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i8.nxv4f16( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i8_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i8.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i8.nxv8f16( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i8_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i8.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i8.nxv16f16( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i8_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i8.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv32i8.nxv32f16( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv32i8_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv32i8.nxv32f16( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i16.nxv1f32( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i16_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i16.nxv1f32( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i16.nxv2f32( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i16.nxv2f32( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i16.nxv4f32( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i16_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i16.nxv4f32( %0, %1, @@ -329,10 +375,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i16.nxv8f32( %0, i64 %1) @@ -347,10 +396,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i16_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i16.nxv8f32( %0, %1, @@ -365,10 +416,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv16i16.nxv16f32( %0, i64 %1) @@ -383,10 +437,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i16_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv16i16.nxv16f32( %0, %1, @@ -401,10 +457,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i32.nxv1f64( %0, i64 %1) @@ -419,10 +478,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv1i32.nxv1f64( %0, %1, @@ -437,10 +498,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv2i32.nxv2f64( %0, i64 %1) @@ -455,10 +519,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i32_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv2i32.nxv2f64( %0, %1, @@ -473,10 +539,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv4i32.nxv4f64( %0, i64 %1) @@ -491,10 +560,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i32_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv4i32.nxv4f64( %0, %1, @@ -509,10 +580,13 @@ i64); define @intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_rtz.xu.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.nxv8i32.nxv8f64( %0, i64 %1) @@ -527,10 +601,12 @@ i64); define @intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i32_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_rtz.xu.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.rtz.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.rtz.xu.f.w.mask.nxv8i32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16( %0, i32 %1) @@ -203,10 +232,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16( %0, %1, @@ -221,10 +252,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32( %0, i32 %1) @@ -239,10 +273,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32( %0, %1, @@ -257,10 +293,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32( %0, i32 %1) @@ -275,10 +314,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32( %0, %1, @@ -293,10 +334,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32( %0, i32 %1) @@ -311,10 +355,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32( %0, %1, @@ -329,10 +375,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32( %0, i32 %1) @@ -347,10 +396,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32( %0, %1, @@ -365,10 +416,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32( %0, i32 %1) @@ -383,10 +437,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32( %0, %1, @@ -401,10 +457,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64( %0, i32 %1) @@ -419,10 +478,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64( %0, %1, @@ -437,10 +498,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64( %0, i32 %1) @@ -455,10 +519,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64( %0, %1, @@ -473,10 +539,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64( %0, i32 %1) @@ -491,10 +560,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64( %0, %1, @@ -509,10 +580,13 @@ i32); define @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64( %0, i32 %1) @@ -527,10 +601,12 @@ i32); define @intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32( %0, %1, @@ -329,10 +375,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32( %0, i64 %1) @@ -347,10 +396,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32( %0, %1, @@ -365,10 +416,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32( %0, i64 %1) @@ -383,10 +437,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32( %0, %1, @@ -401,10 +457,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64( %0, i64 %1) @@ -419,10 +478,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64( %0, %1, @@ -437,10 +498,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64( %0, i64 %1) @@ -455,10 +519,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64( %0, %1, @@ -473,10 +539,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64( %0, i64 %1) @@ -491,10 +560,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64( %0, %1, @@ -509,10 +580,13 @@ i64); define @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.x.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64( %0, i64 %1) @@ -527,10 +601,12 @@ i64); define @intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.x.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16( %0, i32 %1) @@ -203,10 +232,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16( %0, %1, @@ -221,10 +252,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32( %0, i32 %1) @@ -239,10 +273,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32( %0, %1, @@ -257,10 +293,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32( %0, i32 %1) @@ -275,10 +314,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32( %0, %1, @@ -293,10 +334,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32( %0, i32 %1) @@ -311,10 +355,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32( %0, %1, @@ -329,10 +375,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32( %0, i32 %1) @@ -347,10 +396,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32( %0, %1, @@ -365,10 +416,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32( %0, i32 %1) @@ -383,10 +437,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32( %0, %1, @@ -401,10 +457,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64( %0, i32 %1) @@ -419,10 +478,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64( %0, %1, @@ -437,10 +498,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64( %0, i32 %1) @@ -455,10 +519,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64( %0, %1, @@ -473,10 +539,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64( %0, i32 %1) @@ -491,10 +560,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64( %0, %1, @@ -509,10 +580,13 @@ i32); define @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64( %0, i32 %1) @@ -527,10 +601,12 @@ i32); define @intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32( %0, %1, @@ -329,10 +375,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32( %0, i64 %1) @@ -347,10 +396,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32( %0, %1, @@ -365,10 +416,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32( %0, i64 %1) @@ -383,10 +437,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32( %0, %1, @@ -401,10 +457,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64( %0, i64 %1) @@ -419,10 +478,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64( %0, %1, @@ -437,10 +498,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64( %0, i64 %1) @@ -455,10 +519,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64( %0, %1, @@ -473,10 +539,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64( %0, i64 %1) @@ -491,10 +560,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64( %0, %1, @@ -509,10 +580,13 @@ i64); define @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfncvt.xu.f.w v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64( %0, i64 %1) @@ -527,10 +601,12 @@ i64); define @intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfncvt.xu.f.w {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20 +; CHECK-NEXT: vfnmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20 +; CHECK-NEXT: vfnmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20 +; CHECK-NEXT: vfnmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f32.f32( @@ -1011,7 +999,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1039,7 +1027,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1067,7 +1055,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1095,7 +1083,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1123,7 +1111,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1151,7 +1139,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20 +; CHECK-NEXT: vfnmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20 +; CHECK-NEXT: vfnmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20 +; CHECK-NEXT: vfnmacc.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmacc.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f32.f32( @@ -1008,7 +996,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv1f64.f64( @@ -1032,7 +1020,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f64.f64( @@ -1056,7 +1044,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv2f64.f64( @@ -1080,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f64.f64( @@ -1104,7 +1092,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.nxv4f64.f64( @@ -1128,7 +1116,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20 +; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20 +; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20 +; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f32.f32( @@ -1011,7 +999,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1039,7 +1027,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1067,7 +1055,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1095,7 +1083,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1123,7 +1111,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1151,7 +1139,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20 +; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20 +; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18 +; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20 +; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmadd.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f32.f32( @@ -1008,7 +996,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv1f64.f64( @@ -1032,7 +1020,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f64.f64( @@ -1056,7 +1044,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv2f64.f64( @@ -1080,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f64.f64( @@ -1104,7 +1092,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20 +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.nxv4f64.f64( @@ -1128,7 +1116,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmadd.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmadd.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20 +; CHECK-NEXT: vfnmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20 +; CHECK-NEXT: vfnmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20 +; CHECK-NEXT: vfnmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f32.f32( @@ -1011,7 +999,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1039,7 +1027,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1067,7 +1055,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1095,7 +1083,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1123,7 +1111,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1151,7 +1139,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20 +; CHECK-NEXT: vfnmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20 +; CHECK-NEXT: vfnmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20 +; CHECK-NEXT: vfnmsac.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsac.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f32.f32( @@ -1008,7 +996,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv1f64.f64( @@ -1032,7 +1020,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f64.f64( @@ -1056,7 +1044,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv2f64.f64( @@ -1080,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f64.f64( @@ -1104,7 +1092,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.nxv4f64.f64( @@ -1128,7 +1116,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20 +; CHECK-NEXT: vfnmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20 +; CHECK-NEXT: vfnmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20 +; CHECK-NEXT: vfnmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f32.f32( @@ -1011,7 +999,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1039,7 +1027,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1067,7 +1055,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1095,7 +1083,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1123,7 +1111,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1151,7 +1139,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20 +; CHECK-NEXT: vfnmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( @@ -194,10 +194,8 @@ define @intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv16f16.nxv16f16( @@ -219,10 +217,8 @@ define @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f32.nxv2f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20 +; CHECK-NEXT: vfnmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f32.nxv4f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( @@ -382,10 +378,8 @@ define @intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv8f32.nxv8f32( @@ -407,10 +401,8 @@ define @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18 +; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f64.nxv1f64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20 +; CHECK-NEXT: vfnmsub.vv v8, v10, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f64.nxv2f64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( @@ -524,10 +516,8 @@ define @intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f64.nxv4f64( @@ -549,10 +539,8 @@ define @intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( @@ -576,7 +564,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f16.f16( @@ -600,7 +588,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f16.f16( @@ -624,7 +612,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f16.f16( @@ -648,7 +636,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f16.f16( @@ -672,7 +660,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f16.f16( @@ -696,7 +684,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f16.f16( @@ -720,7 +708,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv8f16.f16( @@ -744,7 +732,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f16.f16( @@ -768,7 +756,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv16f16.f16( @@ -792,7 +780,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv16f16.f16( @@ -816,7 +804,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f32.f32( @@ -840,7 +828,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f32.f32( @@ -864,7 +852,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f32.f32( @@ -888,7 +876,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f32.f32( @@ -912,7 +900,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f32.f32( @@ -936,7 +924,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f32.f32( @@ -960,7 +948,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv8f32.f32( @@ -984,7 +972,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f32.f32( @@ -1008,7 +996,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv1f64.f64( @@ -1032,7 +1020,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f64.f64( @@ -1056,7 +1044,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv2f64.f64( @@ -1080,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f64.f64( @@ -1104,7 +1092,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20 +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.nxv4f64.f64( @@ -1128,7 +1116,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfnmsub.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfnmsub.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll @@ -11,7 +11,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv1f16.f16( @@ -34,7 +34,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv1f16.f16( @@ -57,7 +57,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv2f16.f16( @@ -80,7 +80,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv2f16.f16( @@ -103,7 +103,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv4f16.f16( @@ -126,7 +126,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv4f16.f16( @@ -149,7 +149,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv8f16.f16( @@ -172,7 +172,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv8f16.f16( @@ -195,7 +195,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv16f16.f16( @@ -218,7 +218,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv16f16.f16( @@ -241,7 +241,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv32f16.f16( @@ -262,11 +262,9 @@ define @intrinsic_vfrdiv_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv32f16.f16( @@ -289,7 +287,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv1f32.f32( @@ -312,7 +310,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv1f32.f32( @@ -335,7 +333,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv2f32.f32( @@ -358,7 +356,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv2f32.f32( @@ -381,7 +379,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv4f32.f32( @@ -404,7 +402,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv4f32.f32( @@ -427,7 +425,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv8f32.f32( @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv8f32.f32( @@ -473,7 +471,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.nxv16f32.f32( @@ -494,11 +492,9 @@ define @intrinsic_vfrdiv_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrdiv.mask.nxv16f32.f32( @@ -524,7 +520,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -551,7 +547,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -578,7 +574,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -605,7 +601,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -632,7 +628,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -659,7 +655,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfrdiv.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -686,7 +682,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfrdiv.vf v16, v16, ft0 +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -709,13 +705,11 @@ ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfrdiv.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfrdiv.nxv1f16.f16( @@ -6,10 +7,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv1f16.f16( %0, half %1, @@ -26,10 +30,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv1f16.f16( %0, %1, @@ -46,10 +53,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv2f16.f16( %0, half %1, @@ -66,10 +76,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv2f16.f16( %0, %1, @@ -86,10 +99,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv4f16.f16( %0, half %1, @@ -106,10 +122,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv4f16.f16( %0, %1, @@ -126,10 +145,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv8f16.f16( %0, half %1, @@ -146,10 +168,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv8f16.f16( %0, %1, @@ -166,10 +191,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv16f16.f16( %0, half %1, @@ -186,10 +214,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv16f16.f16( %0, %1, @@ -206,10 +237,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv32f16.f16( %0, half %1, @@ -226,10 +260,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv32f16.f16( %0, %1, @@ -246,10 +283,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv1f32.f32( %0, float %1, @@ -266,10 +306,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv1f32.f32( %0, %1, @@ -286,10 +329,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv2f32.f32( %0, float %1, @@ -306,10 +352,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv2f32.f32( %0, %1, @@ -326,10 +375,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv4f32.f32( %0, float %1, @@ -346,10 +398,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv4f32.f32( %0, %1, @@ -366,10 +421,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv8f32.f32( %0, float %1, @@ -386,10 +444,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv8f32.f32( %0, %1, @@ -406,10 +467,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv16f32.f32( %0, float %1, @@ -426,10 +490,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv16f32.f32( %0, %1, @@ -446,10 +513,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv1f64.f64( %0, double %1, @@ -466,10 +536,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv1f64.f64( %0, %1, @@ -486,10 +559,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv2f64.f64( %0, double %1, @@ -506,10 +582,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv2f64.f64( %0, %1, @@ -526,10 +605,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv4f64.f64( %0, double %1, @@ -546,10 +628,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv4f64.f64( %0, %1, @@ -566,10 +651,13 @@ i64); define @intrinsic_vfrdiv_vf_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrdiv.nxv8f64.f64( %0, double %1, @@ -586,10 +674,13 @@ i64); define @intrinsic_vfrdiv_mask_vf_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfrdiv.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfrdiv.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrdiv.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18 +; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16.nxv1i1( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18 +; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16.nxv2i1( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18 +; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16.nxv4i1( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v18, v17 +; CHECK-NEXT: vfredmax.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16.nxv8i1( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v20, v17 +; CHECK-NEXT: vfredmax.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16.nxv16i1( @@ -240,10 +240,8 @@ define @intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16( @@ -265,10 +263,8 @@ define @intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.nxv32i1( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18 +; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.nxv1i1( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18 +; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.nxv2i1( @@ -383,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v18, v17 +; CHECK-NEXT: vfredmax.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32( @@ -406,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.nxv4i1( @@ -429,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v20, v17 +; CHECK-NEXT: vfredmax.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv2f32.nxv8f32( @@ -452,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.nxv8i1( @@ -474,10 +470,8 @@ define @intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv2f32.nxv16f32( @@ -499,10 +493,8 @@ define @intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.nxv16i1( @@ -525,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18 +; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv1f64.nxv1f64( @@ -548,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64.nxv1i1( @@ -571,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v18, v17 +; CHECK-NEXT: vfredmax.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv1f64.nxv2f64( @@ -594,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64.nxv2i1( @@ -617,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v20, v17 +; CHECK-NEXT: vfredmax.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv1f64.nxv4f64( @@ -640,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64.nxv4i1( @@ -662,10 +654,8 @@ define @intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.nxv1f64.nxv8f64( @@ -687,10 +677,8 @@ define @intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfredmax.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.nxv8i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16( @@ -7,10 +8,12 @@ i64); define @intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv4f16.nxv1f16( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv4f16.nxv2f16( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv4f16.nxv4f16( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv4f16.nxv8f16( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv4f16.nxv16f16( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv4f16.nxv32f16( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv2f32.nxv1f32( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv2f32.nxv2f32( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv2f32.nxv4f32( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv2f32.nxv8f32( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv2f32.nxv16f32( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv1f64.nxv1f64( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv1f64.nxv2f64( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv1f64.nxv4f64( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmax.nxv1f64.nxv8f64( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18 +; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16.nxv1i1( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18 +; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16.nxv2i1( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18 +; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16.nxv4i1( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v18, v17 +; CHECK-NEXT: vfredmin.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16.nxv8i1( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v20, v17 +; CHECK-NEXT: vfredmin.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16.nxv16i1( @@ -240,10 +240,8 @@ define @intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16( @@ -265,10 +263,8 @@ define @intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.nxv32i1( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18 +; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.nxv1i1( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18 +; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32.nxv2i1( @@ -383,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v18, v17 +; CHECK-NEXT: vfredmin.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32( @@ -406,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32.nxv4i1( @@ -429,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v20, v17 +; CHECK-NEXT: vfredmin.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv2f32.nxv8f32( @@ -452,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32.nxv8i1( @@ -474,10 +470,8 @@ define @intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv2f32.nxv16f32( @@ -499,10 +493,8 @@ define @intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32.nxv16i1( @@ -525,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18 +; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv1f64.nxv1f64( @@ -548,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64.nxv1i1( @@ -571,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v18, v17 +; CHECK-NEXT: vfredmin.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv1f64.nxv2f64( @@ -594,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64.nxv2i1( @@ -617,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v20, v17 +; CHECK-NEXT: vfredmin.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv1f64.nxv4f64( @@ -640,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64.nxv4i1( @@ -662,10 +654,8 @@ define @intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.nxv1f64.nxv8f64( @@ -687,10 +677,8 @@ define @intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfredmin.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64.nxv8i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16( @@ -7,10 +8,12 @@ i64); define @intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv4f16.nxv1f16( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv4f16.nxv2f16( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv4f16.nxv4f16( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv4f16.nxv8f16( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv4f16.nxv16f16( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv4f16.nxv32f16( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv2f32.nxv1f32( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv2f32.nxv2f32( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv2f32.nxv4f32( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv2f32.nxv8f32( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv2f32.nxv16f32( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv1f64.nxv1f64( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv1f64.nxv2f64( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv1f64.nxv4f64( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredmin.nxv1f64.nxv8f64( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18 +; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18 +; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18 +; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v18, v17 +; CHECK-NEXT: vfredosum.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v20, v17 +; CHECK-NEXT: vfredosum.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1( @@ -240,10 +240,8 @@ define @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16( @@ -265,10 +263,8 @@ define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18 +; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18 +; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1( @@ -383,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v18, v17 +; CHECK-NEXT: vfredosum.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32( @@ -406,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1( @@ -429,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v20, v17 +; CHECK-NEXT: vfredosum.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv8f32( @@ -452,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1( @@ -474,10 +470,8 @@ define @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv16f32( @@ -499,10 +493,8 @@ define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1( @@ -525,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18 +; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv1f64( @@ -548,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1( @@ -571,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v18, v17 +; CHECK-NEXT: vfredosum.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv2f64( @@ -594,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1( @@ -617,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v20, v17 +; CHECK-NEXT: vfredosum.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv4f64( @@ -640,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1( @@ -662,10 +654,8 @@ define @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv8f64( @@ -687,10 +677,8 @@ define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfredosum.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16( @@ -7,10 +8,12 @@ i64); define @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv2f32.nxv8f32( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv2f32.nxv16f32( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv1f64.nxv1f64( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv1f64.nxv2f64( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv1f64.nxv4f64( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredosum.nxv1f64.nxv8f64( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18 +; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv4f16.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18 +; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv4f16.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18 +; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv4f16.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v18, v17 +; CHECK-NEXT: vfredsum.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv4f16.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v20, v17 +; CHECK-NEXT: vfredsum.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv4f16.nxv16f16( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1( @@ -240,10 +240,8 @@ define @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv4f16.nxv32f16( @@ -265,10 +263,8 @@ define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18 +; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv2f32.nxv1f32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18 +; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv2f32.nxv2f32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1( @@ -383,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v18, v17 +; CHECK-NEXT: vfredsum.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv2f32.nxv4f32( @@ -406,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1( @@ -429,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v20, v17 +; CHECK-NEXT: vfredsum.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv2f32.nxv8f32( @@ -452,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1( @@ -474,10 +470,8 @@ define @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv2f32.nxv16f32( @@ -499,10 +493,8 @@ define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1( @@ -525,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18 +; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv1f64.nxv1f64( @@ -548,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v17, v18, v0.t +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.nxv1i1( @@ -571,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v18, v17 +; CHECK-NEXT: vfredsum.vs v8, v10, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv1f64.nxv2f64( @@ -594,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v18, v17, v0.t +; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.nxv2i1( @@ -617,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v20, v17 +; CHECK-NEXT: vfredsum.vs v8, v12, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv1f64.nxv4f64( @@ -640,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v20, v17, v0.t +; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.nxv4i1( @@ -662,10 +654,8 @@ define @intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v8, v17 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.nxv1f64.nxv8f64( @@ -687,10 +677,8 @@ define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfredsum.vs v16, v8, v17, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.nxv8i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfredsum.nxv4f16.nxv1f16( @@ -7,10 +8,12 @@ i64); define @intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv4f16.nxv1f16( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv4f16.nxv2f16( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv4f16.nxv4f16( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv4f16.nxv8f16( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv4f16.nxv16f16( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv4f16.nxv32f16( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv2f32.nxv1f32( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv2f32.nxv2f32( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv2f32.nxv4f32( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv2f32.nxv8f32( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv2f32.nxv16f32( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv1f64.nxv1f64( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv1f64.nxv2f64( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv1f64.nxv4f64( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfredsum.nxv1f64.nxv8f64( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll @@ -11,7 +11,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv1f16.f16( @@ -34,7 +34,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv1f16.f16( @@ -57,7 +57,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv2f16.f16( @@ -80,7 +80,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv2f16.f16( @@ -103,7 +103,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv4f16.f16( @@ -126,7 +126,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv4f16.f16( @@ -149,7 +149,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv8f16.f16( @@ -172,7 +172,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv8f16.f16( @@ -195,7 +195,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv16f16.f16( @@ -218,7 +218,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv16f16.f16( @@ -241,7 +241,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv32f16.f16( @@ -262,11 +262,9 @@ define @intrinsic_vfrsub_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv32f16.f16( @@ -289,7 +287,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv1f32.f32( @@ -312,7 +310,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv1f32.f32( @@ -335,7 +333,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv2f32.f32( @@ -358,7 +356,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv2f32.f32( @@ -381,7 +379,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv4f32.f32( @@ -404,7 +402,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv4f32.f32( @@ -427,7 +425,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv8f32.f32( @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv8f32.f32( @@ -473,7 +471,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.nxv16f32.f32( @@ -494,11 +492,9 @@ define @intrinsic_vfrsub_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfrsub.mask.nxv16f32.f32( @@ -524,7 +520,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -551,7 +547,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -578,7 +574,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -605,7 +601,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -632,7 +628,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -659,7 +655,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfrsub.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -686,7 +682,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, ft0 +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -709,13 +705,11 @@ ; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfrsub.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s @@ -7,10 +8,13 @@ i64); define @intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv1f16.f16( %0, half %1, @@ -27,10 +31,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv1f16.f16( %0, %1, @@ -47,10 +54,13 @@ i64); define @intrinsic_vfrsub_vf_nxv2f16_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv2f16.f16( %0, half %1, @@ -67,10 +77,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv2f16.f16( %0, %1, @@ -87,10 +100,13 @@ i64); define @intrinsic_vfrsub_vf_nxv4f16_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv4f16.f16( %0, half %1, @@ -107,10 +123,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv4f16.f16( %0, %1, @@ -127,10 +146,13 @@ i64); define @intrinsic_vfrsub_vf_nxv8f16_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv8f16.f16( %0, half %1, @@ -147,10 +169,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv8f16.f16( %0, %1, @@ -167,10 +192,13 @@ i64); define @intrinsic_vfrsub_vf_nxv16f16_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv16f16.f16( %0, half %1, @@ -187,10 +215,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv16f16.f16( %0, %1, @@ -207,10 +238,13 @@ i64); define @intrinsic_vfrsub_vf_nxv32f16_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv32f16.f16( %0, half %1, @@ -227,10 +261,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv32f16.f16( %0, %1, @@ -247,10 +284,13 @@ i64); define @intrinsic_vfrsub_vf_nxv1f32_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv1f32.f32( %0, float %1, @@ -267,10 +307,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv1f32.f32( %0, %1, @@ -287,10 +330,13 @@ i64); define @intrinsic_vfrsub_vf_nxv2f32_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv2f32.f32( %0, float %1, @@ -307,10 +353,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv2f32.f32( %0, %1, @@ -327,10 +376,13 @@ i64); define @intrinsic_vfrsub_vf_nxv4f32_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv4f32.f32( %0, float %1, @@ -347,10 +399,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv4f32.f32( %0, %1, @@ -367,10 +422,13 @@ i64); define @intrinsic_vfrsub_vf_nxv8f32_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv8f32.f32( %0, float %1, @@ -387,10 +445,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv8f32.f32( %0, %1, @@ -407,10 +468,13 @@ i64); define @intrinsic_vfrsub_vf_nxv16f32_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv16f32.f32( %0, float %1, @@ -427,10 +491,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv16f32.f32( %0, %1, @@ -447,10 +514,13 @@ i64); define @intrinsic_vfrsub_vf_nxv1f64_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv1f64.f64( %0, double %1, @@ -467,10 +537,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv1f64.f64( %0, %1, @@ -487,10 +560,13 @@ i64); define @intrinsic_vfrsub_vf_nxv2f64_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv2f64.f64( %0, double %1, @@ -507,10 +583,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv2f64.f64( %0, %1, @@ -527,10 +606,13 @@ i64); define @intrinsic_vfrsub_vf_nxv4f64_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv4f64.f64( %0, double %1, @@ -547,10 +629,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv4f64.f64( %0, %1, @@ -567,10 +652,13 @@ i64); define @intrinsic_vfrsub_vf_nxv8f64_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfrsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfrsub.nxv8f64.f64( %0, double %1, @@ -587,10 +675,13 @@ i64); define @intrinsic_vfrsub_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfrsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfrsub_mask_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfrsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfrsub.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v17 +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv1f16.nxv1f16( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv1f16.nxv1f16( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v17 +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv2f16.nxv2f16( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv2f16.nxv2f16( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v17 +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv4f16.nxv4f16( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv4f16.nxv4f16( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v18 +; CHECK-NEXT: vfsgnj.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv8f16.nxv8f16( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsgnj.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv8f16.nxv8f16( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v20 +; CHECK-NEXT: vfsgnj.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv16f16.nxv16f16( @@ -207,10 +207,8 @@ define @intrinsic_vfsgnj_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv16f16.nxv16f16( @@ -231,10 +229,8 @@ define @intrinsic_vfsgnj_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv32f16.nxv32f16( @@ -255,11 +251,10 @@ define @intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv32f16.nxv32f16( @@ -281,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v17 +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv1f32.nxv1f32( @@ -303,7 +298,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv1f32.nxv1f32( @@ -325,7 +320,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v17 +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv2f32.nxv2f32( @@ -347,7 +342,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv2f32.nxv2f32( @@ -369,7 +364,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v18 +; CHECK-NEXT: vfsgnj.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv4f32.nxv4f32( @@ -391,7 +386,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsgnj.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv4f32.nxv4f32( @@ -413,7 +408,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v20 +; CHECK-NEXT: vfsgnj.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv8f32.nxv8f32( @@ -434,10 +429,8 @@ define @intrinsic_vfsgnj_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv8f32.nxv8f32( @@ -458,10 +451,8 @@ define @intrinsic_vfsgnj_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv16f32.nxv16f32( @@ -482,11 +473,10 @@ define @intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv16f32.nxv16f32( @@ -508,7 +498,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v17 +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv1f64.nxv1f64( @@ -530,7 +520,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv1f64.nxv1f64( @@ -552,7 +542,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v18 +; CHECK-NEXT: vfsgnj.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv2f64.nxv2f64( @@ -574,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsgnj.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv2f64.nxv2f64( @@ -596,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v20 +; CHECK-NEXT: vfsgnj.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv4f64.nxv4f64( @@ -617,10 +607,8 @@ define @intrinsic_vfsgnj_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv4f64.nxv4f64( @@ -641,10 +629,8 @@ define @intrinsic_vfsgnj_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfsgnj.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv8f64.nxv8f64( @@ -665,11 +651,10 @@ define @intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfsgnj.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv8f64.nxv8f64( @@ -692,7 +677,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv1f16.f16( @@ -715,7 +700,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv1f16.f16( @@ -738,7 +723,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv2f16.f16( @@ -761,7 +746,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv2f16.f16( @@ -784,7 +769,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv4f16.f16( @@ -807,7 +792,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv4f16.f16( @@ -830,7 +815,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv8f16.f16( @@ -853,7 +838,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv8f16.f16( @@ -876,7 +861,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv16f16.f16( @@ -899,7 +884,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv16f16.f16( @@ -922,7 +907,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv32f16.f16( @@ -943,11 +928,9 @@ define @intrinsic_vfsgnj_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv32f16.f16( @@ -970,7 +953,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv1f32.f32( @@ -993,7 +976,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv1f32.f32( @@ -1016,7 +999,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv2f32.f32( @@ -1039,7 +1022,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv2f32.f32( @@ -1062,7 +1045,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv4f32.f32( @@ -1085,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv4f32.f32( @@ -1108,7 +1091,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv8f32.f32( @@ -1131,7 +1114,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv8f32.f32( @@ -1154,7 +1137,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.nxv16f32.f32( @@ -1175,11 +1158,9 @@ define @intrinsic_vfsgnj_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnj.mask.nxv16f32.f32( @@ -1205,7 +1186,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1232,7 +1213,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1259,7 +1240,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1286,7 +1267,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1313,7 +1294,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1340,7 +1321,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsgnj.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1367,7 +1348,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfsgnj.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1390,13 +1371,11 @@ ; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfsgnj.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfsgnj.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv1f16( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv1f16( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv2f16( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv2f16( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv4f16( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv4f16( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv8f16( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv8f16( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv16f16( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv16f16( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv32f16_nxv32f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv32f16( %0, %1, @@ -226,10 +249,14 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv32f16( %0, %1, @@ -246,10 +273,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv1f32( %0, %1, @@ -266,10 +295,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv1f32( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv2f32( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv2f32( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv4f32( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv4f32( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv8f32( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv8f32( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv16f32_nxv16f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv16f32( %0, %1, @@ -426,10 +471,14 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv16f32( %0, %1, @@ -446,10 +495,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv1f64( %0, %1, @@ -466,10 +517,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv1f64( %0, %1, @@ -486,10 +539,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv2f64( %0, %1, @@ -506,10 +561,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv2f64( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv4f64( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv4f64( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vfsgnj_vv_nxv8f64_nxv8f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfsgnj.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv8f64( %0, %1, @@ -586,10 +649,14 @@ i64); define @intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsgnj.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfsgnj.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv8f64( %0, %1, @@ -606,10 +673,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv1f16.f16( %0, half %1, @@ -626,10 +696,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv1f16.f16( %0, %1, @@ -646,10 +719,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv2f16.f16( %0, half %1, @@ -666,10 +742,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv2f16.f16( %0, %1, @@ -686,10 +765,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv4f16.f16( %0, half %1, @@ -706,10 +788,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv4f16.f16( %0, %1, @@ -726,10 +811,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv8f16.f16( %0, half %1, @@ -746,10 +834,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv8f16.f16( %0, %1, @@ -766,10 +857,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv16f16.f16( %0, half %1, @@ -786,10 +880,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv16f16.f16( %0, %1, @@ -806,10 +903,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv32f16.f16( %0, half %1, @@ -826,10 +926,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv32f16.f16( %0, %1, @@ -846,10 +949,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv1f32.f32( %0, float %1, @@ -866,10 +972,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv1f32.f32( %0, %1, @@ -886,10 +995,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv2f32.f32( %0, float %1, @@ -906,10 +1018,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv2f32.f32( %0, %1, @@ -926,10 +1041,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv4f32.f32( %0, float %1, @@ -946,10 +1064,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv4f32.f32( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv8f32.f32( %0, float %1, @@ -986,10 +1110,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv8f32.f32( %0, %1, @@ -1006,10 +1133,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv16f32.f32( %0, float %1, @@ -1026,10 +1156,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv16f32.f32( %0, %1, @@ -1046,10 +1179,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv1f64.f64( %0, double %1, @@ -1066,10 +1202,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv1f64.f64( %0, %1, @@ -1086,10 +1225,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv2f64.f64( %0, double %1, @@ -1106,10 +1248,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv2f64.f64( %0, %1, @@ -1126,10 +1271,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv4f64.f64( %0, double %1, @@ -1146,10 +1294,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv4f64.f64( %0, %1, @@ -1166,10 +1317,13 @@ i64); define @intrinsic_vfsgnj_vf_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfsgnj.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnj.nxv8f64.f64( %0, double %1, @@ -1186,10 +1340,13 @@ i64); define @intrinsic_vfsgnj_mask_vf_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsgnj.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnj_mask_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfsgnj.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnj.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv1f16.nxv1f16( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv2f16.nxv2f16( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv2f16.nxv2f16( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv4f16.nxv4f16( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv4f16.nxv4f16( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v18 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv8f16.nxv8f16( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsgnjn.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv8f16.nxv8f16( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v20 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv16f16.nxv16f16( @@ -207,10 +207,8 @@ define @intrinsic_vfsgnjn_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv16f16.nxv16f16( @@ -231,10 +229,8 @@ define @intrinsic_vfsgnjn_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv32f16.nxv32f16( @@ -255,11 +251,10 @@ define @intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv32f16.nxv32f16( @@ -281,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv1f32.nxv1f32( @@ -303,7 +298,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv1f32.nxv1f32( @@ -325,7 +320,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv2f32.nxv2f32( @@ -347,7 +342,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv2f32.nxv2f32( @@ -369,7 +364,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v18 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv4f32.nxv4f32( @@ -391,7 +386,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsgnjn.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv4f32.nxv4f32( @@ -413,7 +408,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v20 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv8f32.nxv8f32( @@ -434,10 +429,8 @@ define @intrinsic_vfsgnjn_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv8f32.nxv8f32( @@ -458,10 +451,8 @@ define @intrinsic_vfsgnjn_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv16f32.nxv16f32( @@ -482,11 +473,10 @@ define @intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv16f32.nxv16f32( @@ -508,7 +498,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv1f64.nxv1f64( @@ -530,7 +520,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv1f64.nxv1f64( @@ -552,7 +542,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v18 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv2f64.nxv2f64( @@ -574,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsgnjn.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv2f64.nxv2f64( @@ -596,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v20 +; CHECK-NEXT: vfsgnjn.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv4f64.nxv4f64( @@ -617,10 +607,8 @@ define @intrinsic_vfsgnjn_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv4f64.nxv4f64( @@ -641,10 +629,8 @@ define @intrinsic_vfsgnjn_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfsgnjn.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv8f64.nxv8f64( @@ -665,11 +651,10 @@ define @intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfsgnjn.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv8f64.nxv8f64( @@ -692,7 +677,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv1f16.f16( @@ -715,7 +700,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv1f16.f16( @@ -738,7 +723,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv2f16.f16( @@ -761,7 +746,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv2f16.f16( @@ -784,7 +769,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv4f16.f16( @@ -807,7 +792,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv4f16.f16( @@ -830,7 +815,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv8f16.f16( @@ -853,7 +838,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv8f16.f16( @@ -876,7 +861,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv16f16.f16( @@ -899,7 +884,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv16f16.f16( @@ -922,7 +907,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv32f16.f16( @@ -943,11 +928,9 @@ define @intrinsic_vfsgnjn_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv32f16.f16( @@ -970,7 +953,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv1f32.f32( @@ -993,7 +976,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv1f32.f32( @@ -1016,7 +999,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv2f32.f32( @@ -1039,7 +1022,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv2f32.f32( @@ -1062,7 +1045,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv4f32.f32( @@ -1085,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv4f32.f32( @@ -1108,7 +1091,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv8f32.f32( @@ -1131,7 +1114,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv8f32.f32( @@ -1154,7 +1137,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.nxv16f32.f32( @@ -1175,11 +1158,9 @@ define @intrinsic_vfsgnjn_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjn.mask.nxv16f32.f32( @@ -1205,7 +1186,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1232,7 +1213,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1259,7 +1240,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1286,7 +1267,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1313,7 +1294,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1340,7 +1321,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsgnjn.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1367,7 +1348,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfsgnjn.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1390,13 +1371,11 @@ ; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfsgnjn.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfsgnjn.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv1f16( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv1f16( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv2f16( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv2f16( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv4f16( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv4f16( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv8f16( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv8f16( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv16f16( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv16f16( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv32f16_nxv32f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv32f16( %0, %1, @@ -226,10 +249,14 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv32f16( %0, %1, @@ -246,10 +273,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv1f32( %0, %1, @@ -266,10 +295,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv1f32( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv2f32( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv2f32( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv4f32( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv4f32( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv8f32( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv8f32( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv16f32_nxv16f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv16f32( %0, %1, @@ -426,10 +471,14 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv16f32( %0, %1, @@ -446,10 +495,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv1f64( %0, %1, @@ -466,10 +517,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv1f64( %0, %1, @@ -486,10 +539,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv2f64( %0, %1, @@ -506,10 +561,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv2f64( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv4f64( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv4f64( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vfsgnjn_vv_nxv8f64_nxv8f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfsgnjn.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv8f64( %0, %1, @@ -586,10 +649,14 @@ i64); define @intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfsgnjn.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv8f64( %0, %1, @@ -606,10 +673,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv1f16.f16( %0, half %1, @@ -626,10 +696,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv1f16.f16( %0, %1, @@ -646,10 +719,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv2f16.f16( %0, half %1, @@ -666,10 +742,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv2f16.f16( %0, %1, @@ -686,10 +765,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv4f16.f16( %0, half %1, @@ -706,10 +788,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv4f16.f16( %0, %1, @@ -726,10 +811,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv8f16.f16( %0, half %1, @@ -746,10 +834,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv8f16.f16( %0, %1, @@ -766,10 +857,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv16f16.f16( %0, half %1, @@ -786,10 +880,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv16f16.f16( %0, %1, @@ -806,10 +903,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv32f16.f16( %0, half %1, @@ -826,10 +926,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv32f16.f16( %0, %1, @@ -846,10 +949,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv1f32.f32( %0, float %1, @@ -866,10 +972,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv1f32.f32( %0, %1, @@ -886,10 +995,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv2f32.f32( %0, float %1, @@ -906,10 +1018,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv2f32.f32( %0, %1, @@ -926,10 +1041,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv4f32.f32( %0, float %1, @@ -946,10 +1064,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv4f32.f32( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv8f32.f32( %0, float %1, @@ -986,10 +1110,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv8f32.f32( %0, %1, @@ -1006,10 +1133,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv16f32.f32( %0, float %1, @@ -1026,10 +1156,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv16f32.f32( %0, %1, @@ -1046,10 +1179,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv1f64.f64( %0, double %1, @@ -1066,10 +1202,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv1f64.f64( %0, %1, @@ -1086,10 +1225,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv2f64.f64( %0, double %1, @@ -1106,10 +1248,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv2f64.f64( %0, %1, @@ -1126,10 +1271,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv4f64.f64( %0, double %1, @@ -1146,10 +1294,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv4f64.f64( %0, %1, @@ -1166,10 +1317,13 @@ i64); define @intrinsic_vfsgnjn_vf_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfsgnjn.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjn.nxv8f64.f64( %0, double %1, @@ -1186,10 +1340,13 @@ i64); define @intrinsic_vfsgnjn_mask_vf_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsgnjn.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjn_mask_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfsgnjn.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjn.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv1f16.nxv1f16( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv2f16.nxv2f16( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv2f16.nxv2f16( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv4f16.nxv4f16( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv4f16.nxv4f16( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v18 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv8f16.nxv8f16( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsgnjx.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv8f16.nxv8f16( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v20 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv16f16.nxv16f16( @@ -207,10 +207,8 @@ define @intrinsic_vfsgnjx_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv16f16.nxv16f16( @@ -231,10 +229,8 @@ define @intrinsic_vfsgnjx_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv32f16.nxv32f16( @@ -255,11 +251,10 @@ define @intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv32f16.nxv32f16( @@ -281,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv1f32.nxv1f32( @@ -303,7 +298,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv1f32.nxv1f32( @@ -325,7 +320,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv2f32.nxv2f32( @@ -347,7 +342,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv2f32.nxv2f32( @@ -369,7 +364,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v18 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv4f32.nxv4f32( @@ -391,7 +386,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsgnjx.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv4f32.nxv4f32( @@ -413,7 +408,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v20 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv8f32.nxv8f32( @@ -434,10 +429,8 @@ define @intrinsic_vfsgnjx_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv8f32.nxv8f32( @@ -458,10 +451,8 @@ define @intrinsic_vfsgnjx_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv16f32.nxv16f32( @@ -482,11 +473,10 @@ define @intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv16f32.nxv16f32( @@ -508,7 +498,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v17 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv1f64.nxv1f64( @@ -530,7 +520,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv1f64.nxv1f64( @@ -552,7 +542,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v18 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv2f64.nxv2f64( @@ -574,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsgnjx.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv2f64.nxv2f64( @@ -596,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v20 +; CHECK-NEXT: vfsgnjx.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv4f64.nxv4f64( @@ -617,10 +607,8 @@ define @intrinsic_vfsgnjx_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv4f64.nxv4f64( @@ -641,10 +629,8 @@ define @intrinsic_vfsgnjx_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfsgnjx.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv8f64.nxv8f64( @@ -665,11 +651,10 @@ define @intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfsgnjx.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv8f64.nxv8f64( @@ -692,7 +677,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv1f16.f16( @@ -715,7 +700,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv1f16.f16( @@ -738,7 +723,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv2f16.f16( @@ -761,7 +746,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv2f16.f16( @@ -784,7 +769,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv4f16.f16( @@ -807,7 +792,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv4f16.f16( @@ -830,7 +815,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv8f16.f16( @@ -853,7 +838,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv8f16.f16( @@ -876,7 +861,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv16f16.f16( @@ -899,7 +884,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv16f16.f16( @@ -922,7 +907,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv32f16.f16( @@ -943,11 +928,9 @@ define @intrinsic_vfsgnjx_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv32f16.f16( @@ -970,7 +953,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv1f32.f32( @@ -993,7 +976,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv1f32.f32( @@ -1016,7 +999,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv2f32.f32( @@ -1039,7 +1022,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv2f32.f32( @@ -1062,7 +1045,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv4f32.f32( @@ -1085,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv4f32.f32( @@ -1108,7 +1091,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv8f32.f32( @@ -1131,7 +1114,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv8f32.f32( @@ -1154,7 +1137,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.nxv16f32.f32( @@ -1175,11 +1158,9 @@ define @intrinsic_vfsgnjx_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsgnjx.mask.nxv16f32.f32( @@ -1205,7 +1186,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1232,7 +1213,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1259,7 +1240,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1286,7 +1267,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1313,7 +1294,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1340,7 +1321,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsgnjx.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1367,7 +1348,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfsgnjx.vf v16, v16, ft0 +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1390,13 +1371,11 @@ ; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfsgnjx.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfsgnjx.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv1f16( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv1f16( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv2f16( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv2f16( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv4f16( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv4f16( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv8f16( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv8f16( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv16f16( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv16f16( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv32f16_nxv32f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv32f16( %0, %1, @@ -226,10 +249,14 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv32f16( %0, %1, @@ -246,10 +273,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv1f32( %0, %1, @@ -266,10 +295,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv1f32( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv2f32( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv2f32( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv4f32( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv4f32( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv8f32( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv8f32( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv16f32_nxv16f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv16f32( %0, %1, @@ -426,10 +471,14 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv16f32( %0, %1, @@ -446,10 +495,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv1f64( %0, %1, @@ -466,10 +517,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv1f64( %0, %1, @@ -486,10 +539,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv2f64( %0, %1, @@ -506,10 +561,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv2f64( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv4f64( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv4f64( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vfsgnjx_vv_nxv8f64_nxv8f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfsgnjx.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv8f64( %0, %1, @@ -586,10 +649,14 @@ i64); define @intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vv_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfsgnjx.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv8f64( %0, %1, @@ -606,10 +673,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv1f16.f16( %0, half %1, @@ -626,10 +696,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv1f16.f16( %0, %1, @@ -646,10 +719,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv2f16.f16( %0, half %1, @@ -666,10 +742,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv2f16.f16( %0, %1, @@ -686,10 +765,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv4f16.f16( %0, half %1, @@ -706,10 +788,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv4f16.f16( %0, %1, @@ -726,10 +811,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv8f16.f16( %0, half %1, @@ -746,10 +834,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv8f16.f16( %0, %1, @@ -766,10 +857,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv16f16.f16( %0, half %1, @@ -786,10 +880,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv16f16.f16( %0, %1, @@ -806,10 +903,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv32f16.f16( %0, half %1, @@ -826,10 +926,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv32f16.f16( %0, %1, @@ -846,10 +949,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv1f32.f32( %0, float %1, @@ -866,10 +972,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv1f32.f32( %0, %1, @@ -886,10 +995,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv2f32.f32( %0, float %1, @@ -906,10 +1018,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv2f32.f32( %0, %1, @@ -926,10 +1041,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv4f32.f32( %0, float %1, @@ -946,10 +1064,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv4f32.f32( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv8f32.f32( %0, float %1, @@ -986,10 +1110,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv8f32.f32( %0, %1, @@ -1006,10 +1133,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv16f32.f32( %0, float %1, @@ -1026,10 +1156,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv16f32.f32( %0, %1, @@ -1046,10 +1179,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv1f64.f64( %0, double %1, @@ -1066,10 +1202,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv1f64.f64( %0, %1, @@ -1086,10 +1225,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv2f64.f64( %0, double %1, @@ -1106,10 +1248,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv2f64.f64( %0, %1, @@ -1126,10 +1271,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv4f64.f64( %0, double %1, @@ -1146,10 +1294,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv4f64.f64( %0, %1, @@ -1166,10 +1317,13 @@ i64); define @intrinsic_vfsgnjx_vf_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfsgnjx.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsgnjx.nxv8f64.f64( %0, double %1, @@ -1186,10 +1340,13 @@ i64); define @intrinsic_vfsgnjx_mask_vf_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsgnjx.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsgnjx_mask_vf_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfsgnjx.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsgnjx.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll @@ -11,7 +11,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv1f16.f16( @@ -34,7 +34,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv1f16.f16( @@ -57,7 +57,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv2f16.f16( @@ -80,7 +80,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv2f16.f16( @@ -103,7 +103,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv4f16.f16( @@ -126,7 +126,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv4f16.f16( @@ -149,7 +149,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv8f16.f16( @@ -172,7 +172,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv8f16.f16( @@ -195,7 +195,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv16f16.f16( @@ -218,7 +218,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv16f16.f16( @@ -241,7 +241,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv32f16.f16( @@ -262,11 +262,9 @@ define @intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfslide1down.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv32f16.f16( @@ -289,7 +287,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv1f32.f32( @@ -312,7 +310,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv1f32.f32( @@ -335,7 +333,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv2f32.f32( @@ -358,7 +356,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv2f32.f32( @@ -381,7 +379,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv4f32.f32( @@ -404,7 +402,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv4f32.f32( @@ -427,7 +425,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv8f32.f32( @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv8f32.f32( @@ -473,7 +471,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv16f32.f32( @@ -494,11 +492,9 @@ define @intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfslide1down.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv16f32.f32( @@ -524,7 +520,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -551,7 +547,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -578,7 +574,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -605,7 +601,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -632,7 +628,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -659,7 +655,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -686,7 +682,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -709,13 +705,11 @@ ; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfslide1down.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll @@ -11,7 +11,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv1f16.f16( @@ -34,7 +34,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv1f16.f16( @@ -57,7 +57,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv2f16.f16( @@ -80,7 +80,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv2f16.f16( @@ -103,7 +103,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv4f16.f16( @@ -126,7 +126,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv4f16.f16( @@ -149,7 +149,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv8f16.f16( @@ -172,7 +172,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv8f16.f16( @@ -195,7 +195,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv16f16.f16( @@ -218,7 +218,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv16f16.f16( @@ -241,7 +241,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv32f16.f16( @@ -262,11 +262,9 @@ define @intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfslide1down.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv32f16.f16( @@ -289,7 +287,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv1f32.f32( @@ -312,7 +310,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv1f32.f32( @@ -335,7 +333,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv2f32.f32( @@ -358,7 +356,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv2f32.f32( @@ -381,7 +379,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv4f32.f32( @@ -404,7 +402,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv4f32.f32( @@ -427,7 +425,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv8f32.f32( @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv8f32.f32( @@ -473,7 +471,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv16f32.f32( @@ -494,11 +492,9 @@ define @intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfslide1down.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv16f32.f32( @@ -521,7 +517,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv1f64.f64( @@ -544,7 +540,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv1f64.f64( @@ -567,7 +563,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv2f64.f64( @@ -590,7 +586,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv2f64.f64( @@ -613,7 +609,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv4f64.f64( @@ -636,7 +632,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1down.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv4f64.f64( @@ -659,7 +655,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfslide1down.vf v16, v16, ft0 +; CHECK-NEXT: vfslide1down.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.nxv8f64.f64( @@ -680,11 +676,9 @@ define @intrinsic_vfslide1down_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: fmv.d.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfslide1down.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfslide1down.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1down.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll @@ -11,8 +11,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv1f16.f16( @@ -35,7 +35,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv1f16.f16( @@ -58,8 +58,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv2f16.f16( @@ -82,7 +82,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv2f16.f16( @@ -105,8 +105,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv4f16.f16( @@ -129,7 +129,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv4f16.f16( @@ -152,8 +152,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfslide1up.vf v26, v16, ft0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vfslide1up.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv8f16.f16( @@ -176,7 +176,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv8f16.f16( @@ -199,8 +199,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfslide1up.vf v28, v16, ft0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vfslide1up.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv16f16.f16( @@ -223,7 +223,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv16f16.f16( @@ -246,8 +246,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfslide1up.vf v8, v16, ft0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vfslide1up.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv32f16.f16( @@ -268,11 +268,9 @@ define @intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfslide1up.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv32f16.f16( @@ -295,8 +293,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv1f32.f32( @@ -319,7 +317,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv1f32.f32( @@ -342,8 +340,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv2f32.f32( @@ -366,7 +364,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv2f32.f32( @@ -389,8 +387,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfslide1up.vf v26, v16, ft0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vfslide1up.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv4f32.f32( @@ -413,7 +411,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv4f32.f32( @@ -436,8 +434,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfslide1up.vf v28, v16, ft0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vfslide1up.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv8f32.f32( @@ -460,7 +458,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv8f32.f32( @@ -483,8 +481,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfslide1up.vf v8, v16, ft0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vfslide1up.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv16f32.f32( @@ -505,11 +503,9 @@ define @intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfslide1up.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv16f32.f32( @@ -535,8 +531,8 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -563,7 +559,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -590,8 +586,8 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfslide1up.vf v26, v16, ft0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vfslide1up.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -618,7 +614,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -645,8 +641,8 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfslide1up.vf v28, v16, ft0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vfslide1up.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -673,7 +669,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -700,8 +696,8 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfslide1up.vf v8, v16, ft0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vfslide1up.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -724,13 +720,11 @@ ; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfslide1up.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll @@ -11,8 +11,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv1f16.f16( @@ -35,7 +35,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv1f16.f16( @@ -58,8 +58,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv2f16.f16( @@ -82,7 +82,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv2f16.f16( @@ -105,8 +105,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv4f16.f16( @@ -129,7 +129,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv4f16.f16( @@ -152,8 +152,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfslide1up.vf v26, v16, ft0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vfslide1up.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv8f16.f16( @@ -176,7 +176,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv8f16.f16( @@ -199,8 +199,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfslide1up.vf v28, v16, ft0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vfslide1up.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv16f16.f16( @@ -223,7 +223,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv16f16.f16( @@ -246,8 +246,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfslide1up.vf v8, v16, ft0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vfslide1up.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv32f16.f16( @@ -268,11 +268,9 @@ define @intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfslide1up.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv32f16.f16( @@ -295,8 +293,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv1f32.f32( @@ -319,7 +317,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv1f32.f32( @@ -342,8 +340,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv2f32.f32( @@ -366,7 +364,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv2f32.f32( @@ -389,8 +387,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfslide1up.vf v26, v16, ft0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vfslide1up.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv4f32.f32( @@ -413,7 +411,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv4f32.f32( @@ -436,8 +434,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfslide1up.vf v28, v16, ft0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vfslide1up.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv8f32.f32( @@ -460,7 +458,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv8f32.f32( @@ -483,8 +481,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfslide1up.vf v8, v16, ft0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vfslide1up.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv16f32.f32( @@ -505,11 +503,9 @@ define @intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfslide1up.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv16f32.f32( @@ -532,8 +528,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu -; CHECK-NEXT: vfslide1up.vf v25, v16, ft0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vfslide1up.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv1f64.f64( @@ -556,7 +552,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv1f64.f64( @@ -579,8 +575,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu -; CHECK-NEXT: vfslide1up.vf v26, v16, ft0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vfslide1up.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv2f64.f64( @@ -603,7 +599,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv2f64.f64( @@ -626,8 +622,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu -; CHECK-NEXT: vfslide1up.vf v28, v16, ft0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vfslide1up.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv4f64.f64( @@ -650,7 +646,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfslide1up.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv4f64.f64( @@ -673,8 +669,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.d.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfslide1up.vf v8, v16, ft0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vfslide1up.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.nxv8f64.f64( @@ -695,11 +691,9 @@ define @intrinsic_vfslide1up_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: fmv.d.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfslide1up.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfslide1up.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfslide1up.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv1f16( @@ -29,7 +29,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv1f16( @@ -49,7 +49,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv2f16( @@ -69,7 +69,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv2f16( @@ -89,7 +89,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv4f16( @@ -109,7 +109,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv4f16( @@ -129,7 +129,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv8f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v18, v0.t +; CHECK-NEXT: vfsqrt.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv8f16( @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv16f16( @@ -189,7 +189,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v20, v0.t +; CHECK-NEXT: vfsqrt.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv16f16( @@ -209,7 +209,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv32f16( @@ -227,7 +227,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv1f32( @@ -247,7 +247,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv1f32( @@ -267,7 +267,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv2f32( @@ -287,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv2f32( @@ -307,7 +307,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv4f32( @@ -327,7 +327,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v18, v0.t +; CHECK-NEXT: vfsqrt.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv4f32( @@ -347,7 +347,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv8f32( @@ -367,7 +367,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v20, v0.t +; CHECK-NEXT: vfsqrt.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv8f32( @@ -387,7 +387,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv16f32( @@ -405,7 +405,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv1f64( @@ -425,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv1f64( @@ -445,7 +445,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv2f64( @@ -465,7 +465,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v18, v0.t +; CHECK-NEXT: vfsqrt.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv2f64( @@ -485,7 +485,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv4f64( @@ -505,7 +505,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v20, v0.t +; CHECK-NEXT: vfsqrt.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.mask.nxv4f64( @@ -525,7 +525,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsqrt.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -31,7 +31,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -55,7 +55,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -77,7 +77,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -101,7 +101,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -123,7 +123,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -147,7 +147,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v18, v0.t +; CHECK-NEXT: vfsqrt.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -193,7 +193,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -215,7 +215,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v20, v0.t +; CHECK-NEXT: vfsqrt.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -239,7 +239,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -260,10 +260,8 @@ define @intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16( ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v8, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vfsqrt.v v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -287,7 +285,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -309,7 +307,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -333,7 +331,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -355,7 +353,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -379,7 +377,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -401,7 +399,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v18, v0.t +; CHECK-NEXT: vfsqrt.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -425,7 +423,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -447,7 +445,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v20, v0.t +; CHECK-NEXT: vfsqrt.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -471,7 +469,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -492,10 +490,8 @@ define @intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32( ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v8, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vfsqrt.v v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -519,7 +515,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -541,7 +537,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v17, v0.t +; CHECK-NEXT: vfsqrt.v v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -565,7 +561,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -587,7 +583,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v18, v0.t +; CHECK-NEXT: vfsqrt.v v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -611,7 +607,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -633,7 +629,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v20, v0.t +; CHECK-NEXT: vfsqrt.v v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, @@ -657,7 +653,7 @@ ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vfsqrt.v v16, v16 +; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: jalr zero, 0(ra) %0, i64 %1) nounwind { @@ -678,10 +674,8 @@ define @intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64( ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vfsqrt.v v16, v8, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vfsqrt.v v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv1f16.nxv1f16( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv1f16.nxv1f16( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv2f16.nxv2f16( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv2f16.nxv2f16( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv4f16.nxv4f16( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv4f16.nxv4f16( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v18 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv8f16.nxv8f16( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv8f16.nxv8f16( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v20 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv16f16.nxv16f16( @@ -207,10 +207,8 @@ define @intrinsic_vfsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv16f16.nxv16f16( @@ -231,10 +229,8 @@ define @intrinsic_vfsub_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsub_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv32f16.nxv32f16( @@ -255,11 +251,10 @@ define @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfsub.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16( @@ -281,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv1f32.nxv1f32( @@ -303,7 +298,7 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv1f32.nxv1f32( @@ -325,7 +320,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv2f32.nxv2f32( @@ -347,7 +342,7 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv2f32.nxv2f32( @@ -369,7 +364,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v18 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv4f32.nxv4f32( @@ -391,7 +386,7 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv4f32.nxv4f32( @@ -413,7 +408,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v20 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv8f32.nxv8f32( @@ -434,10 +429,8 @@ define @intrinsic_vfsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv8f32.nxv8f32( @@ -458,10 +451,8 @@ define @intrinsic_vfsub_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsub_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv16f32.nxv16f32( @@ -482,11 +473,10 @@ define @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfsub.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32( @@ -508,7 +498,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv1f64.nxv1f64( @@ -530,7 +520,7 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vfsub.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv1f64.nxv1f64( @@ -552,7 +542,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v18 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv2f64.nxv2f64( @@ -574,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vfsub.vv v16, v18, v20, v0.t +; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv2f64.nxv2f64( @@ -596,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v20 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv4f64.nxv4f64( @@ -617,10 +607,8 @@ define @intrinsic_vfsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vfsub.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv4f64.nxv4f64( @@ -641,10 +629,8 @@ define @intrinsic_vfsub_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv8f64.nxv8f64( @@ -665,11 +651,10 @@ define @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vfsub.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64( @@ -692,7 +677,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv1f16.f16( @@ -715,7 +700,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv1f16.f16( @@ -738,7 +723,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv2f16.f16( @@ -761,7 +746,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv2f16.f16( @@ -784,7 +769,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv4f16.f16( @@ -807,7 +792,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv4f16.f16( @@ -830,7 +815,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv8f16.f16( @@ -853,7 +838,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfsub.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv8f16.f16( @@ -876,7 +861,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv16f16.f16( @@ -899,7 +884,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vfsub.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv16f16.f16( @@ -922,7 +907,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv32f16.f16( @@ -943,11 +928,9 @@ define @intrinsic_vfsub_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: fmv.h.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vfsub.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsub.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv32f16.f16( @@ -970,7 +953,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv1f32.f32( @@ -993,7 +976,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv1f32.f32( @@ -1016,7 +999,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv2f32.f32( @@ -1039,7 +1022,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv2f32.f32( @@ -1062,7 +1045,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv4f32.f32( @@ -1085,7 +1068,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfsub.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v10, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv4f32.f32( @@ -1108,7 +1091,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv8f32.f32( @@ -1131,7 +1114,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vfsub.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v12, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv8f32.f32( @@ -1154,7 +1137,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.nxv16f32.f32( @@ -1175,11 +1158,9 @@ define @intrinsic_vfsub_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: fmv.w.x ft0, a1 -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vfsub.vf v16, v8, ft0, v0.t +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsub.vf v8, v16, ft0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfsub.mask.nxv16f32.f32( @@ -1205,7 +1186,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1232,7 +1213,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m1,tu,mu -; CHECK-NEXT: vfsub.vf v16, v17, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1259,7 +1240,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1286,7 +1267,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m2,tu,mu -; CHECK-NEXT: vfsub.vf v16, v18, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v10, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1313,7 +1294,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1340,7 +1321,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m4,tu,mu -; CHECK-NEXT: vfsub.vf v16, v20, ft0, v0.t +; CHECK-NEXT: vfsub.vf v8, v12, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1367,7 +1348,7 @@ ; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) ; CHECK-NEXT: vsetvli a0, a2, e64,m8,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, ft0 +; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -1390,13 +1371,11 @@ ; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: sw a1, 8(sp) -; CHECK-NEXT: sw a2, 12(sp) +; CHECK-NEXT: sw a0, 8(sp) +; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: fld ft0, 8(sp) -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a3, e64,m8,tu,mu -; CHECK-NEXT: vfsub.vf v16, v8, ft0, v0.t +; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu +; CHECK-NEXT: vfsub.vf v8, v16, ft0, v0.t ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s @@ -7,10 +8,12 @@ i64); define @intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv1f16.nxv1f16( %0, %1, @@ -27,10 +30,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f16_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv1f16.nxv1f16( %0, %1, @@ -47,10 +52,12 @@ i64); define @intrinsic_vfsub_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv2f16.nxv2f16( %0, %1, @@ -67,10 +74,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f16_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv2f16.nxv2f16( %0, %1, @@ -87,10 +96,12 @@ i64); define @intrinsic_vfsub_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv4f16.nxv4f16( %0, %1, @@ -107,10 +118,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f16_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv4f16.nxv4f16( %0, %1, @@ -127,10 +140,12 @@ i64); define @intrinsic_vfsub_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv8f16.nxv8f16( %0, %1, @@ -147,10 +162,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f16_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv8f16.nxv8f16( %0, %1, @@ -167,10 +184,12 @@ i64); define @intrinsic_vfsub_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv16f16.nxv16f16( %0, %1, @@ -187,10 +206,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f16_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv16f16.nxv16f16( %0, %1, @@ -207,10 +228,12 @@ i64); define @intrinsic_vfsub_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv32f16.nxv32f16( %0, %1, @@ -227,10 +250,14 @@ i64); define @intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32f16_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv32f16.nxv32f16( %0, %1, @@ -247,10 +274,12 @@ i64); define @intrinsic_vfsub_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv1f32.nxv1f32( %0, %1, @@ -267,10 +296,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f32_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv1f32.nxv1f32( %0, %1, @@ -287,10 +318,12 @@ i64); define @intrinsic_vfsub_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv2f32.nxv2f32( %0, %1, @@ -307,10 +340,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f32_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv2f32.nxv2f32( %0, %1, @@ -327,10 +362,12 @@ i64); define @intrinsic_vfsub_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv4f32.nxv4f32( %0, %1, @@ -347,10 +384,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f32_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv4f32.nxv4f32( %0, %1, @@ -367,10 +406,12 @@ i64); define @intrinsic_vfsub_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv8f32.nxv8f32( %0, %1, @@ -387,10 +428,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f32_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv8f32.nxv8f32( %0, %1, @@ -407,10 +450,12 @@ i64); define @intrinsic_vfsub_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv16f32.nxv16f32( %0, %1, @@ -427,10 +472,14 @@ i64); define @intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16f32_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv16f32.nxv16f32( %0, %1, @@ -447,10 +496,12 @@ i64); define @intrinsic_vfsub_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv1f64.nxv1f64( %0, %1, @@ -467,10 +518,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1f64_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv1f64.nxv1f64( %0, %1, @@ -487,10 +540,12 @@ i64); define @intrinsic_vfsub_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv2f64.nxv2f64( %0, %1, @@ -507,10 +562,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2f64_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv2f64.nxv2f64( %0, %1, @@ -527,10 +584,12 @@ i64); define @intrinsic_vfsub_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv4f64.nxv4f64( %0, %1, @@ -547,10 +606,12 @@ i64); define @intrinsic_vfsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4f64_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv4f64.nxv4f64( %0, %1, @@ -567,10 +628,12 @@ i64); define @intrinsic_vfsub_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vv_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfsub.nxv8f64.nxv8f64( %0, %1, @@ -587,10 +650,14 @@ i64); define @intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8f64_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv8f64.nxv8f64( %0, %1, @@ -607,10 +674,13 @@ i64); define @intrinsic_vfsub_vf_nxv1f16_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv1f16.f16( %0, half %1, @@ -627,10 +697,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1f16_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1f16_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv1f16.f16( %0, %1, @@ -647,10 +720,13 @@ i64); define @intrinsic_vfsub_vf_nxv2f16_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv2f16.f16( %0, half %1, @@ -667,10 +743,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2f16_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2f16_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv2f16.f16( %0, %1, @@ -687,10 +766,13 @@ i64); define @intrinsic_vfsub_vf_nxv4f16_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv4f16.f16( %0, half %1, @@ -707,10 +789,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4f16_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4f16_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv4f16.f16( %0, %1, @@ -727,10 +812,13 @@ i64); define @intrinsic_vfsub_vf_nxv8f16_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv8f16.f16( %0, half %1, @@ -747,10 +835,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f16_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f16_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv8f16.f16( %0, %1, @@ -767,10 +858,13 @@ i64); define @intrinsic_vfsub_vf_nxv16f16_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv16f16.f16( %0, half %1, @@ -787,10 +881,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv16f16_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv16f16_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv16f16.f16( %0, %1, @@ -807,10 +904,13 @@ i64); define @intrinsic_vfsub_vf_nxv32f16_nxv32f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv32f16.f16( %0, half %1, @@ -827,10 +927,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv32f16_nxv32f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vfsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv32f16_nxv32f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv32f16.f16( %0, %1, @@ -847,10 +950,13 @@ i64); define @intrinsic_vfsub_vf_nxv1f32_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv1f32.f32( %0, float %1, @@ -867,10 +973,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1f32_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1f32_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv1f32.f32( %0, %1, @@ -887,10 +996,13 @@ i64); define @intrinsic_vfsub_vf_nxv2f32_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv2f32.f32( %0, float %1, @@ -907,10 +1019,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2f32_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2f32_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv2f32.f32( %0, %1, @@ -927,10 +1042,13 @@ i64); define @intrinsic_vfsub_vf_nxv4f32_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv4f32.f32( %0, float %1, @@ -947,10 +1065,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4f32_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4f32_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv4f32.f32( %0, %1, @@ -967,10 +1088,13 @@ i64); define @intrinsic_vfsub_vf_nxv8f32_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv8f32.f32( %0, float %1, @@ -987,10 +1111,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f32_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f32_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv8f32.f32( %0, %1, @@ -1007,10 +1134,13 @@ i64); define @intrinsic_vfsub_vf_nxv16f32_nxv16f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv16f32.f32( %0, float %1, @@ -1027,10 +1157,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv16f32_nxv16f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vfsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv16f32_nxv16f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv16f32.f32( %0, %1, @@ -1047,10 +1180,13 @@ i64); define @intrinsic_vfsub_vf_nxv1f64_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv1f64.f64( %0, double %1, @@ -1067,10 +1203,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1f64_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vfsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1f64_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv1f64.f64( %0, %1, @@ -1087,10 +1226,13 @@ i64); define @intrinsic_vfsub_vf_nxv2f64_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv2f64.f64( %0, double %1, @@ -1107,10 +1249,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2f64_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vfsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2f64_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv2f64.f64( %0, %1, @@ -1127,10 +1272,13 @@ i64); define @intrinsic_vfsub_vf_nxv4f64_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv4f64.f64( %0, double %1, @@ -1147,10 +1295,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4f64_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vfsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4f64_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv4f64.f64( %0, %1, @@ -1167,10 +1318,13 @@ i64); define @intrinsic_vfsub_vf_nxv8f64_nxv8f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfsub_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu +; CHECK-NEXT: vfsub.vf v8, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfsub.nxv8f64.f64( %0, double %1, @@ -1187,10 +1341,13 @@ i64); define @intrinsic_vfsub_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f64_nxv8f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vfsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8f64_nxv8f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vfsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfsub.mask.nxv8f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfsub_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfsub_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfsub_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfsub_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v18 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, fa0 +; CHECK-NEXT: vfrsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK-LABEL: vfsub_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v20 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,9 +133,8 @@ define @vfsub_vv_nxv32f16( %va, %vb) { ; CHECK-LABEL: vfsub_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vfsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -146,7 +145,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -158,7 +157,7 @@ ; CHECK-LABEL: vfsub_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -168,7 +167,7 @@ ; CHECK-LABEL: vfsub_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +179,7 @@ ; CHECK-LABEL: vfsub_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -190,7 +189,7 @@ ; CHECK-LABEL: vfsub_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -202,7 +201,7 @@ ; CHECK-LABEL: vfsub_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v18 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -212,7 +211,7 @@ ; CHECK-LABEL: vfsub_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +223,7 @@ ; CHECK-LABEL: vfsub_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v20 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -234,7 +233,7 @@ ; CHECK-LABEL: vfsub_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -246,7 +245,7 @@ ; CHECK-LABEL: vfsub_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, fa0 +; CHECK-NEXT: vfrsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,9 +256,8 @@ define @vfsub_vv_nxv16f32( %va, %vb) { ; CHECK-LABEL: vfsub_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vfsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -269,7 +267,7 @@ ; CHECK-LABEL: vfsub_vf_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +279,7 @@ ; CHECK-LABEL: vfsub_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -291,7 +289,7 @@ ; CHECK-LABEL: vfsub_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -303,7 +301,7 @@ ; CHECK-LABEL: vfsub_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v18 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -313,7 +311,7 @@ ; CHECK-LABEL: vfsub_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -325,7 +323,7 @@ ; CHECK-LABEL: vfsub_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v20 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -335,7 +333,7 @@ ; CHECK-LABEL: vfsub_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,9 +344,8 @@ define @vfsub_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: vfsub_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vfsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -358,7 +355,7 @@ ; CHECK-LABEL: vfsub_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -370,7 +367,7 @@ ; CHECK-LABEL: vfsub_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, fa0 +; CHECK-NEXT: vfrsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfsub_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfsub_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfsub_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfsub_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v18 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -99,7 +99,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, fa0 +; CHECK-NEXT: vfrsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK-LABEL: vfsub_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v20 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -122,7 +122,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,9 +133,8 @@ define @vfsub_vv_nxv32f16( %va, %vb) { ; CHECK-LABEL: vfsub_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vfsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -146,7 +145,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -158,7 +157,7 @@ ; CHECK-LABEL: vfsub_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -168,7 +167,7 @@ ; CHECK-LABEL: vfsub_vf_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +179,7 @@ ; CHECK-LABEL: vfsub_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -190,7 +189,7 @@ ; CHECK-LABEL: vfsub_vf_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -202,7 +201,7 @@ ; CHECK-LABEL: vfsub_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v18 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -212,7 +211,7 @@ ; CHECK-LABEL: vfsub_vf_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -224,7 +223,7 @@ ; CHECK-LABEL: vfsub_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v20 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -234,7 +233,7 @@ ; CHECK-LABEL: vfsub_vf_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -246,7 +245,7 @@ ; CHECK-LABEL: vfsub_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, fa0 +; CHECK-NEXT: vfrsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,9 +256,8 @@ define @vfsub_vv_nxv16f32( %va, %vb) { ; CHECK-LABEL: vfsub_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vfsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -269,7 +267,7 @@ ; CHECK-LABEL: vfsub_vf_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +279,7 @@ ; CHECK-LABEL: vfsub_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v17 +; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -291,7 +289,7 @@ ; CHECK-LABEL: vfsub_vf_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -303,7 +301,7 @@ ; CHECK-LABEL: vfsub_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v18 +; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -313,7 +311,7 @@ ; CHECK-LABEL: vfsub_vf_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -325,7 +323,7 @@ ; CHECK-LABEL: vfsub_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfsub.vv v16, v16, v20 +; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -335,7 +333,7 @@ ; CHECK-LABEL: vfsub_vf_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,9 +344,8 @@ define @vfsub_vv_nxv8f64( %va, %vb) { ; CHECK-LABEL: vfsub_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vfsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = fsub %va, %vb ret %vc @@ -358,7 +355,7 @@ ; CHECK-LABEL: vfsub_vf_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfsub.vf v16, v16, fa0 +; CHECK-NEXT: vfsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -370,7 +367,7 @@ ; CHECK-LABEL: vfsub_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfrsub.vf v16, v16, fa0 +; CHECK-NEXT: vfrsub.vf v8, v8, fa0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( @@ -6,10 +7,13 @@ i32); define @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -366,10 +412,14 @@ i32); define @intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwadd.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16( %0, half %1, @@ -386,10 +436,13 @@ i32); define @intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16( %0, %1, @@ -406,10 +459,14 @@ i32); define @intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwadd.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16( %0, half %1, @@ -426,10 +483,13 @@ i32); define @intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16( %0, %1, @@ -446,10 +506,14 @@ i32); define @intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwadd.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16( %0, half %1, @@ -466,10 +530,13 @@ i32); define @intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16( %0, %1, @@ -486,10 +553,14 @@ i32); define @intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwadd.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16( %0, half %1, @@ -506,10 +577,13 @@ i32); define @intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16( %0, %1, @@ -526,10 +600,14 @@ i32); define @intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwadd.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv16f32.nxv16f16.f16( %0, half %1, @@ -546,10 +624,13 @@ i32); define @intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16( %0, %1, @@ -566,10 +647,14 @@ i32); define @intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwadd.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32( %0, float %1, @@ -586,10 +671,13 @@ i32); define @intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32( %0, %1, @@ -606,10 +694,14 @@ i32); define @intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwadd.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32( %0, float %1, @@ -626,10 +718,13 @@ i32); define @intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32( %0, %1, @@ -646,10 +741,14 @@ i32); define @intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwadd.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32( %0, float %1, @@ -666,10 +765,13 @@ i32); define @intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32( %0, %1, @@ -686,10 +788,14 @@ i32); define @intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwadd.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv8f64.nxv8f32.f32( %0, float %1, @@ -706,10 +812,13 @@ i32); define @intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( @@ -6,10 +7,13 @@ i64); define @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -366,10 +412,14 @@ i64); define @intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwadd.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16( %0, half %1, @@ -386,10 +436,13 @@ i64); define @intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16( %0, %1, @@ -406,10 +459,14 @@ i64); define @intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwadd.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16( %0, half %1, @@ -426,10 +483,13 @@ i64); define @intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16( %0, %1, @@ -446,10 +506,14 @@ i64); define @intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwadd.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16( %0, half %1, @@ -466,10 +530,13 @@ i64); define @intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16( %0, %1, @@ -486,10 +553,14 @@ i64); define @intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwadd.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16( %0, half %1, @@ -506,10 +577,13 @@ i64); define @intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16( %0, %1, @@ -526,10 +600,14 @@ i64); define @intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwadd.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv16f32.nxv16f16.f16( %0, half %1, @@ -546,10 +624,13 @@ i64); define @intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16( %0, %1, @@ -566,10 +647,14 @@ i64); define @intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwadd.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32( %0, float %1, @@ -586,10 +671,13 @@ i64); define @intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32( %0, %1, @@ -606,10 +694,14 @@ i64); define @intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwadd.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32( %0, float %1, @@ -626,10 +718,13 @@ i64); define @intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32( %0, %1, @@ -646,10 +741,14 @@ i64); define @intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwadd.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32( %0, float %1, @@ -666,10 +765,13 @@ i64); define @intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32( %0, %1, @@ -686,10 +788,14 @@ i64); define @intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwadd.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.nxv8f64.nxv8f32.f32( %0, float %1, @@ -706,10 +812,13 @@ i64); define @intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwadd.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwadd.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( @@ -6,10 +7,13 @@ i32); define @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwadd.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwadd.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwadd.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv16f32.nxv16f16( %0, %1, @@ -186,10 +210,14 @@ i32); define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( %0, %1, @@ -206,10 +234,13 @@ i32); define @intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32( %0, %1, @@ -226,10 +257,12 @@ i32); define @intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32( %0, %1, @@ -246,10 +279,13 @@ i32); define @intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwadd.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32( %0, %1, @@ -266,10 +302,12 @@ i32); define @intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32( %0, %1, @@ -286,10 +324,13 @@ i32); define @intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwadd.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32( %0, %1, @@ -306,10 +347,12 @@ i32); define @intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32( %0, %1, @@ -326,10 +369,13 @@ i32); define @intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwadd.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv8f64.nxv8f32( %0, %1, @@ -346,10 +392,14 @@ i32); define @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( %0, %1, @@ -366,10 +416,14 @@ i32); define @intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwadd.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv1f32.f16( %0, half %1, @@ -386,10 +440,13 @@ i32); define @intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.f16( %0, %1, @@ -406,10 +463,14 @@ i32); define @intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwadd.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv2f32.f16( %0, half %1, @@ -426,10 +487,13 @@ i32); define @intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.f16( %0, %1, @@ -446,10 +510,14 @@ i32); define @intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwadd.wf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv4f32.f16( %0, half %1, @@ -466,10 +534,13 @@ i32); define @intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.f16( %0, %1, @@ -486,10 +557,14 @@ i32); define @intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwadd.wf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv8f32.f16( %0, half %1, @@ -506,10 +581,13 @@ i32); define @intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.f16( %0, %1, @@ -526,10 +604,14 @@ i32); define @intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwadd.wf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv16f32.f16( %0, half %1, @@ -546,10 +628,13 @@ i32); define @intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.f16( %0, %1, @@ -566,10 +651,14 @@ i32); define @intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwadd.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv1f64.f32( %0, float %1, @@ -586,10 +675,13 @@ i32); define @intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.f32( %0, %1, @@ -606,10 +698,14 @@ i32); define @intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwadd.wf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv2f64.f32( %0, float %1, @@ -626,10 +722,13 @@ i32); define @intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.f32( %0, %1, @@ -646,10 +745,14 @@ i32); define @intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwadd.wf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv4f64.f32( %0, float %1, @@ -666,10 +769,13 @@ i32); define @intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.f32( %0, %1, @@ -686,10 +792,14 @@ i32); define @intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwadd.wf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv8f64.f32( %0, float %1, @@ -706,10 +816,13 @@ i32); define @intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( @@ -6,10 +7,13 @@ i64); define @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwadd.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwadd.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwadd.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv16f32.nxv16f16( %0, %1, @@ -186,10 +210,14 @@ i64); define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( %0, %1, @@ -206,10 +234,13 @@ i64); define @intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32( %0, %1, @@ -226,10 +257,12 @@ i64); define @intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32( %0, %1, @@ -246,10 +279,13 @@ i64); define @intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwadd.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32( %0, %1, @@ -266,10 +302,12 @@ i64); define @intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32( %0, %1, @@ -286,10 +324,13 @@ i64); define @intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwadd.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32( %0, %1, @@ -306,10 +347,12 @@ i64); define @intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32( %0, %1, @@ -326,10 +369,13 @@ i64); define @intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwadd.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv8f64.nxv8f32( %0, %1, @@ -346,10 +392,14 @@ i64); define @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( %0, %1, @@ -366,10 +416,14 @@ i64); define @intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwadd.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv1f32.f16( %0, half %1, @@ -386,10 +440,13 @@ i64); define @intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.f16( %0, %1, @@ -406,10 +463,14 @@ i64); define @intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwadd.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv2f32.f16( %0, half %1, @@ -426,10 +487,13 @@ i64); define @intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.f16( %0, %1, @@ -446,10 +510,14 @@ i64); define @intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwadd.wf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv4f32.f16( %0, half %1, @@ -466,10 +534,13 @@ i64); define @intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.f16( %0, %1, @@ -486,10 +557,14 @@ i64); define @intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwadd.wf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv8f32.f16( %0, half %1, @@ -506,10 +581,13 @@ i64); define @intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.f16( %0, %1, @@ -526,10 +604,14 @@ i64); define @intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwadd.wf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv16f32.f16( %0, half %1, @@ -546,10 +628,13 @@ i64); define @intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.f16( %0, %1, @@ -566,10 +651,14 @@ i64); define @intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwadd.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv1f64.f32( %0, float %1, @@ -586,10 +675,13 @@ i64); define @intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.f32( %0, %1, @@ -606,10 +698,14 @@ i64); define @intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwadd.wf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv2f64.f32( %0, float %1, @@ -626,10 +722,13 @@ i64); define @intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.f32( %0, %1, @@ -646,10 +745,14 @@ i64); define @intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwadd.wf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv4f64.f32( %0, float %1, @@ -666,10 +769,13 @@ i64); define @intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.f32( %0, %1, @@ -686,10 +792,14 @@ i64); define @intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwadd.wf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwadd.w.nxv8f64.f32( %0, float %1, @@ -706,10 +816,13 @@ i64); define @intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwadd.wf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwadd.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i32); define @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32( %0, i32 %1) @@ -203,10 +232,12 @@ i32); define @intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32( %0, %1, @@ -221,10 +252,13 @@ i32); define @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32( %0, i32 %1) @@ -239,10 +273,12 @@ i32); define @intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32( %0, %1, @@ -257,10 +293,13 @@ i32); define @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32( %0, i32 %1) @@ -275,10 +314,12 @@ i32); define @intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32( %0, %1, @@ -293,10 +334,13 @@ i32); define @intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32( %0, i32 %1) @@ -311,10 +355,12 @@ i32); define @intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv2f32.nxv2f16( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv8f32.nxv8f16( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv16f32.nxv16f16( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv16f32.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv1f64.nxv1f32( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv1f64.nxv1f32( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv2f64.nxv2f32( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv2f64.nxv2f32( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv4f64.nxv4f32( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv4f64.nxv4f32( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.f.v_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.f.v.nxv8f64.nxv8f32( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.f.v_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.f.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.f.v.mask.nxv8f64.nxv8f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv2f16_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f16.nxv2i8( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv4f16_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f16.nxv4i8( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv8f16_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f16.nxv8i8( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv16f16_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv16f16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv16f16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f16.nxv16i8( %0, %1, @@ -185,10 +211,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8( %0, i32 %1) @@ -203,10 +232,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv32f16_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv32f16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv32f16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv32f16.nxv32i8( %0, %1, @@ -221,10 +252,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16( %0, i32 %1) @@ -239,10 +273,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv1f32_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16( %0, %1, @@ -257,10 +293,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16( %0, i32 %1) @@ -275,10 +314,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv2f32_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16( %0, %1, @@ -293,10 +334,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16( %0, i32 %1) @@ -311,10 +355,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv4f32_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16( %0, %1, @@ -329,10 +375,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16( %0, i32 %1) @@ -347,10 +396,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv8f32_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16( %0, %1, @@ -365,10 +416,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16( %0, i32 %1) @@ -383,10 +437,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv16f32_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv16f32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv16f32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16( %0, %1, @@ -401,10 +457,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32( %0, i32 %1) @@ -419,10 +478,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv1f64_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32( %0, %1, @@ -437,10 +498,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32( %0, i32 %1) @@ -455,10 +519,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv2f64_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32( %0, %1, @@ -473,10 +539,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32( %0, i32 %1) @@ -491,10 +560,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv4f64_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32( %0, %1, @@ -509,10 +580,13 @@ i32); define @intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32( %0, i32 %1) @@ -527,10 +601,12 @@ i32); define @intrinsic_vfwcvt_mask_f.x.v_nxv8f64_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f16.nxv1i8( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv2f16.nxv2i8( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv2f16_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f16.nxv2i8( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv4f16.nxv4i8( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv4f16_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f16.nxv4i8( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv8f16.nxv8i8( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv8f16_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f16.nxv8i8( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv16f16.nxv16i8( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv16f16_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv16f16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv16f16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f16.nxv16i8( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv32f16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv32f16.nxv32i8( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv32f16_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv32f16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv32f16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv32f16.nxv32i8( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv1f32.nxv1i16( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv1f32_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f32.nxv1i16( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv2f32.nxv2i16( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv2f32_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f32.nxv2i16( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv4f32.nxv4i16( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv4f32_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f32.nxv4i16( %0, %1, @@ -329,10 +375,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv8f32.nxv8i16( %0, i64 %1) @@ -347,10 +396,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv8f32_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f32.nxv8i16( %0, %1, @@ -365,10 +416,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv16f32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv16f32.nxv16i16( %0, i64 %1) @@ -383,10 +437,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv16f32_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv16f32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv16f32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv16f32.nxv16i16( %0, %1, @@ -401,10 +457,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv1f64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv1f64.nxv1i32( %0, i64 %1) @@ -419,10 +478,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv1f64_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv1f64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv1f64.nxv1i32( %0, %1, @@ -437,10 +498,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv2f64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv2f64.nxv2i32( %0, i64 %1) @@ -455,10 +519,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv2f64_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv2f64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv2f64.nxv2i32( %0, %1, @@ -473,10 +539,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv4f64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv4f64.nxv4i32( %0, i64 %1) @@ -491,10 +560,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv4f64_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv4f64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv4f64.nxv4i32( %0, %1, @@ -509,10 +580,13 @@ i64); define @intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.x.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.x.v_nxv8f64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.x.v.nxv8f64.nxv8i32( %0, i64 %1) @@ -527,10 +601,12 @@ i64); define @intrinsic_vfwcvt_mask_f.x.v_nxv8f64_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.x.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.x.v_nxv8f64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.f.x.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.x.v.mask.nxv8f64.nxv8i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv1f16_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f16.nxv1i8( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv2f16_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f16.nxv2i8( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv4f16_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f16.nxv4i8( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv8f16_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f16.nxv8i8( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv16f16_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv16f16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv16f16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f16.nxv16i8( %0, %1, @@ -185,10 +211,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8( %0, i32 %1) @@ -203,10 +232,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv32f16_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv32f16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv32f16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv32f16.nxv32i8( %0, %1, @@ -221,10 +252,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16( %0, i32 %1) @@ -239,10 +273,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv1f32_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16( %0, %1, @@ -257,10 +293,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16( %0, i32 %1) @@ -275,10 +314,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv2f32_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16( %0, %1, @@ -293,10 +334,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16( %0, i32 %1) @@ -311,10 +355,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv4f32_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16( %0, %1, @@ -329,10 +375,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16( %0, i32 %1) @@ -347,10 +396,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv8f32_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16( %0, %1, @@ -365,10 +416,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16( %0, i32 %1) @@ -383,10 +437,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv16f32_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv16f32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv16f32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16( %0, %1, @@ -401,10 +457,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32( %0, i32 %1) @@ -419,10 +478,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv1f64_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32( %0, %1, @@ -437,10 +498,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32( %0, i32 %1) @@ -455,10 +519,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv2f64_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32( %0, %1, @@ -473,10 +539,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32( %0, i32 %1) @@ -491,10 +560,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv4f64_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32( %0, %1, @@ -509,10 +580,13 @@ i32); define @intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32( %0, i32 %1) @@ -527,10 +601,12 @@ i32); define @intrinsic_vfwcvt_mask_f.xu.v_nxv8f64_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv1f16_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f16.nxv1i8( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f16.nxv2i8( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv2f16_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f16.nxv2i8( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f16.nxv4i8( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv4f16_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f16.nxv4i8( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f16.nxv8i8( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv8f16_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f16.nxv8i8( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f16.nxv16i8( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv16f16_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv16f16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv16f16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f16.nxv16i8( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv32f16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv32f16.nxv32i8( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv32f16_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv32f16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv32f16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv32f16.nxv32i8( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f32.nxv1i16( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv1f32_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f32.nxv1i16( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f32.nxv2i16( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv2f32_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f32.nxv2i16( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f32.nxv4i16( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv4f32_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f32.nxv4i16( %0, %1, @@ -329,10 +375,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f32.nxv8i16( %0, i64 %1) @@ -347,10 +396,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv8f32_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f32.nxv8i16( %0, %1, @@ -365,10 +416,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv16f32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv16f32.nxv16i16( %0, i64 %1) @@ -383,10 +437,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv16f32_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv16f32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv16f32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv16f32.nxv16i16( %0, %1, @@ -401,10 +457,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv1f64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv1f64.nxv1i32( %0, i64 %1) @@ -419,10 +478,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv1f64_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv1f64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv1f64.nxv1i32( %0, %1, @@ -437,10 +498,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv2f64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv2f64.nxv2i32( %0, i64 %1) @@ -455,10 +519,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv2f64_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv2f64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv2f64.nxv2i32( %0, %1, @@ -473,10 +539,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv4f64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv4f64.nxv4i32( %0, i64 %1) @@ -491,10 +560,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv4f64_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv4f64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv4f64.nxv4i32( %0, %1, @@ -509,10 +580,13 @@ i64); define @intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.f.xu.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_f.xu.v_nxv8f64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.f.xu.v.nxv8f64.nxv8i32( %0, i64 %1) @@ -527,10 +601,12 @@ i64); define @intrinsic_vfwcvt_mask_f.xu.v_nxv8f64_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.f.xu.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_f.xu.v_nxv8f64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.f.xu.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.f.xu.v.mask.nxv8f64.nxv8i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv1i32_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv2i32_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv4i32_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv8i32_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv16i32_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv16i32.nxv16f16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv1i32_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i32.nxv2f16( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv2i32_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i32.nxv4f16( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv4i32_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i32.nxv8f16( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv8i32_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv16i32.nxv16f16( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv16i32_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv16i32.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv1i64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i64.nxv1f32( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv1i64_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv1i64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv1i64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv1i64.nxv1f32( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv2i64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv2i64.nxv2f32( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv2i64_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv2i64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv2i64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv2i64.nxv2f32( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv4i64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv4i64.nxv4f32( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv4i64_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv4i64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv4i64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv4i64.nxv4f32( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfwcvt_rtz.x.f.v_nxv8i64_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.x.f.v_nxv8i64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.nxv8i64.nxv8f32( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.x.f.v_nxv8i64_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv8i64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.x.f.v_nxv8i64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.rtz.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.x.f.v.mask.nxv8i64.nxv8f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i32.nxv2f16( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i32.nxv4f16( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i32.nxv8f16( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv16i32.nxv16f16( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv16i32.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv1i64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i64.nxv1f32( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv1i64_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv1i64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv1i64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv1i64.nxv1f32( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv2i64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv2i64.nxv2f32( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv2i64_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv2i64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv2i64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv2i64.nxv2f32( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv4i64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv4i64.nxv4f32( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv4i64_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv4i64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv4i64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv4i64.nxv4f32( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfwcvt_rtz.xu.f.v_nxv8i64_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_rtz.xu.f.v_nxv8i64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv8i64.nxv8f32( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv8i64_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv8i64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_rtz.xu.f.v_nxv8i64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.rtz.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.rtz.xu.f.v.mask.nxv8i64.nxv8f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfwcvt_mask_x.f.v_nxv1i64_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfwcvt_mask_x.f.v_nxv2i64_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfwcvt_mask_x.f.v_nxv4i64_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.x.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfwcvt_mask_x.f.v_nxv8i64_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.x.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.x.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( @@ -5,10 +6,13 @@ i32); define @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( %0, i32 %1) @@ -23,10 +27,12 @@ i32); define @intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i32); define @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16( %0, i32 %1) @@ -59,10 +68,12 @@ i32); define @intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i32); define @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16( %0, i32 %1) @@ -95,10 +109,12 @@ i32); define @intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i32); define @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16( %0, i32 %1) @@ -131,10 +150,12 @@ i32); define @intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i32); define @intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16( %0, i32 %1) @@ -167,10 +191,12 @@ i32); define @intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( @@ -5,10 +6,13 @@ i64); define @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( %0, i64 %1) @@ -23,10 +27,12 @@ i64); define @intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16( %0, %1, @@ -41,10 +47,13 @@ i64); define @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16( %0, i64 %1) @@ -59,10 +68,12 @@ i64); define @intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16( %0, %1, @@ -77,10 +88,13 @@ i64); define @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16( %0, i64 %1) @@ -95,10 +109,12 @@ i64); define @intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16( %0, %1, @@ -113,10 +129,13 @@ i64); define @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16( %0, i64 %1) @@ -131,10 +150,12 @@ i64); define @intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16( %0, %1, @@ -149,10 +170,13 @@ i64); define @intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16( %0, i64 %1) @@ -167,10 +191,12 @@ i64); define @intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16( %0, %1, @@ -185,10 +211,13 @@ i64); define @intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32( %0, i64 %1) @@ -203,10 +232,12 @@ i64); define @intrinsic_vfwcvt_mask_xu.f.v_nxv1i64_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32( %0, %1, @@ -221,10 +252,13 @@ i64); define @intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32( %0, i64 %1) @@ -239,10 +273,12 @@ i64); define @intrinsic_vfwcvt_mask_xu.f.v_nxv2i64_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32( %0, %1, @@ -257,10 +293,13 @@ i64); define @intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32( %0, i64 %1) @@ -275,10 +314,12 @@ i64); define @intrinsic_vfwcvt_mask_xu.f.v_nxv4i64_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32( %0, %1, @@ -293,10 +334,13 @@ i64); define @intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwcvt.xu.f.v v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32( %0, i64 %1) @@ -311,10 +355,12 @@ i64); define @intrinsic_vfwcvt_mask_xu.f.v_nxv8i64_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwcvt.xu.f.v v8, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwcvt.xu.f.v {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18 +; CHECK-NEXT: vfwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18 +; CHECK-NEXT: vfwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v18, v19 +; CHECK-NEXT: vfwmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v20, v22 +; CHECK-NEXT: vfwmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16( @@ -194,11 +194,8 @@ define @intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv16f32.nxv16f16( @@ -220,11 +217,8 @@ define @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16( @@ -247,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18 +; CHECK-NEXT: vfwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv1f64.nxv1f32( @@ -270,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v18, v19 +; CHECK-NEXT: vfwmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv2f64.nxv2f32( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v20, v22 +; CHECK-NEXT: vfwmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv4f64.nxv4f32( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32( @@ -384,11 +378,8 @@ define @intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv8f64.nxv8f32( @@ -410,11 +401,8 @@ define @intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32( @@ -438,7 +426,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv1f32.f16( @@ -462,7 +450,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f32.f16( @@ -486,7 +474,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv2f32.f16( @@ -510,7 +498,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f32.f16( @@ -534,7 +522,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv4f32.f16( @@ -558,7 +546,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f32.f16( @@ -582,7 +570,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv8f32.f16( @@ -606,7 +594,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f32.f16( @@ -628,11 +616,9 @@ define @intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmacc.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv16f32.f16( @@ -654,11 +640,9 @@ define @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmacc.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv16f32.f16( @@ -682,7 +666,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv1f64.f32( @@ -706,7 +690,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f64.f32( @@ -730,7 +714,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv2f64.f32( @@ -754,7 +738,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f64.f32( @@ -778,7 +762,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv4f64.f32( @@ -802,7 +786,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f64.f32( @@ -824,11 +808,9 @@ define @intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmacc.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv8f64.f32( @@ -850,11 +832,9 @@ define @intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmacc.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18 +; CHECK-NEXT: vfwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18 +; CHECK-NEXT: vfwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v18, v19 +; CHECK-NEXT: vfwmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v20, v22 +; CHECK-NEXT: vfwmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16( @@ -194,11 +194,8 @@ define @intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv16f32.nxv16f16( @@ -220,11 +217,8 @@ define @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16( @@ -247,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18 +; CHECK-NEXT: vfwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv1f64.nxv1f32( @@ -270,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v18, v19 +; CHECK-NEXT: vfwmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv2f64.nxv2f32( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v20, v22 +; CHECK-NEXT: vfwmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv4f64.nxv4f32( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32( @@ -384,11 +378,8 @@ define @intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv8f64.nxv8f32( @@ -410,11 +401,8 @@ define @intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32( @@ -438,7 +426,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv1f32.f16( @@ -462,7 +450,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f32.f16( @@ -486,7 +474,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv2f32.f16( @@ -510,7 +498,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f32.f16( @@ -534,7 +522,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv4f32.f16( @@ -558,7 +546,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f32.f16( @@ -582,7 +570,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv8f32.f16( @@ -606,7 +594,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f32.f16( @@ -628,11 +616,9 @@ define @intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmacc.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv16f32.f16( @@ -654,11 +640,9 @@ define @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmacc.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv16f32.f16( @@ -682,7 +666,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv1f64.f32( @@ -706,7 +690,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f64.f32( @@ -730,7 +714,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv2f64.f32( @@ -754,7 +738,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f64.f32( @@ -778,7 +762,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfwmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv4f64.f32( @@ -802,7 +786,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f64.f32( @@ -824,11 +808,9 @@ define @intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmacc.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.nxv8f64.f32( @@ -850,11 +832,9 @@ define @intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmacc.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmacc.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v18, v19 +; CHECK-NEXT: vfwmsac.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v20, v22 +; CHECK-NEXT: vfwmsac.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16( @@ -194,11 +194,8 @@ define @intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmsac.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv16f32.nxv16f16( @@ -220,11 +217,8 @@ define @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16( @@ -247,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv1f64.nxv1f32( @@ -270,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v18, v19 +; CHECK-NEXT: vfwmsac.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv2f64.nxv2f32( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v20, v22 +; CHECK-NEXT: vfwmsac.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv4f64.nxv4f32( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32( @@ -384,11 +378,8 @@ define @intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmsac.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv8f64.nxv8f32( @@ -410,11 +401,8 @@ define @intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32( @@ -438,7 +426,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv1f32.f16( @@ -462,7 +450,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f32.f16( @@ -486,7 +474,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv2f32.f16( @@ -510,7 +498,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f32.f16( @@ -534,7 +522,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv4f32.f16( @@ -558,7 +546,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f32.f16( @@ -582,7 +570,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv8f32.f16( @@ -606,7 +594,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f32.f16( @@ -628,11 +616,9 @@ define @intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmsac.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv16f32.f16( @@ -654,11 +640,9 @@ define @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmsac.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv16f32.f16( @@ -682,7 +666,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv1f64.f32( @@ -706,7 +690,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f64.f32( @@ -730,7 +714,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv2f64.f32( @@ -754,7 +738,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f64.f32( @@ -778,7 +762,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv4f64.f32( @@ -802,7 +786,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f64.f32( @@ -824,11 +808,9 @@ define @intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmsac.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv8f64.f32( @@ -850,11 +832,9 @@ define @intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmsac.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v18, v19 +; CHECK-NEXT: vfwmsac.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v20, v22 +; CHECK-NEXT: vfwmsac.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16( @@ -194,11 +194,8 @@ define @intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmsac.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv16f32.nxv16f16( @@ -220,11 +217,8 @@ define @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16( @@ -247,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv1f64.nxv1f32( @@ -270,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v18, v19 +; CHECK-NEXT: vfwmsac.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv2f64.nxv2f32( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v20, v22 +; CHECK-NEXT: vfwmsac.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv4f64.nxv4f32( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32( @@ -384,11 +378,8 @@ define @intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmsac.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv8f64.nxv8f32( @@ -410,11 +401,8 @@ define @intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmsac.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32( @@ -438,7 +426,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv1f32.f16( @@ -462,7 +450,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f32.f16( @@ -486,7 +474,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv2f32.f16( @@ -510,7 +498,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f32.f16( @@ -534,7 +522,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv4f32.f16( @@ -558,7 +546,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f32.f16( @@ -582,7 +570,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv8f32.f16( @@ -606,7 +594,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f32.f16( @@ -628,11 +616,9 @@ define @intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmsac.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv16f32.f16( @@ -654,11 +640,9 @@ define @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmsac.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv16f32.f16( @@ -682,7 +666,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv1f64.f32( @@ -706,7 +690,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f64.f32( @@ -730,7 +714,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv2f64.f32( @@ -754,7 +738,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f64.f32( @@ -778,7 +762,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfwmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv4f64.f32( @@ -802,7 +786,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f64.f32( @@ -824,11 +808,9 @@ define @intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmsac.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.nxv8f64.f32( @@ -850,11 +832,9 @@ define @intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwmsac.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmsac.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( @@ -6,10 +7,13 @@ i32); define @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwmul.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwmul.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwmul.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwmul.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwmul.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwmul.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -366,10 +412,14 @@ i32); define @intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwmul.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16( %0, half %1, @@ -386,10 +436,13 @@ i32); define @intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.f16( %0, %1, @@ -406,10 +459,14 @@ i32); define @intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwmul.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16( %0, half %1, @@ -426,10 +483,13 @@ i32); define @intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.f16( %0, %1, @@ -446,10 +506,14 @@ i32); define @intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwmul.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16( %0, half %1, @@ -466,10 +530,13 @@ i32); define @intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.f16( %0, %1, @@ -486,10 +553,14 @@ i32); define @intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwmul.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16( %0, half %1, @@ -506,10 +577,13 @@ i32); define @intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.f16( %0, %1, @@ -526,10 +600,14 @@ i32); define @intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwmul.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.f16( %0, half %1, @@ -546,10 +624,13 @@ i32); define @intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.f16( %0, %1, @@ -566,10 +647,14 @@ i32); define @intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwmul.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv1f64.nxv1f32.f32( %0, float %1, @@ -586,10 +671,13 @@ i32); define @intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.f32( %0, %1, @@ -606,10 +694,14 @@ i32); define @intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwmul.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv2f64.nxv2f32.f32( %0, float %1, @@ -626,10 +718,13 @@ i32); define @intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.f32( %0, %1, @@ -646,10 +741,14 @@ i32); define @intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwmul.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv4f64.nxv4f32.f32( %0, float %1, @@ -666,10 +765,13 @@ i32); define @intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.f32( %0, %1, @@ -686,10 +788,14 @@ i32); define @intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwmul.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv8f64.nxv8f32.f32( %0, float %1, @@ -706,10 +812,13 @@ i32); define @intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( @@ -6,10 +7,13 @@ i64); define @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwmul.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwmul.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwmul.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwmul.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwmul.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwmul.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwmul.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -366,10 +412,14 @@ i64); define @intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwmul.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16( %0, half %1, @@ -386,10 +436,13 @@ i64); define @intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.f16( %0, %1, @@ -406,10 +459,14 @@ i64); define @intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwmul.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16( %0, half %1, @@ -426,10 +483,13 @@ i64); define @intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.f16( %0, %1, @@ -446,10 +506,14 @@ i64); define @intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwmul.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16( %0, half %1, @@ -466,10 +530,13 @@ i64); define @intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.f16( %0, %1, @@ -486,10 +553,14 @@ i64); define @intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwmul.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16( %0, half %1, @@ -506,10 +577,13 @@ i64); define @intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.f16( %0, %1, @@ -526,10 +600,14 @@ i64); define @intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwmul.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv16f32.nxv16f16.f16( %0, half %1, @@ -546,10 +624,13 @@ i64); define @intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.f16( %0, %1, @@ -566,10 +647,14 @@ i64); define @intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwmul.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv1f64.nxv1f32.f32( %0, float %1, @@ -586,10 +671,13 @@ i64); define @intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.f32( %0, %1, @@ -606,10 +694,14 @@ i64); define @intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwmul.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv2f64.nxv2f32.f32( %0, float %1, @@ -626,10 +718,13 @@ i64); define @intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.f32( %0, %1, @@ -646,10 +741,14 @@ i64); define @intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwmul.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv4f64.nxv4f32.f32( %0, float %1, @@ -666,10 +765,13 @@ i64); define @intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.f32( %0, %1, @@ -686,10 +788,14 @@ i64); define @intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwmul.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwmul.nxv8f64.nxv8f32.f32( %0, float %1, @@ -706,10 +812,13 @@ i64); define @intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwmul.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwmul.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( @@ -7,10 +8,12 @@ i32); define @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v10, v11 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v12, v14 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v16, v20 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v10, v11 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v12, v14 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v16, v20 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwnmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32( %0, %1, @@ -385,10 +422,13 @@ i32); define @intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv1f32.f16( %0, half %1, @@ -406,10 +446,13 @@ i32); define @intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv1f32.f16( %0, half %1, @@ -427,10 +470,13 @@ i32); define @intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv2f32.f16( %0, half %1, @@ -448,10 +494,13 @@ i32); define @intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv2f32.f16( %0, half %1, @@ -469,10 +518,13 @@ i32); define @intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv4f32.f16( %0, half %1, @@ -490,10 +542,13 @@ i32); define @intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv4f32.f16( %0, half %1, @@ -511,10 +566,13 @@ i32); define @intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv8f32.f16( %0, half %1, @@ -532,10 +590,13 @@ i32); define @intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv8f32.f16( %0, half %1, @@ -553,10 +614,13 @@ i32); define @intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv16f32.f16( %0, half %1, @@ -574,10 +638,13 @@ i32); define @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv16f32.f16( %0, half %1, @@ -595,10 +662,13 @@ i32); define @intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv1f64.f32( %0, float %1, @@ -616,10 +686,13 @@ i32); define @intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv1f64.f32( %0, float %1, @@ -637,10 +710,13 @@ i32); define @intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv2f64.f32( %0, float %1, @@ -658,10 +734,13 @@ i32); define @intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv2f64.f32( %0, float %1, @@ -679,10 +758,13 @@ i32); define @intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv4f64.f32( %0, float %1, @@ -700,10 +782,13 @@ i32); define @intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv4f64.f32( %0, float %1, @@ -721,10 +806,13 @@ i32); define @intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}} %a = call @llvm.riscv.vfwnmacc.nxv8f64.f32( %0, float %1, @@ -742,10 +830,13 @@ i32); define @intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwnmacc.vf {{v[0-9]+}}, ft0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwnmacc.mask.nxv8f64.f32( %0, float %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v18, v19 +; CHECK-NEXT: vfwnmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v20, v22 +; CHECK-NEXT: vfwnmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16( @@ -194,11 +194,8 @@ define @intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16( @@ -220,11 +217,8 @@ define @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16( @@ -247,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v17, v18 +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32( @@ -270,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v18, v19 +; CHECK-NEXT: vfwnmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v20, v22 +; CHECK-NEXT: vfwnmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32( @@ -384,11 +378,8 @@ define @intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32( @@ -410,11 +401,8 @@ define @intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32( @@ -438,7 +426,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv1f32.f16( @@ -462,7 +450,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f32.f16( @@ -486,7 +474,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv2f32.f16( @@ -510,7 +498,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f32.f16( @@ -534,7 +522,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv4f32.f16( @@ -558,7 +546,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f32.f16( @@ -582,7 +570,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv8f32.f16( @@ -606,7 +594,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f32.f16( @@ -628,11 +616,9 @@ define @intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv16f32.f16( @@ -654,11 +640,9 @@ define @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv16f32.f16( @@ -682,7 +666,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17 +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv1f64.f32( @@ -706,7 +690,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f64.f32( @@ -730,7 +714,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18 +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv2f64.f32( @@ -754,7 +738,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f64.f32( @@ -778,7 +762,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20 +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv4f64.f32( @@ -802,7 +786,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f64.f32( @@ -824,11 +808,9 @@ define @intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.nxv8f64.f32( @@ -850,11 +832,9 @@ define @intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwnmacc.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v18, v19 +; CHECK-NEXT: vfwnmsac.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v20, v22 +; CHECK-NEXT: vfwnmsac.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16( @@ -194,11 +194,8 @@ define @intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16( @@ -220,11 +217,8 @@ define @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16( @@ -247,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32( @@ -270,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v18, v19 +; CHECK-NEXT: vfwnmsac.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v20, v22 +; CHECK-NEXT: vfwnmsac.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32( @@ -384,11 +378,8 @@ define @intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32( @@ -410,11 +401,8 @@ define @intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32( @@ -438,7 +426,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv1f32.f16( @@ -462,7 +450,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f32.f16( @@ -486,7 +474,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv2f32.f16( @@ -510,7 +498,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f32.f16( @@ -534,7 +522,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv4f32.f16( @@ -558,7 +546,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f32.f16( @@ -582,7 +570,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv8f32.f16( @@ -606,7 +594,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f32.f16( @@ -628,11 +616,9 @@ define @intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv16f32.f16( @@ -654,11 +640,9 @@ define @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv16f32.f16( @@ -682,7 +666,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv1f64.f32( @@ -706,7 +690,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f64.f32( @@ -730,7 +714,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv2f64.f32( @@ -754,7 +738,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f64.f32( @@ -778,7 +762,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv4f64.f32( @@ -802,7 +786,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f64.f32( @@ -824,11 +808,9 @@ define @intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv8f64.f32( @@ -850,11 +832,9 @@ define @intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v18, v19 +; CHECK-NEXT: vfwnmsac.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v20, v22 +; CHECK-NEXT: vfwnmsac.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16( @@ -194,11 +194,8 @@ define @intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16( @@ -220,11 +217,8 @@ define @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16( @@ -247,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18 +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32( @@ -270,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v18, v19 +; CHECK-NEXT: vfwnmsac.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v18, v19, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v20, v22 +; CHECK-NEXT: vfwnmsac.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v20, v22, v0.t +; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32( @@ -384,11 +378,8 @@ define @intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32( @@ -410,11 +401,8 @@ define @intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32( @@ -438,7 +426,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv1f32.f16( @@ -462,7 +450,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f32.f16( @@ -486,7 +474,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv2f32.f16( @@ -510,7 +498,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f32.f16( @@ -534,7 +522,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv4f32.f16( @@ -558,7 +546,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f32.f16( @@ -582,7 +570,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv8f32.f16( @@ -606,7 +594,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f32.f16( @@ -628,11 +616,9 @@ define @intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv16f32.f16( @@ -654,11 +640,9 @@ define @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: fmv.h.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv16f32.f16( @@ -682,7 +666,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv1f64.f32( @@ -706,7 +690,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f64.f32( @@ -730,7 +714,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv2f64.f32( @@ -754,7 +738,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f64.f32( @@ -778,7 +762,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20 +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv4f64.f32( @@ -802,7 +786,7 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20, v0.t +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f64.f32( @@ -824,11 +808,9 @@ define @intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.nxv8f64.f32( @@ -850,11 +832,9 @@ define @intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) ; CHECK-NEXT: fmv.w.x ft0, a0 -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwnmsac.vf v8, ft0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( @@ -7,10 +8,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( @@ -7,10 +8,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( @@ -7,10 +8,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv1f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( @@ -7,10 +8,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( @@ -6,10 +7,13 @@ i32); define @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -366,10 +412,14 @@ i32); define @intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwsub.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16( %0, half %1, @@ -386,10 +436,13 @@ i32); define @intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.f16( %0, %1, @@ -406,10 +459,14 @@ i32); define @intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwsub.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16( %0, half %1, @@ -426,10 +483,13 @@ i32); define @intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.f16( %0, %1, @@ -446,10 +506,14 @@ i32); define @intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwsub.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16( %0, half %1, @@ -466,10 +530,13 @@ i32); define @intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.f16( %0, %1, @@ -486,10 +553,14 @@ i32); define @intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwsub.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16( %0, half %1, @@ -506,10 +577,13 @@ i32); define @intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.f16( %0, %1, @@ -526,10 +600,14 @@ i32); define @intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwsub.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv16f32.nxv16f16.f16( %0, half %1, @@ -546,10 +624,13 @@ i32); define @intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.f16( %0, %1, @@ -566,10 +647,14 @@ i32); define @intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwsub.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32( %0, float %1, @@ -586,10 +671,13 @@ i32); define @intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.f32( %0, %1, @@ -606,10 +694,14 @@ i32); define @intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwsub.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32( %0, float %1, @@ -626,10 +718,13 @@ i32); define @intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.f32( %0, %1, @@ -646,10 +741,14 @@ i32); define @intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwsub.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32( %0, float %1, @@ -666,10 +765,13 @@ i32); define @intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.f32( %0, %1, @@ -686,10 +788,14 @@ i32); define @intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwsub.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv8f64.nxv8f32.f32( %0, float %1, @@ -706,10 +812,13 @@ i32); define @intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( @@ -6,10 +7,13 @@ i64); define @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.nxv16f16( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.nxv1f32( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.nxv2f32( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.nxv4f32( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vfwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.nxv8f32( %0, %1, @@ -366,10 +412,14 @@ i64); define @intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwsub.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16( %0, half %1, @@ -386,10 +436,13 @@ i64); define @intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.f16( %0, %1, @@ -406,10 +459,14 @@ i64); define @intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwsub.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16( %0, half %1, @@ -426,10 +483,13 @@ i64); define @intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.f16( %0, %1, @@ -446,10 +506,14 @@ i64); define @intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwsub.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16( %0, half %1, @@ -466,10 +530,13 @@ i64); define @intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.f16( %0, %1, @@ -486,10 +553,14 @@ i64); define @intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwsub.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16( %0, half %1, @@ -506,10 +577,13 @@ i64); define @intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.f16( %0, %1, @@ -526,10 +600,14 @@ i64); define @intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwsub.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv16f32.nxv16f16.f16( %0, half %1, @@ -546,10 +624,13 @@ i64); define @intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.f16( %0, %1, @@ -566,10 +647,14 @@ i64); define @intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwsub.vf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32( %0, float %1, @@ -586,10 +671,13 @@ i64); define @intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.f32( %0, %1, @@ -606,10 +694,14 @@ i64); define @intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwsub.vf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32( %0, float %1, @@ -626,10 +718,13 @@ i64); define @intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.f32( %0, %1, @@ -646,10 +741,14 @@ i64); define @intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwsub.vf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32( %0, float %1, @@ -666,10 +765,13 @@ i64); define @intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.f32( %0, %1, @@ -686,10 +788,14 @@ i64); define @intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwsub.vf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.nxv8f64.nxv8f32.f32( %0, float %1, @@ -706,10 +812,13 @@ i64); define @intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwsub.vf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwsub.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( @@ -6,10 +7,13 @@ i32); define @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwsub.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwsub.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwsub.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16( %0, %1, @@ -186,10 +210,14 @@ i32); define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( %0, %1, @@ -206,10 +234,13 @@ i32); define @intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32( %0, %1, @@ -226,10 +257,12 @@ i32); define @intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32( %0, %1, @@ -246,10 +279,13 @@ i32); define @intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwsub.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( %0, %1, @@ -266,10 +302,12 @@ i32); define @intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32( %0, %1, @@ -286,10 +324,13 @@ i32); define @intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwsub.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32( %0, %1, @@ -306,10 +347,12 @@ i32); define @intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32( %0, %1, @@ -326,10 +369,13 @@ i32); define @intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwsub.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv8f64.nxv8f32( %0, %1, @@ -346,10 +392,14 @@ i32); define @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( %0, %1, @@ -366,10 +416,14 @@ i32); define @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwsub.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv1f32.f16( %0, half %1, @@ -386,10 +440,13 @@ i32); define @intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( %0, %1, @@ -406,10 +463,14 @@ i32); define @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwsub.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv2f32.f16( %0, half %1, @@ -426,10 +487,13 @@ i32); define @intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( %0, %1, @@ -446,10 +510,14 @@ i32); define @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwsub.wf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv4f32.f16( %0, half %1, @@ -466,10 +534,13 @@ i32); define @intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( %0, %1, @@ -486,10 +557,14 @@ i32); define @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwsub.wf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv8f32.f16( %0, half %1, @@ -506,10 +581,13 @@ i32); define @intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( %0, %1, @@ -526,10 +604,14 @@ i32); define @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwsub.wf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv16f32.f16( %0, half %1, @@ -546,10 +628,13 @@ i32); define @intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( %0, %1, @@ -566,10 +651,14 @@ i32); define @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwsub.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv1f64.f32( %0, float %1, @@ -586,10 +675,13 @@ i32); define @intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( %0, %1, @@ -606,10 +698,14 @@ i32); define @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwsub.wf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv2f64.f32( %0, float %1, @@ -626,10 +722,13 @@ i32); define @intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( %0, %1, @@ -646,10 +745,14 @@ i32); define @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwsub.wf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv4f64.f32( %0, float %1, @@ -666,10 +769,13 @@ i32); define @intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( %0, %1, @@ -686,10 +792,14 @@ i32); define @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwsub.wf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv8f64.f32( %0, float %1, @@ -706,10 +816,13 @@ i32); define @intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( @@ -6,10 +7,13 @@ i64); define @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vfwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vfwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vfwsub.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vfwsub.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vfwsub.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16( %0, %1, @@ -186,10 +210,14 @@ i64); define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( %0, %1, @@ -206,10 +234,13 @@ i64); define @intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vfwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32( %0, %1, @@ -226,10 +257,12 @@ i64); define @intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32( %0, %1, @@ -246,10 +279,13 @@ i64); define @intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vfwsub.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( %0, %1, @@ -266,10 +302,12 @@ i64); define @intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32( %0, %1, @@ -286,10 +324,13 @@ i64); define @intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vfwsub.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32( %0, %1, @@ -306,10 +347,12 @@ i64); define @intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32( %0, %1, @@ -326,10 +369,13 @@ i64); define @intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vfwsub.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv8f64.nxv8f32( %0, %1, @@ -346,10 +392,14 @@ i64); define @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( %0, %1, @@ -366,10 +416,14 @@ i64); define @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vfwsub.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv1f32.f16( %0, half %1, @@ -386,10 +440,13 @@ i64); define @intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( %0, %1, @@ -406,10 +463,14 @@ i64); define @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vfwsub.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv2f32.f16( %0, half %1, @@ -426,10 +487,13 @@ i64); define @intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( %0, %1, @@ -446,10 +510,14 @@ i64); define @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vfwsub.wf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv4f32.f16( %0, half %1, @@ -466,10 +534,13 @@ i64); define @intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( %0, %1, @@ -486,10 +557,14 @@ i64); define @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vfwsub.wf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv8f32.f16( %0, half %1, @@ -506,10 +581,13 @@ i64); define @intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( %0, %1, @@ -526,10 +604,14 @@ i64); define @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vfwsub.wf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv16f32.f16( %0, half %1, @@ -546,10 +628,13 @@ i64); define @intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( %0, %1, @@ -566,10 +651,14 @@ i64); define @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vfwsub.wf v25, v8, ft0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv1f64.f32( %0, float %1, @@ -586,10 +675,13 @@ i64); define @intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v9, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( %0, %1, @@ -606,10 +698,14 @@ i64); define @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vfwsub.wf v26, v8, ft0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv2f64.f32( %0, float %1, @@ -626,10 +722,13 @@ i64); define @intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v10, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( %0, %1, @@ -646,10 +745,14 @@ i64); define @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vfwsub.wf v28, v8, ft0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv4f64.f32( %0, float %1, @@ -666,10 +769,13 @@ i64); define @intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v12, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( %0, %1, @@ -686,10 +792,14 @@ i64); define @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vfwsub.wf v16, v8, ft0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vfwsub.w.nxv8f64.f32( %0, float %1, @@ -706,10 +816,13 @@ i64); define @intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vfwsub.wf v8, v16, ft0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vfwsub.wf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll @@ -1,13 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vid.nxv1i8( i32); define @intrinsic_vid_v_nxv1i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv1i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv1i8( i32 %0) @@ -20,10 +23,12 @@ i32); define @intrinsic_vid_mask_v_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv1i8( %0, %1, @@ -36,10 +41,12 @@ i32); define @intrinsic_vid_v_nxv2i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv2i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv2i8( i32 %0) @@ -52,10 +59,12 @@ i32); define @intrinsic_vid_mask_v_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv2i8( %0, %1, @@ -68,10 +77,12 @@ i32); define @intrinsic_vid_v_nxv4i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv4i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv4i8( i32 %0) @@ -84,10 +95,12 @@ i32); define @intrinsic_vid_mask_v_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv4i8( %0, %1, @@ -100,10 +113,12 @@ i32); define @intrinsic_vid_v_nxv8i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv8i8 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv8i8( i32 %0) @@ -116,10 +131,12 @@ i32); define @intrinsic_vid_mask_v_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8 -; CHECK: vsetvli {{.*}}, a0, e8,m1,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv8i8( %0, %1, @@ -132,10 +149,12 @@ i32); define @intrinsic_vid_v_nxv16i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv16i8 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv16i8( i32 %0) @@ -148,10 +167,12 @@ i32); define @intrinsic_vid_mask_v_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8 -; CHECK: vsetvli {{.*}}, a0, e8,m2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv16i8( %0, %1, @@ -164,10 +185,12 @@ i32); define @intrinsic_vid_v_nxv32i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv32i8 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv32i8( i32 %0) @@ -180,10 +203,12 @@ i32); define @intrinsic_vid_mask_v_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8 -; CHECK: vsetvli {{.*}}, a0, e8,m4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv32i8( %0, %1, @@ -196,10 +221,12 @@ i32); define @intrinsic_vid_v_nxv1i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv1i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv1i16( i32 %0) @@ -212,10 +239,12 @@ i32); define @intrinsic_vid_mask_v_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv1i16( %0, %1, @@ -228,10 +257,12 @@ i32); define @intrinsic_vid_v_nxv2i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv2i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv2i16( i32 %0) @@ -244,10 +275,12 @@ i32); define @intrinsic_vid_mask_v_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv2i16( %0, %1, @@ -260,10 +293,12 @@ i32); define @intrinsic_vid_v_nxv4i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv4i16 -; CHECK: vsetvli {{.*}}, a0, e16,m1,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv4i16( i32 %0) @@ -276,10 +311,12 @@ i32); define @intrinsic_vid_mask_v_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16 -; CHECK: vsetvli {{.*}}, a0, e16,m1,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv4i16( %0, %1, @@ -292,10 +329,12 @@ i32); define @intrinsic_vid_v_nxv8i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv8i16 -; CHECK: vsetvli {{.*}}, a0, e16,m2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv8i16( i32 %0) @@ -308,10 +347,12 @@ i32); define @intrinsic_vid_mask_v_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16 -; CHECK: vsetvli {{.*}}, a0, e16,m2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv8i16( %0, %1, @@ -324,10 +365,12 @@ i32); define @intrinsic_vid_v_nxv16i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv16i16 -; CHECK: vsetvli {{.*}}, a0, e16,m4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv16i16( i32 %0) @@ -340,10 +383,12 @@ i32); define @intrinsic_vid_mask_v_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16 -; CHECK: vsetvli {{.*}}, a0, e16,m4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv16i16( %0, %1, @@ -356,10 +401,12 @@ i32); define @intrinsic_vid_v_nxv32i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv32i16 -; CHECK: vsetvli {{.*}}, a0, e16,m8,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv32i16( i32 %0) @@ -372,10 +419,12 @@ i32); define @intrinsic_vid_mask_v_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16 -; CHECK: vsetvli {{.*}}, a0, e16,m8,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv32i16( %0, %1, @@ -388,10 +437,12 @@ i32); define @intrinsic_vid_v_nxv1i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv1i32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv1i32( i32 %0) @@ -404,10 +455,12 @@ i32); define @intrinsic_vid_mask_v_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv1i32( %0, %1, @@ -420,10 +473,12 @@ i32); define @intrinsic_vid_v_nxv2i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv2i32 -; CHECK: vsetvli {{.*}}, a0, e32,m1,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv2i32( i32 %0) @@ -436,10 +491,12 @@ i32); define @intrinsic_vid_mask_v_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32 -; CHECK: vsetvli {{.*}}, a0, e32,m1,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv2i32( %0, %1, @@ -452,10 +509,12 @@ i32); define @intrinsic_vid_v_nxv4i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv4i32 -; CHECK: vsetvli {{.*}}, a0, e32,m2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv4i32( i32 %0) @@ -468,10 +527,12 @@ i32); define @intrinsic_vid_mask_v_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32 -; CHECK: vsetvli {{.*}}, a0, e32,m2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv4i32( %0, %1, @@ -484,10 +545,12 @@ i32); define @intrinsic_vid_v_nxv8i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv8i32 -; CHECK: vsetvli {{.*}}, a0, e32,m4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv8i32( i32 %0) @@ -500,10 +563,12 @@ i32); define @intrinsic_vid_mask_v_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32 -; CHECK: vsetvli {{.*}}, a0, e32,m4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv8i32( %0, %1, @@ -516,10 +581,12 @@ i32); define @intrinsic_vid_v_nxv16i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv16i32 -; CHECK: vsetvli {{.*}}, a0, e32,m8,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv16i32( i32 %0) @@ -532,10 +599,12 @@ i32); define @intrinsic_vid_mask_v_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32 -; CHECK: vsetvli {{.*}}, a0, e32,m8,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll @@ -1,13 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vid.nxv1i8( i64); define @intrinsic_vid_v_nxv1i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv1i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv1i8( i64 %0) @@ -20,10 +23,12 @@ i64); define @intrinsic_vid_mask_v_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv1i8( %0, %1, @@ -36,10 +41,12 @@ i64); define @intrinsic_vid_v_nxv2i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv2i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv2i8( i64 %0) @@ -52,10 +59,12 @@ i64); define @intrinsic_vid_mask_v_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv2i8( %0, %1, @@ -68,10 +77,12 @@ i64); define @intrinsic_vid_v_nxv4i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv4i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv4i8( i64 %0) @@ -84,10 +95,12 @@ i64); define @intrinsic_vid_mask_v_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv4i8( %0, %1, @@ -100,10 +113,12 @@ i64); define @intrinsic_vid_v_nxv8i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv8i8 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv8i8( i64 %0) @@ -116,10 +131,12 @@ i64); define @intrinsic_vid_mask_v_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8 -; CHECK: vsetvli {{.*}}, a0, e8,m1,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv8i8( %0, %1, @@ -132,10 +149,12 @@ i64); define @intrinsic_vid_v_nxv16i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv16i8 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv16i8( i64 %0) @@ -148,10 +167,12 @@ i64); define @intrinsic_vid_mask_v_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8 -; CHECK: vsetvli {{.*}}, a0, e8,m2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv16i8( %0, %1, @@ -164,10 +185,12 @@ i64); define @intrinsic_vid_v_nxv32i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv32i8 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv32i8( i64 %0) @@ -180,10 +203,12 @@ i64); define @intrinsic_vid_mask_v_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8 -; CHECK: vsetvli {{.*}}, a0, e8,m4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv32i8( %0, %1, @@ -196,10 +221,12 @@ i64); define @intrinsic_vid_v_nxv1i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv1i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv1i16( i64 %0) @@ -212,10 +239,12 @@ i64); define @intrinsic_vid_mask_v_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv1i16( %0, %1, @@ -228,10 +257,12 @@ i64); define @intrinsic_vid_v_nxv2i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv2i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv2i16( i64 %0) @@ -244,10 +275,12 @@ i64); define @intrinsic_vid_mask_v_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv2i16( %0, %1, @@ -260,10 +293,12 @@ i64); define @intrinsic_vid_v_nxv4i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv4i16 -; CHECK: vsetvli {{.*}}, a0, e16,m1,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv4i16( i64 %0) @@ -276,10 +311,12 @@ i64); define @intrinsic_vid_mask_v_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16 -; CHECK: vsetvli {{.*}}, a0, e16,m1,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv4i16( %0, %1, @@ -292,10 +329,12 @@ i64); define @intrinsic_vid_v_nxv8i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv8i16 -; CHECK: vsetvli {{.*}}, a0, e16,m2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv8i16( i64 %0) @@ -308,10 +347,12 @@ i64); define @intrinsic_vid_mask_v_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16 -; CHECK: vsetvli {{.*}}, a0, e16,m2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv8i16( %0, %1, @@ -324,10 +365,12 @@ i64); define @intrinsic_vid_v_nxv16i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv16i16 -; CHECK: vsetvli {{.*}}, a0, e16,m4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv16i16( i64 %0) @@ -340,10 +383,12 @@ i64); define @intrinsic_vid_mask_v_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16 -; CHECK: vsetvli {{.*}}, a0, e16,m4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv16i16( %0, %1, @@ -356,10 +401,12 @@ i64); define @intrinsic_vid_v_nxv32i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv32i16 -; CHECK: vsetvli {{.*}}, a0, e16,m8,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv32i16( i64 %0) @@ -372,10 +419,12 @@ i64); define @intrinsic_vid_mask_v_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16 -; CHECK: vsetvli {{.*}}, a0, e16,m8,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv32i16( %0, %1, @@ -388,10 +437,12 @@ i64); define @intrinsic_vid_v_nxv1i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv1i32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv1i32( i64 %0) @@ -404,10 +455,12 @@ i64); define @intrinsic_vid_mask_v_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv1i32( %0, %1, @@ -420,10 +473,12 @@ i64); define @intrinsic_vid_v_nxv2i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv2i32 -; CHECK: vsetvli {{.*}}, a0, e32,m1,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv2i32( i64 %0) @@ -436,10 +491,12 @@ i64); define @intrinsic_vid_mask_v_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32 -; CHECK: vsetvli {{.*}}, a0, e32,m1,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv2i32( %0, %1, @@ -452,10 +509,12 @@ i64); define @intrinsic_vid_v_nxv4i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv4i32 -; CHECK: vsetvli {{.*}}, a0, e32,m2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv4i32( i64 %0) @@ -468,10 +527,12 @@ i64); define @intrinsic_vid_mask_v_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32 -; CHECK: vsetvli {{.*}}, a0, e32,m2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv4i32( %0, %1, @@ -484,10 +545,12 @@ i64); define @intrinsic_vid_v_nxv8i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv8i32 -; CHECK: vsetvli {{.*}}, a0, e32,m4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv8i32( i64 %0) @@ -500,10 +563,12 @@ i64); define @intrinsic_vid_mask_v_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32 -; CHECK: vsetvli {{.*}}, a0, e32,m4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv8i32( %0, %1, @@ -516,10 +581,12 @@ i64); define @intrinsic_vid_v_nxv16i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv16i32 -; CHECK: vsetvli {{.*}}, a0, e32,m8,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv16i32( i64 %0) @@ -532,10 +599,12 @@ i64); define @intrinsic_vid_mask_v_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32 -; CHECK: vsetvli {{.*}}, a0, e32,m8,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv16i32( %0, %1, @@ -548,10 +617,12 @@ i64); define @intrinsic_vid_v_nxv1i64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv1i64 -; CHECK: vsetvli {{.*}}, a0, e64,m1,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv1i64( i64 %0) @@ -564,10 +635,12 @@ i64); define @intrinsic_vid_mask_v_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i64 -; CHECK: vsetvli {{.*}}, a0, e64,m1,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv1i64( %0, %1, @@ -580,10 +653,12 @@ i64); define @intrinsic_vid_v_nxv2i64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv2i64 -; CHECK: vsetvli {{.*}}, a0, e64,m2,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv2i64( i64 %0) @@ -596,10 +671,12 @@ i64); define @intrinsic_vid_mask_v_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i64 -; CHECK: vsetvli {{.*}}, a0, e64,m2,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv2i64( %0, %1, @@ -612,10 +689,12 @@ i64); define @intrinsic_vid_v_nxv4i64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv4i64 -; CHECK: vsetvli {{.*}}, a0, e64,m4,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv4i64( i64 %0) @@ -628,10 +707,12 @@ i64); define @intrinsic_vid_mask_v_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i64 -; CHECK: vsetvli {{.*}}, a0, e64,m4,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv4i64( %0, %1, @@ -644,10 +725,12 @@ i64); define @intrinsic_vid_v_nxv8i64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vid_v_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_v_nxv8i64 -; CHECK: vsetvli {{.*}}, a0, e64,m8,ta,mu -; CHECK: vid.v {{v[0-9]+}} %a = call @llvm.riscv.vid.nxv8i64( i64 %0) @@ -660,10 +743,12 @@ i64); define @intrinsic_vid_mask_v_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vid.v v8, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i64 -; CHECK: vsetvli {{.*}}, a0, e64,m8,tu,mu -; CHECK: vid.v {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vid.mask.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv1i8( @@ -29,7 +29,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv1i8( @@ -49,7 +49,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv2i8( @@ -69,7 +69,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv2i8( @@ -89,7 +89,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv4i8( @@ -109,7 +109,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv4i8( @@ -129,7 +129,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv8i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv8i8( @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv16i8( @@ -189,7 +189,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv16i8( @@ -209,7 +209,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv32i8( @@ -229,7 +229,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv32i8( @@ -249,7 +249,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv64i8( @@ -269,7 +269,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv64i8( @@ -289,7 +289,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv1i16( @@ -309,7 +309,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv1i16( @@ -329,7 +329,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv2i16( @@ -349,7 +349,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv2i16( @@ -369,7 +369,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv4i16( @@ -389,7 +389,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv4i16( @@ -409,7 +409,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv8i16( @@ -429,7 +429,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv8i16( @@ -449,7 +449,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv16i16( @@ -469,7 +469,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv16i16( @@ -489,7 +489,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv32i16( @@ -509,7 +509,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i16_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv32i16( @@ -529,7 +529,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv1i32( @@ -549,7 +549,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i32_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv1i32( @@ -569,7 +569,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv2i32( @@ -589,7 +589,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i32_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv2i32( @@ -609,7 +609,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv4i32( @@ -629,7 +629,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i32_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv4i32( @@ -649,7 +649,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv8i32( @@ -669,7 +669,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i32_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv8i32( @@ -689,7 +689,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv16i32( @@ -709,7 +709,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i32_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv16i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv1i8( @@ -29,7 +29,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv1i8( @@ -49,7 +49,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv2i8( @@ -69,7 +69,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv2i8( @@ -89,7 +89,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv4i8( @@ -109,7 +109,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv4i8( @@ -129,7 +129,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv8i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv8i8( @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv16i8( @@ -189,7 +189,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv16i8( @@ -209,7 +209,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv32i8( @@ -229,7 +229,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv32i8( @@ -249,7 +249,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv64i8( @@ -269,7 +269,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv64i8( @@ -289,7 +289,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv1i16( @@ -309,7 +309,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv1i16( @@ -329,7 +329,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv2i16( @@ -349,7 +349,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv2i16( @@ -369,7 +369,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv4i16( @@ -389,7 +389,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv4i16( @@ -409,7 +409,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv8i16( @@ -429,7 +429,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv8i16( @@ -449,7 +449,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv16i16( @@ -469,7 +469,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv16i16( @@ -489,7 +489,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv32i16( @@ -509,7 +509,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i16_nxv32i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv32i16( @@ -529,7 +529,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv1i32( @@ -549,7 +549,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i32_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv1i32( @@ -569,7 +569,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv2i32( @@ -589,7 +589,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i32_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv2i32( @@ -609,7 +609,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv4i32( @@ -629,7 +629,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i32_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv4i32( @@ -649,7 +649,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv8i32( @@ -669,7 +669,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i32_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv8i32( @@ -689,7 +689,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv16i32( @@ -709,7 +709,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i32_nxv16i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv16i32( @@ -729,7 +729,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv1i64_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv1i64( @@ -749,7 +749,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i64_nxv1i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv1i64( @@ -769,7 +769,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv2i64_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv2i64( @@ -789,7 +789,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i64_nxv2i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv2i64( @@ -809,7 +809,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv4i64_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv4i64( @@ -829,7 +829,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i64_nxv4i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv4i64( @@ -849,7 +849,7 @@ ; CHECK-LABEL: intrinsic_viota_m_nxv8i64_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: viota.m v16, v0 +; CHECK-NEXT: viota.m v8, v0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.nxv8i64( @@ -869,7 +869,7 @@ ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i64_nxv8i1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu -; CHECK-NEXT: viota.m v16, v0, v0.t +; CHECK-NEXT: viota.m v8, v0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.viota.mask.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: -mattr=+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s @@ -6,10 +7,12 @@ i32); define @intrinsic_vle_v_nxv1i32_nxv1i32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1i32( * %0, i32 %1) @@ -24,10 +27,12 @@ i32); define @intrinsic_vle_mask_v_nxv1i32_nxv1i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1i32( %0, * %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vle_v_nxv2i32_nxv2i32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2i32( * %0, i32 %1) @@ -60,10 +67,12 @@ i32); define @intrinsic_vle_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2i32( %0, * %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vle_v_nxv4i32_nxv4i32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4i32( * %0, i32 %1) @@ -96,10 +107,12 @@ i32); define @intrinsic_vle_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4i32( %0, * %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vle_v_nxv8i32_nxv8i32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8i32( * %0, i32 %1) @@ -132,10 +147,12 @@ i32); define @intrinsic_vle_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8i32( %0, * %1, @@ -150,10 +167,12 @@ i32); define @intrinsic_vle_v_nxv16i32_nxv16i32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16i32( * %0, i32 %1) @@ -168,10 +187,12 @@ i32); define @intrinsic_vle_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16i32( %0, * %1, @@ -186,10 +207,12 @@ i32); define @intrinsic_vle_v_nxv1f32_nxv1f32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1f32( * %0, i32 %1) @@ -204,10 +227,12 @@ i32); define @intrinsic_vle_mask_v_nxv1f32_nxv1f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1f32( %0, * %1, @@ -222,10 +247,12 @@ i32); define @intrinsic_vle_v_nxv2f32_nxv2f32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2f32( * %0, i32 %1) @@ -240,10 +267,12 @@ i32); define @intrinsic_vle_mask_v_nxv2f32_nxv2f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2f32( %0, * %1, @@ -258,10 +287,12 @@ i32); define @intrinsic_vle_v_nxv4f32_nxv4f32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4f32( * %0, i32 %1) @@ -276,10 +307,12 @@ i32); define @intrinsic_vle_mask_v_nxv4f32_nxv4f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4f32( %0, * %1, @@ -294,10 +327,12 @@ i32); define @intrinsic_vle_v_nxv8f32_nxv8f32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8f32( * %0, i32 %1) @@ -312,10 +347,12 @@ i32); define @intrinsic_vle_mask_v_nxv8f32_nxv8f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8f32( %0, * %1, @@ -330,10 +367,12 @@ i32); define @intrinsic_vle_v_nxv16f32_nxv16f32(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16f32( * %0, i32 %1) @@ -348,10 +387,12 @@ i32); define @intrinsic_vle_mask_v_nxv16f32_nxv16f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16f32( %0, * %1, @@ -366,10 +407,12 @@ i32); define @intrinsic_vle_v_nxv1i16_nxv1i16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1i16( * %0, i32 %1) @@ -384,10 +427,12 @@ i32); define @intrinsic_vle_mask_v_nxv1i16_nxv1i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1i16( %0, * %1, @@ -402,10 +447,12 @@ i32); define @intrinsic_vle_v_nxv2i16_nxv2i16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2i16( * %0, i32 %1) @@ -420,10 +467,12 @@ i32); define @intrinsic_vle_mask_v_nxv2i16_nxv2i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2i16( %0, * %1, @@ -438,10 +487,12 @@ i32); define @intrinsic_vle_v_nxv4i16_nxv4i16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4i16( * %0, i32 %1) @@ -456,10 +507,12 @@ i32); define @intrinsic_vle_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4i16( %0, * %1, @@ -474,10 +527,12 @@ i32); define @intrinsic_vle_v_nxv8i16_nxv8i16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8i16( * %0, i32 %1) @@ -492,10 +547,12 @@ i32); define @intrinsic_vle_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8i16( %0, * %1, @@ -510,10 +567,12 @@ i32); define @intrinsic_vle_v_nxv16i16_nxv16i16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16i16( * %0, i32 %1) @@ -528,10 +587,12 @@ i32); define @intrinsic_vle_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16i16( %0, * %1, @@ -546,10 +607,12 @@ i32); define @intrinsic_vle_v_nxv32i16_nxv32i16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv32i16( * %0, i32 %1) @@ -564,10 +627,12 @@ i32); define @intrinsic_vle_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv32i16( %0, * %1, @@ -582,10 +647,12 @@ i32); define @intrinsic_vle_v_nxv1f16_nxv1f16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1f16( * %0, i32 %1) @@ -600,10 +667,12 @@ i32); define @intrinsic_vle_mask_v_nxv1f16_nxv1f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1f16( %0, * %1, @@ -618,10 +687,12 @@ i32); define @intrinsic_vle_v_nxv2f16_nxv2f16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2f16( * %0, i32 %1) @@ -636,10 +707,12 @@ i32); define @intrinsic_vle_mask_v_nxv2f16_nxv2f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2f16( %0, * %1, @@ -654,10 +727,12 @@ i32); define @intrinsic_vle_v_nxv4f16_nxv4f16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4f16( * %0, i32 %1) @@ -672,10 +747,12 @@ i32); define @intrinsic_vle_mask_v_nxv4f16_nxv4f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4f16( %0, * %1, @@ -690,10 +767,12 @@ i32); define @intrinsic_vle_v_nxv8f16_nxv8f16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8f16( * %0, i32 %1) @@ -708,10 +787,12 @@ i32); define @intrinsic_vle_mask_v_nxv8f16_nxv8f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8f16( %0, * %1, @@ -726,10 +807,12 @@ i32); define @intrinsic_vle_v_nxv16f16_nxv16f16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16f16( * %0, i32 %1) @@ -744,10 +827,12 @@ i32); define @intrinsic_vle_mask_v_nxv16f16_nxv16f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16f16( %0, * %1, @@ -762,10 +847,12 @@ i32); define @intrinsic_vle_v_nxv32f16_nxv32f16(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv32f16( * %0, i32 %1) @@ -780,10 +867,12 @@ i32); define @intrinsic_vle_mask_v_nxv32f16_nxv32f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv32f16( %0, * %1, @@ -798,10 +887,12 @@ i32); define @intrinsic_vle_v_nxv1i8_nxv1i8(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1i8( * %0, i32 %1) @@ -816,10 +907,12 @@ i32); define @intrinsic_vle_mask_v_nxv1i8_nxv1i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1i8( %0, * %1, @@ -834,10 +927,12 @@ i32); define @intrinsic_vle_v_nxv2i8_nxv2i8(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2i8( * %0, i32 %1) @@ -852,10 +947,12 @@ i32); define @intrinsic_vle_mask_v_nxv2i8_nxv2i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2i8( %0, * %1, @@ -870,10 +967,12 @@ i32); define @intrinsic_vle_v_nxv4i8_nxv4i8(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4i8( * %0, i32 %1) @@ -888,10 +987,12 @@ i32); define @intrinsic_vle_mask_v_nxv4i8_nxv4i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4i8( %0, * %1, @@ -906,10 +1007,12 @@ i32); define @intrinsic_vle_v_nxv8i8_nxv8i8(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8i8( * %0, i32 %1) @@ -924,10 +1027,12 @@ i32); define @intrinsic_vle_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8i8( %0, * %1, @@ -942,10 +1047,12 @@ i32); define @intrinsic_vle_v_nxv16i8_nxv16i8(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16i8( * %0, i32 %1) @@ -960,10 +1067,12 @@ i32); define @intrinsic_vle_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16i8( %0, * %1, @@ -978,10 +1087,12 @@ i32); define @intrinsic_vle_v_nxv32i8_nxv32i8(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv32i8( * %0, i32 %1) @@ -996,10 +1107,12 @@ i32); define @intrinsic_vle_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv32i8( %0, * %1, @@ -1014,10 +1127,12 @@ i32); define @intrinsic_vle_v_nxv64i8_nxv64i8(* %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv64i8( * %0, i32 %1) @@ -1032,10 +1147,12 @@ i32); define @intrinsic_vle_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv64i8( %0, * %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s @@ -6,10 +7,12 @@ i64); define @intrinsic_vle_v_nxv1i64_nxv1i64(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1i64( * %0, i64 %1) @@ -24,10 +27,12 @@ i64); define @intrinsic_vle_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1i64( %0, * %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vle_v_nxv2i64_nxv2i64(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2i64( * %0, i64 %1) @@ -60,10 +67,12 @@ i64); define @intrinsic_vle_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2i64( %0, * %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vle_v_nxv4i64_nxv4i64(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4i64( * %0, i64 %1) @@ -96,10 +107,12 @@ i64); define @intrinsic_vle_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4i64( %0, * %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vle_v_nxv8i64_nxv8i64(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8i64( * %0, i64 %1) @@ -132,10 +147,12 @@ i64); define @intrinsic_vle_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8i64( %0, * %1, @@ -150,10 +167,12 @@ i64); define @intrinsic_vle_v_nxv1f64_nxv1f64(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1f64( * %0, i64 %1) @@ -168,10 +187,12 @@ i64); define @intrinsic_vle_mask_v_nxv1f64_nxv1f64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1f64( %0, * %1, @@ -186,10 +207,12 @@ i64); define @intrinsic_vle_v_nxv2f64_nxv2f64(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2f64( * %0, i64 %1) @@ -204,10 +227,12 @@ i64); define @intrinsic_vle_mask_v_nxv2f64_nxv2f64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2f64( %0, * %1, @@ -222,10 +247,12 @@ i64); define @intrinsic_vle_v_nxv4f64_nxv4f64(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4f64( * %0, i64 %1) @@ -240,10 +267,12 @@ i64); define @intrinsic_vle_mask_v_nxv4f64_nxv4f64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4f64( %0, * %1, @@ -258,10 +287,12 @@ i64); define @intrinsic_vle_v_nxv8f64_nxv8f64(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8f64( * %0, i64 %1) @@ -276,10 +307,12 @@ i64); define @intrinsic_vle_mask_v_nxv8f64_nxv8f64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vle64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vle64.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8f64( %0, * %1, @@ -294,10 +327,12 @@ i64); define @intrinsic_vle_v_nxv1i32_nxv1i32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1i32( * %0, i64 %1) @@ -312,10 +347,12 @@ i64); define @intrinsic_vle_mask_v_nxv1i32_nxv1i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1i32( %0, * %1, @@ -330,10 +367,12 @@ i64); define @intrinsic_vle_v_nxv2i32_nxv2i32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2i32( * %0, i64 %1) @@ -348,10 +387,12 @@ i64); define @intrinsic_vle_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2i32( %0, * %1, @@ -366,10 +407,12 @@ i64); define @intrinsic_vle_v_nxv4i32_nxv4i32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4i32( * %0, i64 %1) @@ -384,10 +427,12 @@ i64); define @intrinsic_vle_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4i32( %0, * %1, @@ -402,10 +447,12 @@ i64); define @intrinsic_vle_v_nxv8i32_nxv8i32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8i32( * %0, i64 %1) @@ -420,10 +467,12 @@ i64); define @intrinsic_vle_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8i32( %0, * %1, @@ -438,10 +487,12 @@ i64); define @intrinsic_vle_v_nxv16i32_nxv16i32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16i32( * %0, i64 %1) @@ -456,10 +507,12 @@ i64); define @intrinsic_vle_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16i32( %0, * %1, @@ -474,10 +527,12 @@ i64); define @intrinsic_vle_v_nxv1f32_nxv1f32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1f32( * %0, i64 %1) @@ -492,10 +547,12 @@ i64); define @intrinsic_vle_mask_v_nxv1f32_nxv1f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1f32( %0, * %1, @@ -510,10 +567,12 @@ i64); define @intrinsic_vle_v_nxv2f32_nxv2f32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2f32( * %0, i64 %1) @@ -528,10 +587,12 @@ i64); define @intrinsic_vle_mask_v_nxv2f32_nxv2f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2f32( %0, * %1, @@ -546,10 +607,12 @@ i64); define @intrinsic_vle_v_nxv4f32_nxv4f32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4f32( * %0, i64 %1) @@ -564,10 +627,12 @@ i64); define @intrinsic_vle_mask_v_nxv4f32_nxv4f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4f32( %0, * %1, @@ -582,10 +647,12 @@ i64); define @intrinsic_vle_v_nxv8f32_nxv8f32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8f32( * %0, i64 %1) @@ -600,10 +667,12 @@ i64); define @intrinsic_vle_mask_v_nxv8f32_nxv8f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8f32( %0, * %1, @@ -618,10 +687,12 @@ i64); define @intrinsic_vle_v_nxv16f32_nxv16f32(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16f32( * %0, i64 %1) @@ -636,10 +707,12 @@ i64); define @intrinsic_vle_mask_v_nxv16f32_nxv16f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vle32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vle32.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16f32( %0, * %1, @@ -654,10 +727,12 @@ i64); define @intrinsic_vle_v_nxv1i16_nxv1i16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1i16( * %0, i64 %1) @@ -672,10 +747,12 @@ i64); define @intrinsic_vle_mask_v_nxv1i16_nxv1i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1i16( %0, * %1, @@ -690,10 +767,12 @@ i64); define @intrinsic_vle_v_nxv2i16_nxv2i16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2i16( * %0, i64 %1) @@ -708,10 +787,12 @@ i64); define @intrinsic_vle_mask_v_nxv2i16_nxv2i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2i16( %0, * %1, @@ -726,10 +807,12 @@ i64); define @intrinsic_vle_v_nxv4i16_nxv4i16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4i16( * %0, i64 %1) @@ -744,10 +827,12 @@ i64); define @intrinsic_vle_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4i16( %0, * %1, @@ -762,10 +847,12 @@ i64); define @intrinsic_vle_v_nxv8i16_nxv8i16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8i16( * %0, i64 %1) @@ -780,10 +867,12 @@ i64); define @intrinsic_vle_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8i16( %0, * %1, @@ -798,10 +887,12 @@ i64); define @intrinsic_vle_v_nxv16i16_nxv16i16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16i16( * %0, i64 %1) @@ -816,10 +907,12 @@ i64); define @intrinsic_vle_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16i16( %0, * %1, @@ -834,10 +927,12 @@ i64); define @intrinsic_vle_v_nxv32i16_nxv32i16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv32i16( * %0, i64 %1) @@ -852,10 +947,12 @@ i64); define @intrinsic_vle_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv32i16( %0, * %1, @@ -870,10 +967,12 @@ i64); define @intrinsic_vle_v_nxv1f16_nxv1f16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1f16( * %0, i64 %1) @@ -888,10 +987,12 @@ i64); define @intrinsic_vle_mask_v_nxv1f16_nxv1f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1f16( %0, * %1, @@ -906,10 +1007,12 @@ i64); define @intrinsic_vle_v_nxv2f16_nxv2f16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2f16( * %0, i64 %1) @@ -924,10 +1027,12 @@ i64); define @intrinsic_vle_mask_v_nxv2f16_nxv2f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2f16( %0, * %1, @@ -942,10 +1047,12 @@ i64); define @intrinsic_vle_v_nxv4f16_nxv4f16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4f16( * %0, i64 %1) @@ -960,10 +1067,12 @@ i64); define @intrinsic_vle_mask_v_nxv4f16_nxv4f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4f16( %0, * %1, @@ -978,10 +1087,12 @@ i64); define @intrinsic_vle_v_nxv8f16_nxv8f16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8f16( * %0, i64 %1) @@ -996,10 +1107,12 @@ i64); define @intrinsic_vle_mask_v_nxv8f16_nxv8f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8f16( %0, * %1, @@ -1014,10 +1127,12 @@ i64); define @intrinsic_vle_v_nxv16f16_nxv16f16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16f16( * %0, i64 %1) @@ -1032,10 +1147,12 @@ i64); define @intrinsic_vle_mask_v_nxv16f16_nxv16f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16f16( %0, * %1, @@ -1050,10 +1167,12 @@ i64); define @intrinsic_vle_v_nxv32f16_nxv32f16(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv32f16( * %0, i64 %1) @@ -1068,10 +1187,12 @@ i64); define @intrinsic_vle_mask_v_nxv32f16_nxv32f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vle16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vle16.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv32f16( %0, * %1, @@ -1086,10 +1207,12 @@ i64); define @intrinsic_vle_v_nxv1i8_nxv1i8(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv1i8( * %0, i64 %1) @@ -1104,10 +1227,12 @@ i64); define @intrinsic_vle_mask_v_nxv1i8_nxv1i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv1i8( %0, * %1, @@ -1122,10 +1247,12 @@ i64); define @intrinsic_vle_v_nxv2i8_nxv2i8(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv2i8( * %0, i64 %1) @@ -1140,10 +1267,12 @@ i64); define @intrinsic_vle_mask_v_nxv2i8_nxv2i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv2i8( %0, * %1, @@ -1158,10 +1287,12 @@ i64); define @intrinsic_vle_v_nxv4i8_nxv4i8(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv4i8( * %0, i64 %1) @@ -1176,10 +1307,12 @@ i64); define @intrinsic_vle_mask_v_nxv4i8_nxv4i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv4i8( %0, * %1, @@ -1194,10 +1327,12 @@ i64); define @intrinsic_vle_v_nxv8i8_nxv8i8(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv8i8( * %0, i64 %1) @@ -1212,10 +1347,12 @@ i64); define @intrinsic_vle_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv8i8( %0, * %1, @@ -1230,10 +1367,12 @@ i64); define @intrinsic_vle_v_nxv16i8_nxv16i8(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv16i8( * %0, i64 %1) @@ -1248,10 +1387,12 @@ i64); define @intrinsic_vle_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv16i8( %0, * %1, @@ -1266,10 +1407,12 @@ i64); define @intrinsic_vle_v_nxv32i8_nxv32i8(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv32i8( * %0, i64 %1) @@ -1284,10 +1427,12 @@ i64); define @intrinsic_vle_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv32i8( %0, * %1, @@ -1302,10 +1447,12 @@ i64); define @intrinsic_vle_v_nxv64i8_nxv64i8(* %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0) %a = call @llvm.riscv.vle.nxv64i8( * %0, i64 %1) @@ -1320,10 +1467,12 @@ i64); define @intrinsic_vle_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vle_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vle8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vle_mask_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vle8.v {{v[0-9]+}}, (a0), v0.t %a = call @llvm.riscv.vle.mask.nxv64i8( %0, * %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1i32( @@ -29,7 +29,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1i32( @@ -49,7 +49,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2i32( @@ -69,7 +69,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2i32( @@ -89,7 +89,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4i32( @@ -109,7 +109,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4i32( @@ -129,7 +129,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8i32( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8i32( @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16i32( @@ -189,7 +189,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16i32( @@ -209,7 +209,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1f32( @@ -229,7 +229,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1f32( @@ -249,7 +249,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2f32( @@ -269,7 +269,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2f32( @@ -289,7 +289,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4f32( @@ -309,7 +309,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4f32( @@ -329,7 +329,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8f32( @@ -349,7 +349,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8f32( @@ -369,7 +369,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16f32( @@ -389,7 +389,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16f32( @@ -409,7 +409,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1i16( @@ -429,7 +429,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1i16( @@ -449,7 +449,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2i16( @@ -469,7 +469,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2i16( @@ -489,7 +489,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4i16( @@ -509,7 +509,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4i16( @@ -529,7 +529,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8i16( @@ -549,7 +549,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8i16( @@ -569,7 +569,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16i16( @@ -589,7 +589,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16i16( @@ -609,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv32i16( @@ -629,7 +629,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv32i16( @@ -649,7 +649,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1f16( @@ -669,7 +669,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1f16( @@ -689,7 +689,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2f16( @@ -709,7 +709,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2f16( @@ -729,7 +729,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4f16( @@ -749,7 +749,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4f16( @@ -769,7 +769,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8f16( @@ -789,7 +789,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8f16( @@ -809,7 +809,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16f16( @@ -829,7 +829,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16f16( @@ -849,7 +849,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv32f16( @@ -869,7 +869,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv32f16( @@ -889,7 +889,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1i8( @@ -909,7 +909,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1i8( @@ -929,7 +929,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2i8( @@ -949,7 +949,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2i8( @@ -969,7 +969,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4i8( @@ -989,7 +989,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4i8( @@ -1009,7 +1009,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8i8( @@ -1029,7 +1029,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8i8( @@ -1049,7 +1049,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16i8( @@ -1069,7 +1069,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16i8( @@ -1089,7 +1089,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv32i8( @@ -1109,7 +1109,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv32i8( @@ -1129,7 +1129,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv64i8( @@ -1149,7 +1149,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv64i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll @@ -9,7 +9,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vle64ff.v v16, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1i64( @@ -29,7 +29,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vle64ff.v v16, (a0), v0.t +; CHECK-NEXT: vle64ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1i64( @@ -49,7 +49,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vle64ff.v v16, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2i64( @@ -69,7 +69,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vle64ff.v v16, (a0), v0.t +; CHECK-NEXT: vle64ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2i64( @@ -89,7 +89,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vle64ff.v v16, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4i64( @@ -109,7 +109,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vle64ff.v v16, (a0), v0.t +; CHECK-NEXT: vle64ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4i64( @@ -129,7 +129,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vle64ff.v v16, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8i64( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu -; CHECK-NEXT: vle64ff.v v16, (a0), v0.t +; CHECK-NEXT: vle64ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8i64( @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vle64ff.v v16, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1f64( @@ -189,7 +189,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vle64ff.v v16, (a0), v0.t +; CHECK-NEXT: vle64ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1f64( @@ -209,7 +209,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vle64ff.v v16, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2f64( @@ -229,7 +229,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vle64ff.v v16, (a0), v0.t +; CHECK-NEXT: vle64ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2f64( @@ -249,7 +249,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vle64ff.v v16, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4f64( @@ -269,7 +269,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vle64ff.v v16, (a0), v0.t +; CHECK-NEXT: vle64ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4f64( @@ -289,7 +289,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vle64ff.v v16, (a0) +; CHECK-NEXT: vle64ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8f64( @@ -309,7 +309,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu -; CHECK-NEXT: vle64ff.v v16, (a0), v0.t +; CHECK-NEXT: vle64ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8f64( @@ -329,7 +329,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1i32( @@ -349,7 +349,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1i32( @@ -369,7 +369,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2i32( @@ -389,7 +389,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2i32( @@ -409,7 +409,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4i32( @@ -429,7 +429,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4i32( @@ -449,7 +449,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8i32( @@ -469,7 +469,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8i32( @@ -489,7 +489,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16i32( @@ -509,7 +509,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16i32( @@ -529,7 +529,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1f32( @@ -549,7 +549,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1f32( @@ -569,7 +569,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2f32( @@ -589,7 +589,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2f32( @@ -609,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4f32( @@ -629,7 +629,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4f32( @@ -649,7 +649,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8f32( @@ -669,7 +669,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8f32( @@ -689,7 +689,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vle32ff.v v16, (a0) +; CHECK-NEXT: vle32ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16f32( @@ -709,7 +709,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu -; CHECK-NEXT: vle32ff.v v16, (a0), v0.t +; CHECK-NEXT: vle32ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16f32( @@ -729,7 +729,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1i16( @@ -749,7 +749,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1i16( @@ -769,7 +769,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2i16( @@ -789,7 +789,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2i16( @@ -809,7 +809,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4i16( @@ -829,7 +829,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4i16( @@ -849,7 +849,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8i16( @@ -869,7 +869,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8i16( @@ -889,7 +889,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16i16( @@ -909,7 +909,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16i16( @@ -929,7 +929,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv32i16( @@ -949,7 +949,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv32i16( @@ -969,7 +969,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1f16( @@ -989,7 +989,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1f16( @@ -1009,7 +1009,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2f16( @@ -1029,7 +1029,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2f16( @@ -1049,7 +1049,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4f16( @@ -1069,7 +1069,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4f16( @@ -1089,7 +1089,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8f16( @@ -1109,7 +1109,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8f16( @@ -1129,7 +1129,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16f16( @@ -1149,7 +1149,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16f16( @@ -1169,7 +1169,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vle16ff.v v16, (a0) +; CHECK-NEXT: vle16ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv32f16( @@ -1189,7 +1189,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu -; CHECK-NEXT: vle16ff.v v16, (a0), v0.t +; CHECK-NEXT: vle16ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv32f16( @@ -1209,7 +1209,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv1i8( @@ -1229,7 +1229,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv1i8( @@ -1249,7 +1249,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv2i8( @@ -1269,7 +1269,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv2i8( @@ -1289,7 +1289,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv4i8( @@ -1309,7 +1309,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv4i8( @@ -1329,7 +1329,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv8i8( @@ -1349,7 +1349,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv8i8( @@ -1369,7 +1369,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv16i8( @@ -1389,7 +1389,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv16i8( @@ -1409,7 +1409,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv32i8( @@ -1429,7 +1429,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv32i8( @@ -1449,7 +1449,7 @@ ; CHECK-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vle8ff.v v16, (a0) +; CHECK-NEXT: vle8ff.v v8, (a0) ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.nxv64i8( @@ -1469,7 +1469,7 @@ ; CHECK-LABEL: intrinsic_vleff_mask_v_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu -; CHECK-NEXT: vle8ff.v v16, (a0), v0.t +; CHECK-NEXT: vle8ff.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vleff.mask.nxv64i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i8.nxv1i32( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i8.nxv1i32( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i8.nxv2i32( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i8.nxv2i32( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i8.nxv4i32( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i8.nxv4i32( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i8.nxv8i32( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i8.nxv8i32( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i8.nxv16i32( @@ -207,10 +207,8 @@ define @intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i8.nxv16i32( @@ -232,7 +230,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i16.nxv1i32( @@ -254,7 +252,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i16.nxv1i32( @@ -276,7 +274,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i16.nxv2i32( @@ -298,7 +296,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i16.nxv2i32( @@ -320,7 +318,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i16.nxv4i32( @@ -342,7 +340,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i16.nxv4i32( @@ -364,7 +362,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i16.nxv8i32( @@ -386,7 +384,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i16.nxv8i32( @@ -408,7 +406,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i16.nxv16i32( @@ -429,10 +427,8 @@ define @intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i16.nxv16i32( @@ -454,7 +450,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i32.nxv1i32( @@ -476,7 +472,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32( @@ -498,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i32.nxv2i32( @@ -520,7 +516,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i32.nxv2i32( @@ -542,7 +538,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i32.nxv4i32( @@ -564,7 +560,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i32.nxv4i32( @@ -586,7 +582,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i32.nxv8i32( @@ -608,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i32.nxv8i32( @@ -630,7 +626,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i32.nxv16i32( @@ -651,10 +647,8 @@ define @intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i32.nxv16i32( @@ -676,7 +670,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f16.nxv1i32( @@ -698,7 +692,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32( @@ -720,7 +714,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f16.nxv2i32( @@ -742,7 +736,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32( @@ -764,7 +758,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f16.nxv4i32( @@ -786,7 +780,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32( @@ -808,7 +802,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f16.nxv8i32( @@ -830,7 +824,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32( @@ -852,7 +846,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f16.nxv16i32( @@ -873,10 +867,8 @@ define @intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32( @@ -898,7 +890,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f32.nxv1i32( @@ -920,7 +912,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32( @@ -942,7 +934,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f32.nxv2i32( @@ -964,7 +956,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f32.nxv2i32( @@ -986,7 +978,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f32.nxv4i32( @@ -1008,7 +1000,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f32.nxv4i32( @@ -1030,7 +1022,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f32.nxv8i32( @@ -1052,7 +1044,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f32.nxv8i32( @@ -1074,7 +1066,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f32.nxv16i32( @@ -1095,10 +1087,8 @@ define @intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f32.nxv16i32( @@ -1120,7 +1110,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f64.nxv1i32( @@ -1142,7 +1132,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f64.nxv1i32( @@ -1164,7 +1154,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f64.nxv2i32( @@ -1186,7 +1176,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f64.nxv2i32( @@ -1208,7 +1198,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f64.nxv4i32( @@ -1230,7 +1220,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f64.nxv4i32( @@ -1252,7 +1242,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f64.nxv8i32( @@ -1273,10 +1263,8 @@ define @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f64.nxv8i32( @@ -1298,7 +1286,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i8.nxv1i16( @@ -1320,7 +1308,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i8.nxv1i16( @@ -1342,7 +1330,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i8.nxv2i16( @@ -1364,7 +1352,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i8.nxv2i16( @@ -1386,7 +1374,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i8.nxv4i16( @@ -1408,7 +1396,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i8.nxv4i16( @@ -1430,7 +1418,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i8.nxv8i16( @@ -1452,7 +1440,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i8.nxv8i16( @@ -1474,7 +1462,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i8.nxv16i16( @@ -1496,7 +1484,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i8.nxv16i16( @@ -1518,7 +1506,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32i8.nxv32i16( @@ -1539,10 +1527,8 @@ define @intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32i8.nxv32i16( @@ -1564,7 +1550,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i16.nxv1i16( @@ -1586,7 +1572,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i16.nxv1i16( @@ -1608,7 +1594,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i16.nxv2i16( @@ -1630,7 +1616,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i16.nxv2i16( @@ -1652,7 +1638,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i16.nxv4i16( @@ -1674,7 +1660,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i16.nxv4i16( @@ -1696,7 +1682,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i16.nxv8i16( @@ -1718,7 +1704,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i16.nxv8i16( @@ -1740,7 +1726,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i16.nxv16i16( @@ -1762,7 +1748,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i16.nxv16i16( @@ -1784,7 +1770,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32i16.nxv32i16( @@ -1805,10 +1791,8 @@ define @intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32i16.nxv32i16( @@ -1830,7 +1814,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i32.nxv1i16( @@ -1852,7 +1836,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16( @@ -1874,7 +1858,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i32.nxv2i16( @@ -1896,7 +1880,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i32.nxv2i16( @@ -1918,7 +1902,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i32.nxv4i16( @@ -1940,7 +1924,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i32.nxv4i16( @@ -1962,7 +1946,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i32.nxv8i16( @@ -1984,7 +1968,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i32.nxv8i16( @@ -2006,7 +1990,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i32.nxv16i16( @@ -2027,10 +2011,8 @@ define @intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i32.nxv16i16( @@ -2052,7 +2034,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f16.nxv1i16( @@ -2074,7 +2056,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16( @@ -2096,7 +2078,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f16.nxv2i16( @@ -2118,7 +2100,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16( @@ -2140,7 +2122,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f16.nxv4i16( @@ -2162,7 +2144,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16( @@ -2184,7 +2166,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f16.nxv8i16( @@ -2206,7 +2188,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16( @@ -2228,7 +2210,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f16.nxv16i16( @@ -2250,7 +2232,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16( @@ -2272,7 +2254,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32f16.nxv32i16( @@ -2293,10 +2275,8 @@ define @intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16( @@ -2318,7 +2298,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f32.nxv1i16( @@ -2340,7 +2320,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f32.nxv1i16( @@ -2362,7 +2342,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f32.nxv2i16( @@ -2384,7 +2364,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f32.nxv2i16( @@ -2406,7 +2386,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f32.nxv4i16( @@ -2428,7 +2408,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f32.nxv4i16( @@ -2450,7 +2430,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f32.nxv8i16( @@ -2472,7 +2452,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f32.nxv8i16( @@ -2494,7 +2474,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f32.nxv16i16( @@ -2515,10 +2495,8 @@ define @intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f32.nxv16i16( @@ -2540,7 +2518,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f64.nxv1i16( @@ -2562,7 +2540,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f64.nxv1i16( @@ -2584,7 +2562,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f64.nxv2i16( @@ -2606,7 +2584,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f64.nxv2i16( @@ -2628,7 +2606,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f64.nxv4i16( @@ -2650,7 +2628,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f64.nxv4i16( @@ -2672,7 +2650,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f64.nxv8i16( @@ -2693,10 +2671,8 @@ define @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f64.nxv8i16( @@ -2718,7 +2694,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i8.nxv1i8( @@ -2740,7 +2716,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i8.nxv1i8( @@ -2762,7 +2738,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i8.nxv2i8( @@ -2784,7 +2760,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i8.nxv2i8( @@ -2806,7 +2782,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i8.nxv4i8( @@ -2828,7 +2804,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i8.nxv4i8( @@ -2850,7 +2826,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i8.nxv8i8( @@ -2872,7 +2848,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i8.nxv8i8( @@ -2894,7 +2870,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i8.nxv16i8( @@ -2916,7 +2892,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i8.nxv16i8( @@ -2938,7 +2914,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32i8.nxv32i8( @@ -2960,7 +2936,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32i8.nxv32i8( @@ -2982,7 +2958,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv64i8.nxv64i8( @@ -3003,10 +2979,8 @@ define @intrinsic_vloxei_mask_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv64i8.nxv64i8( @@ -3028,7 +3002,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i16.nxv1i8( @@ -3050,7 +3024,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i16.nxv1i8( @@ -3072,7 +3046,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i16.nxv2i8( @@ -3094,7 +3068,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i16.nxv2i8( @@ -3116,7 +3090,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i16.nxv4i8( @@ -3138,7 +3112,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i16.nxv4i8( @@ -3160,7 +3134,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i16.nxv8i8( @@ -3182,7 +3156,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i16.nxv8i8( @@ -3204,7 +3178,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i16.nxv16i8( @@ -3226,7 +3200,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i16.nxv16i8( @@ -3248,7 +3222,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32i16.nxv32i8( @@ -3269,10 +3243,8 @@ define @intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32i16.nxv32i8( @@ -3294,7 +3266,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i32.nxv1i8( @@ -3316,7 +3288,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i32.nxv1i8( @@ -3338,7 +3310,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i32.nxv2i8( @@ -3360,7 +3332,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i32.nxv2i8( @@ -3382,7 +3354,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i32.nxv4i8( @@ -3404,7 +3376,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i32.nxv4i8( @@ -3426,7 +3398,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i32.nxv8i8( @@ -3448,7 +3420,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i32.nxv8i8( @@ -3470,7 +3442,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i32.nxv16i8( @@ -3491,10 +3463,8 @@ define @intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i32.nxv16i8( @@ -3516,7 +3486,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f16.nxv1i8( @@ -3538,7 +3508,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8( @@ -3560,7 +3530,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f16.nxv2i8( @@ -3582,7 +3552,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8( @@ -3604,7 +3574,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f16.nxv4i8( @@ -3626,7 +3596,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8( @@ -3648,7 +3618,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f16.nxv8i8( @@ -3670,7 +3640,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8( @@ -3692,7 +3662,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f16.nxv16i8( @@ -3714,7 +3684,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8( @@ -3736,7 +3706,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32f16.nxv32i8( @@ -3757,10 +3727,8 @@ define @intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8( @@ -3782,7 +3750,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f32.nxv1i8( @@ -3804,7 +3772,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f32.nxv1i8( @@ -3826,7 +3794,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f32.nxv2i8( @@ -3848,7 +3816,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f32.nxv2i8( @@ -3870,7 +3838,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f32.nxv4i8( @@ -3892,7 +3860,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f32.nxv4i8( @@ -3914,7 +3882,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f32.nxv8i8( @@ -3936,7 +3904,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f32.nxv8i8( @@ -3958,7 +3926,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f32.nxv16i8( @@ -3979,10 +3947,8 @@ define @intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f32.nxv16i8( @@ -4004,7 +3970,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f64.nxv1i8( @@ -4026,7 +3992,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f64.nxv1i8( @@ -4048,7 +4014,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f64.nxv2i8( @@ -4070,7 +4036,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f64.nxv2i8( @@ -4092,7 +4058,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f64.nxv4i8( @@ -4114,7 +4080,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f64.nxv4i8( @@ -4136,7 +4102,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f64.nxv8i8( @@ -4157,10 +4123,8 @@ define @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v25, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i8.nxv1i64( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i8.nxv1i64( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i8.nxv2i64( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i8.nxv2i64( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i8.nxv4i64( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i8.nxv4i64( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i8.nxv8i64( @@ -163,10 +163,8 @@ define @intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m1,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i8.nxv8i64( @@ -188,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i16.nxv1i64( @@ -210,7 +208,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i16.nxv1i64( @@ -232,7 +230,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i16.nxv2i64( @@ -254,7 +252,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i16.nxv2i64( @@ -276,7 +274,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i16.nxv4i64( @@ -298,7 +296,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i16.nxv4i64( @@ -320,7 +318,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i16.nxv8i64( @@ -341,10 +339,8 @@ define @intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i16.nxv8i64( @@ -366,7 +362,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i32.nxv1i64( @@ -388,7 +384,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i32.nxv1i64( @@ -410,7 +406,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i32.nxv2i64( @@ -432,7 +428,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i32.nxv2i64( @@ -454,7 +450,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i32.nxv4i64( @@ -476,7 +472,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64( @@ -498,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i32.nxv8i64( @@ -519,10 +515,8 @@ define @intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i32.nxv8i64( @@ -544,7 +538,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i64.nxv1i64( @@ -566,7 +560,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i64.nxv1i64( @@ -588,7 +582,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i64.nxv2i64( @@ -610,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i64.nxv2i64( @@ -632,7 +626,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i64.nxv4i64( @@ -654,7 +648,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i64.nxv4i64( @@ -676,7 +670,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i64.nxv8i64( @@ -697,10 +691,8 @@ define @intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i64.nxv8i64( @@ -722,7 +714,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f16.nxv1i64( @@ -744,7 +736,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f16.nxv1i64( @@ -766,7 +758,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f16.nxv2i64( @@ -788,7 +780,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f16.nxv2i64( @@ -810,7 +802,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f16.nxv4i64( @@ -832,7 +824,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f16.nxv4i64( @@ -854,7 +846,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f16.nxv8i64( @@ -875,10 +867,8 @@ define @intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f16.nxv8i64( @@ -900,7 +890,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f32.nxv1i64( @@ -922,7 +912,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f32.nxv1i64( @@ -944,7 +934,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f32.nxv2i64( @@ -966,7 +956,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f32.nxv2i64( @@ -988,7 +978,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f32.nxv4i64( @@ -1010,7 +1000,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f32.nxv4i64( @@ -1032,7 +1022,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f32.nxv8i64( @@ -1053,10 +1043,8 @@ define @intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f32.nxv8i64( @@ -1078,7 +1066,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f64.nxv1i64( @@ -1100,7 +1088,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f64.nxv1i64( @@ -1122,7 +1110,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f64.nxv2i64( @@ -1144,7 +1132,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f64.nxv2i64( @@ -1166,7 +1154,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f64.nxv4i64( @@ -1188,7 +1176,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f64.nxv4i64( @@ -1210,7 +1198,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v16 +; CHECK-NEXT: vloxei64.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f64.nxv8i64( @@ -1231,10 +1219,8 @@ define @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f64.nxv8i64( @@ -1256,7 +1242,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i8.nxv1i32( @@ -1278,7 +1264,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i8.nxv1i32( @@ -1300,7 +1286,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i8.nxv2i32( @@ -1322,7 +1308,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i8.nxv2i32( @@ -1344,7 +1330,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i8.nxv4i32( @@ -1366,7 +1352,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i8.nxv4i32( @@ -1388,7 +1374,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i8.nxv8i32( @@ -1410,7 +1396,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i8.nxv8i32( @@ -1432,7 +1418,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i8.nxv16i32( @@ -1453,10 +1439,8 @@ define @intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i8.nxv16i32( @@ -1478,7 +1462,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i16.nxv1i32( @@ -1500,7 +1484,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i16.nxv1i32( @@ -1522,7 +1506,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i16.nxv2i32( @@ -1544,7 +1528,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i16.nxv2i32( @@ -1566,7 +1550,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i16.nxv4i32( @@ -1588,7 +1572,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i16.nxv4i32( @@ -1610,7 +1594,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i16.nxv8i32( @@ -1632,7 +1616,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i16.nxv8i32( @@ -1654,7 +1638,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i16.nxv16i32( @@ -1675,10 +1659,8 @@ define @intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i16.nxv16i32( @@ -1700,7 +1682,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i32.nxv1i32( @@ -1722,7 +1704,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i32.nxv1i32( @@ -1744,7 +1726,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i32.nxv2i32( @@ -1766,7 +1748,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i32.nxv2i32( @@ -1788,7 +1770,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i32.nxv4i32( @@ -1810,7 +1792,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i32.nxv4i32( @@ -1832,7 +1814,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i32.nxv8i32( @@ -1854,7 +1836,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i32.nxv8i32( @@ -1876,7 +1858,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i32.nxv16i32( @@ -1897,10 +1879,8 @@ define @intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i32.nxv16i32( @@ -1922,7 +1902,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i64.nxv1i32( @@ -1944,7 +1924,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32( @@ -1966,7 +1946,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i64.nxv2i32( @@ -1988,7 +1968,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i64.nxv2i32( @@ -2010,7 +1990,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i64.nxv4i32( @@ -2032,7 +2012,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i64.nxv4i32( @@ -2054,7 +2034,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i64.nxv8i32( @@ -2075,10 +2055,8 @@ define @intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i64.nxv8i32( @@ -2100,7 +2078,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f16.nxv1i32( @@ -2122,7 +2100,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f16.nxv1i32( @@ -2144,7 +2122,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f16.nxv2i32( @@ -2166,7 +2144,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f16.nxv2i32( @@ -2188,7 +2166,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f16.nxv4i32( @@ -2210,7 +2188,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f16.nxv4i32( @@ -2232,7 +2210,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f16.nxv8i32( @@ -2254,7 +2232,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f16.nxv8i32( @@ -2276,7 +2254,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f16.nxv16i32( @@ -2297,10 +2275,8 @@ define @intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f16.nxv16i32( @@ -2322,7 +2298,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f32.nxv1i32( @@ -2344,7 +2320,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f32.nxv1i32( @@ -2366,7 +2342,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f32.nxv2i32( @@ -2388,7 +2364,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f32.nxv2i32( @@ -2410,7 +2386,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f32.nxv4i32( @@ -2432,7 +2408,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f32.nxv4i32( @@ -2454,7 +2430,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f32.nxv8i32( @@ -2476,7 +2452,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f32.nxv8i32( @@ -2498,7 +2474,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f32.nxv16i32( @@ -2519,10 +2495,8 @@ define @intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f32.nxv16i32( @@ -2544,7 +2518,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f64.nxv1i32( @@ -2566,7 +2540,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f64.nxv1i32( @@ -2588,7 +2562,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f64.nxv2i32( @@ -2610,7 +2584,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f64.nxv2i32( @@ -2632,7 +2606,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f64.nxv4i32( @@ -2654,7 +2628,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f64.nxv4i32( @@ -2676,7 +2650,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v16 +; CHECK-NEXT: vloxei32.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f64.nxv8i32( @@ -2697,10 +2671,8 @@ define @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei32.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f64.nxv8i32( @@ -2722,7 +2694,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i8.nxv1i16( @@ -2744,7 +2716,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i8.nxv1i16( @@ -2766,7 +2738,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i8.nxv2i16( @@ -2788,7 +2760,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i8.nxv2i16( @@ -2810,7 +2782,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i8.nxv4i16( @@ -2832,7 +2804,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i8.nxv4i16( @@ -2854,7 +2826,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i8.nxv8i16( @@ -2876,7 +2848,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i8.nxv8i16( @@ -2898,7 +2870,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i8.nxv16i16( @@ -2920,7 +2892,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i8.nxv16i16( @@ -2942,7 +2914,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32i8.nxv32i16( @@ -2963,10 +2935,8 @@ define @intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32i8.nxv32i16( @@ -2988,7 +2958,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i16.nxv1i16( @@ -3010,7 +2980,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i16.nxv1i16( @@ -3032,7 +3002,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i16.nxv2i16( @@ -3054,7 +3024,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i16.nxv2i16( @@ -3076,7 +3046,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i16.nxv4i16( @@ -3098,7 +3068,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i16.nxv4i16( @@ -3120,7 +3090,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i16.nxv8i16( @@ -3142,7 +3112,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i16.nxv8i16( @@ -3164,7 +3134,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i16.nxv16i16( @@ -3186,7 +3156,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i16.nxv16i16( @@ -3208,7 +3178,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32i16.nxv32i16( @@ -3229,10 +3199,8 @@ define @intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32i16.nxv32i16( @@ -3254,7 +3222,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i32.nxv1i16( @@ -3276,7 +3244,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16( @@ -3298,7 +3266,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i32.nxv2i16( @@ -3320,7 +3288,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i32.nxv2i16( @@ -3342,7 +3310,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i32.nxv4i16( @@ -3364,7 +3332,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i32.nxv4i16( @@ -3386,7 +3354,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i32.nxv8i16( @@ -3408,7 +3376,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i32.nxv8i16( @@ -3430,7 +3398,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i32.nxv16i16( @@ -3451,10 +3419,8 @@ define @intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i32.nxv16i16( @@ -3476,7 +3442,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i64.nxv1i16( @@ -3498,7 +3464,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i64.nxv1i16( @@ -3520,7 +3486,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i64.nxv2i16( @@ -3542,7 +3508,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i64.nxv2i16( @@ -3564,7 +3530,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i64.nxv4i16( @@ -3586,7 +3552,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i64.nxv4i16( @@ -3608,7 +3574,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i64.nxv8i16( @@ -3629,10 +3595,8 @@ define @intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i64.nxv8i16( @@ -3654,7 +3618,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f16.nxv1i16( @@ -3676,7 +3640,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f16.nxv1i16( @@ -3698,7 +3662,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f16.nxv2i16( @@ -3720,7 +3684,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f16.nxv2i16( @@ -3742,7 +3706,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f16.nxv4i16( @@ -3764,7 +3728,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f16.nxv4i16( @@ -3786,7 +3750,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f16.nxv8i16( @@ -3808,7 +3772,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f16.nxv8i16( @@ -3830,7 +3794,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f16.nxv16i16( @@ -3852,7 +3816,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f16.nxv16i16( @@ -3874,7 +3838,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32f16.nxv32i16( @@ -3895,10 +3859,8 @@ define @intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32f16.nxv32i16( @@ -3920,7 +3882,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f32.nxv1i16( @@ -3942,7 +3904,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f32.nxv1i16( @@ -3964,7 +3926,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f32.nxv2i16( @@ -3986,7 +3948,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f32.nxv2i16( @@ -4008,7 +3970,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f32.nxv4i16( @@ -4030,7 +3992,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f32.nxv4i16( @@ -4052,7 +4014,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f32.nxv8i16( @@ -4074,7 +4036,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f32.nxv8i16( @@ -4096,7 +4058,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f32.nxv16i16( @@ -4117,10 +4079,8 @@ define @intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f32.nxv16i16( @@ -4142,7 +4102,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f64.nxv1i16( @@ -4164,7 +4124,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f64.nxv1i16( @@ -4186,7 +4146,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f64.nxv2i16( @@ -4208,7 +4168,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f64.nxv2i16( @@ -4230,7 +4190,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f64.nxv4i16( @@ -4252,7 +4212,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f64.nxv4i16( @@ -4274,7 +4234,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v16 +; CHECK-NEXT: vloxei16.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f64.nxv8i16( @@ -4295,10 +4255,8 @@ define @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei16.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f64.nxv8i16( @@ -4320,7 +4278,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i8.nxv1i8( @@ -4342,7 +4300,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i8.nxv1i8( @@ -4364,7 +4322,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i8.nxv2i8( @@ -4386,7 +4344,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i8.nxv2i8( @@ -4408,7 +4366,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i8.nxv4i8( @@ -4430,7 +4388,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i8.nxv4i8( @@ -4452,7 +4410,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i8.nxv8i8( @@ -4474,7 +4432,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i8.nxv8i8( @@ -4496,7 +4454,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i8.nxv16i8( @@ -4518,7 +4476,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i8.nxv16i8( @@ -4540,7 +4498,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32i8.nxv32i8( @@ -4562,7 +4520,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32i8.nxv32i8( @@ -4584,7 +4542,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv64i8.nxv64i8( @@ -4605,10 +4563,8 @@ define @intrinsic_vloxei_mask_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv64i8.nxv64i8( @@ -4630,7 +4586,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i16.nxv1i8( @@ -4652,7 +4608,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i16.nxv1i8( @@ -4674,7 +4630,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i16.nxv2i8( @@ -4696,7 +4652,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i16.nxv2i8( @@ -4718,7 +4674,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i16.nxv4i8( @@ -4740,7 +4696,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i16.nxv4i8( @@ -4762,7 +4718,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i16.nxv8i8( @@ -4784,7 +4740,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i16.nxv8i8( @@ -4806,7 +4762,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i16.nxv16i8( @@ -4828,7 +4784,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i16.nxv16i8( @@ -4850,7 +4806,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32i16.nxv32i8( @@ -4871,10 +4827,8 @@ define @intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32i16.nxv32i8( @@ -4896,7 +4850,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i32.nxv1i8( @@ -4918,7 +4872,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i32.nxv1i8( @@ -4940,7 +4894,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i32.nxv2i8( @@ -4962,7 +4916,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i32.nxv2i8( @@ -4984,7 +4938,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i32.nxv4i8( @@ -5006,7 +4960,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i32.nxv4i8( @@ -5028,7 +4982,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i32.nxv8i8( @@ -5050,7 +5004,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i32.nxv8i8( @@ -5072,7 +5026,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16i32.nxv16i8( @@ -5093,10 +5047,8 @@ define @intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16i32.nxv16i8( @@ -5118,7 +5070,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1i64.nxv1i8( @@ -5140,7 +5092,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1i64.nxv1i8( @@ -5162,7 +5114,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2i64.nxv2i8( @@ -5184,7 +5136,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2i64.nxv2i8( @@ -5206,7 +5158,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4i64.nxv4i8( @@ -5228,7 +5180,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4i64.nxv4i8( @@ -5250,7 +5202,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8i64.nxv8i8( @@ -5271,10 +5223,8 @@ define @intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v25, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8i64.nxv8i8( @@ -5296,7 +5246,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f16.nxv1i8( @@ -5318,7 +5268,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f16.nxv1i8( @@ -5340,7 +5290,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f16.nxv2i8( @@ -5362,7 +5312,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f16.nxv2i8( @@ -5384,7 +5334,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f16.nxv4i8( @@ -5406,7 +5356,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f16.nxv4i8( @@ -5428,7 +5378,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f16.nxv8i8( @@ -5450,7 +5400,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f16.nxv8i8( @@ -5472,7 +5422,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f16.nxv16i8( @@ -5494,7 +5444,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f16.nxv16i8( @@ -5516,7 +5466,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv32f16.nxv32i8( @@ -5537,10 +5487,8 @@ define @intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv32f16.nxv32i8( @@ -5562,7 +5510,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f32.nxv1i8( @@ -5584,7 +5532,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f32.nxv1i8( @@ -5606,7 +5554,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f32.nxv2i8( @@ -5628,7 +5576,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f32.nxv2i8( @@ -5650,7 +5598,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f32.nxv4i8( @@ -5672,7 +5620,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f32.nxv4i8( @@ -5694,7 +5642,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f32.nxv8i8( @@ -5716,7 +5664,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f32.nxv8i8( @@ -5738,7 +5686,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv16f32.nxv16i8( @@ -5759,10 +5707,8 @@ define @intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv16f32.nxv16i8( @@ -5784,7 +5730,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv1f64.nxv1i8( @@ -5806,7 +5752,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv1f64.nxv1i8( @@ -5828,7 +5774,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv2f64.nxv2i8( @@ -5850,7 +5796,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv2f64.nxv2i8( @@ -5872,7 +5818,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv4f64.nxv4i8( @@ -5894,7 +5840,7 @@ ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vloxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv4f64.nxv4i8( @@ -5916,7 +5862,7 @@ ; CHECK-LABEL: intrinsic_vloxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v16 +; CHECK-NEXT: vloxei8.v v8, (a0), v8 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.nxv8f64.nxv8i8( @@ -5937,10 +5883,8 @@ define @intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vloxei_mask_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,tu,mu -; CHECK-NEXT: vloxei8.v v16, (a0), v25, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vloxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vloxei.mask.nxv8f64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vlse.nxv1i32( @@ -6,10 +7,12 @@ i32); define @intrinsic_vlse_v_nxv1i32_nxv1i32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1i32( * %0, i32 %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vlse_mask_v_nxv1i32_nxv1i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1i32( %0, * %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vlse_v_nxv2i32_nxv2i32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2i32( * %0, i32 %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vlse_mask_v_nxv2i32_nxv2i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2i32( %0, * %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vlse_v_nxv4i32_nxv4i32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4i32( * %0, i32 %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vlse_mask_v_nxv4i32_nxv4i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4i32( %0, * %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vlse_v_nxv8i32_nxv8i32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8i32( * %0, i32 %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vlse_mask_v_nxv8i32_nxv8i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8i32( %0, * %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vlse_v_nxv16i32_nxv16i32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16i32( * %0, i32 %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vlse_mask_v_nxv16i32_nxv16i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16i32( %0, * %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vlse_v_nxv1f32_nxv1f32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1f32( * %0, i32 %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vlse_mask_v_nxv1f32_nxv1f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1f32( %0, * %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vlse_v_nxv2f32_nxv2f32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2f32( * %0, i32 %1, @@ -266,10 +293,12 @@ i32); define @intrinsic_vlse_mask_v_nxv2f32_nxv2f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2f32( %0, * %1, @@ -286,10 +315,12 @@ i32); define @intrinsic_vlse_v_nxv4f32_nxv4f32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4f32( * %0, i32 %1, @@ -306,10 +337,12 @@ i32); define @intrinsic_vlse_mask_v_nxv4f32_nxv4f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4f32( %0, * %1, @@ -326,10 +359,12 @@ i32); define @intrinsic_vlse_v_nxv8f32_nxv8f32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8f32( * %0, i32 %1, @@ -346,10 +381,12 @@ i32); define @intrinsic_vlse_mask_v_nxv8f32_nxv8f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8f32( %0, * %1, @@ -366,10 +403,12 @@ i32); define @intrinsic_vlse_v_nxv16f32_nxv16f32(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16f32( * %0, i32 %1, @@ -386,10 +425,12 @@ i32); define @intrinsic_vlse_mask_v_nxv16f32_nxv16f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16f32( %0, * %1, @@ -406,10 +447,12 @@ i32); define @intrinsic_vlse_v_nxv1i16_nxv1i16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1i16( * %0, i32 %1, @@ -426,10 +469,12 @@ i32); define @intrinsic_vlse_mask_v_nxv1i16_nxv1i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1i16( %0, * %1, @@ -446,10 +491,12 @@ i32); define @intrinsic_vlse_v_nxv2i16_nxv2i16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2i16( * %0, i32 %1, @@ -466,10 +513,12 @@ i32); define @intrinsic_vlse_mask_v_nxv2i16_nxv2i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2i16( %0, * %1, @@ -486,10 +535,12 @@ i32); define @intrinsic_vlse_v_nxv4i16_nxv4i16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4i16( * %0, i32 %1, @@ -506,10 +557,12 @@ i32); define @intrinsic_vlse_mask_v_nxv4i16_nxv4i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4i16( %0, * %1, @@ -526,10 +579,12 @@ i32); define @intrinsic_vlse_v_nxv8i16_nxv8i16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8i16( * %0, i32 %1, @@ -546,10 +601,12 @@ i32); define @intrinsic_vlse_mask_v_nxv8i16_nxv8i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8i16( %0, * %1, @@ -566,10 +623,12 @@ i32); define @intrinsic_vlse_v_nxv16i16_nxv16i16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16i16( * %0, i32 %1, @@ -586,10 +645,12 @@ i32); define @intrinsic_vlse_mask_v_nxv16i16_nxv16i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16i16( %0, * %1, @@ -606,10 +667,12 @@ i32); define @intrinsic_vlse_v_nxv32i16_nxv32i16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv32i16( * %0, i32 %1, @@ -626,10 +689,12 @@ i32); define @intrinsic_vlse_mask_v_nxv32i16_nxv32i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv32i16( %0, * %1, @@ -646,10 +711,12 @@ i32); define @intrinsic_vlse_v_nxv1f16_nxv1f16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1f16( * %0, i32 %1, @@ -666,10 +733,12 @@ i32); define @intrinsic_vlse_mask_v_nxv1f16_nxv1f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1f16( %0, * %1, @@ -686,10 +755,12 @@ i32); define @intrinsic_vlse_v_nxv2f16_nxv2f16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2f16( * %0, i32 %1, @@ -706,10 +777,12 @@ i32); define @intrinsic_vlse_mask_v_nxv2f16_nxv2f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2f16( %0, * %1, @@ -726,10 +799,12 @@ i32); define @intrinsic_vlse_v_nxv4f16_nxv4f16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4f16( * %0, i32 %1, @@ -746,10 +821,12 @@ i32); define @intrinsic_vlse_mask_v_nxv4f16_nxv4f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4f16( %0, * %1, @@ -766,10 +843,12 @@ i32); define @intrinsic_vlse_v_nxv8f16_nxv8f16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8f16( * %0, i32 %1, @@ -786,10 +865,12 @@ i32); define @intrinsic_vlse_mask_v_nxv8f16_nxv8f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8f16( %0, * %1, @@ -806,10 +887,12 @@ i32); define @intrinsic_vlse_v_nxv16f16_nxv16f16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16f16( * %0, i32 %1, @@ -826,10 +909,12 @@ i32); define @intrinsic_vlse_mask_v_nxv16f16_nxv16f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16f16( %0, * %1, @@ -846,10 +931,12 @@ i32); define @intrinsic_vlse_v_nxv32f16_nxv32f16(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv32f16( * %0, i32 %1, @@ -866,10 +953,12 @@ i32); define @intrinsic_vlse_mask_v_nxv32f16_nxv32f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv32f16( %0, * %1, @@ -886,10 +975,12 @@ i32); define @intrinsic_vlse_v_nxv1i8_nxv1i8(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf8,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1i8( * %0, i32 %1, @@ -906,10 +997,12 @@ i32); define @intrinsic_vlse_mask_v_nxv1i8_nxv1i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf8,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1i8( %0, * %1, @@ -926,10 +1019,12 @@ i32); define @intrinsic_vlse_v_nxv2i8_nxv2i8(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf4,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2i8( * %0, i32 %1, @@ -946,10 +1041,12 @@ i32); define @intrinsic_vlse_mask_v_nxv2i8_nxv2i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf4,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2i8( %0, * %1, @@ -966,10 +1063,12 @@ i32); define @intrinsic_vlse_v_nxv4i8_nxv4i8(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf2,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4i8( * %0, i32 %1, @@ -986,10 +1085,12 @@ i32); define @intrinsic_vlse_mask_v_nxv4i8_nxv4i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf2,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4i8( %0, * %1, @@ -1006,10 +1107,12 @@ i32); define @intrinsic_vlse_v_nxv8i8_nxv8i8(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a2, e8,m1,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8i8( * %0, i32 %1, @@ -1026,10 +1129,12 @@ i32); define @intrinsic_vlse_mask_v_nxv8i8_nxv8i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a2, e8,m1,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8i8( %0, * %1, @@ -1046,10 +1151,12 @@ i32); define @intrinsic_vlse_v_nxv16i8_nxv16i8(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a2, e8,m2,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16i8( * %0, i32 %1, @@ -1066,10 +1173,12 @@ i32); define @intrinsic_vlse_mask_v_nxv16i8_nxv16i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m2,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a2, e8,m2,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16i8( %0, * %1, @@ -1086,10 +1195,12 @@ i32); define @intrinsic_vlse_v_nxv32i8_nxv32i8(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a2, e8,m4,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv32i8( * %0, i32 %1, @@ -1106,10 +1217,12 @@ i32); define @intrinsic_vlse_mask_v_nxv32i8_nxv32i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m4,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a2, e8,m4,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv32i8( %0, * %1, @@ -1126,10 +1239,12 @@ i32); define @intrinsic_vlse_v_nxv64i8_nxv64i8(* %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a2, e8,m8,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv64i8( * %0, i32 %1, @@ -1146,10 +1261,12 @@ i32); define @intrinsic_vlse_mask_v_nxv64i8_nxv64i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m8,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a2, e8,m8,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv64i8( %0, * %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vlse.nxv1i64( @@ -6,10 +7,12 @@ i64); define @intrinsic_vlse_v_nxv1i64_nxv1i64(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, a2, e64,m1,ta,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1i64( * %0, i64 %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vlse_mask_v_nxv1i64_nxv1i64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, a2, e64,m1,tu,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1i64( %0, * %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vlse_v_nxv2i64_nxv2i64(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, a2, e64,m2,ta,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2i64( * %0, i64 %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vlse_mask_v_nxv2i64_nxv2i64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, a2, e64,m2,tu,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2i64( %0, * %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vlse_v_nxv4i64_nxv4i64(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, a2, e64,m4,ta,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4i64( * %0, i64 %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vlse_mask_v_nxv4i64_nxv4i64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,tu,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, a2, e64,m4,tu,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4i64( %0, * %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vlse_v_nxv8i64_nxv8i64(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, a2, e64,m8,ta,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8i64( * %0, i64 %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vlse_mask_v_nxv8i64_nxv8i64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,tu,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, a2, e64,m8,tu,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8i64( %0, * %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vlse_v_nxv1f64_nxv1f64(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, a2, e64,m1,ta,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1f64( * %0, i64 %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vlse_mask_v_nxv1f64_nxv1f64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, a2, e64,m1,tu,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1f64( %0, * %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vlse_v_nxv2f64_nxv2f64(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, a2, e64,m2,ta,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2f64( * %0, i64 %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vlse_mask_v_nxv2f64_nxv2f64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, a2, e64,m2,tu,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2f64( %0, * %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vlse_v_nxv4f64_nxv4f64(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, a2, e64,m4,ta,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4f64( * %0, i64 %1, @@ -266,10 +293,12 @@ i64); define @intrinsic_vlse_mask_v_nxv4f64_nxv4f64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,tu,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, a2, e64,m4,tu,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4f64( %0, * %1, @@ -286,10 +315,12 @@ i64); define @intrinsic_vlse_v_nxv8f64_nxv8f64(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, a2, e64,m8,ta,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8f64( * %0, i64 %1, @@ -306,10 +337,12 @@ i64); define @intrinsic_vlse_mask_v_nxv8f64_nxv8f64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,tu,mu +; CHECK-NEXT: vlse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, a2, e64,m8,tu,mu -; CHECK: vlse64.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8f64( %0, * %1, @@ -326,10 +359,12 @@ i64); define @intrinsic_vlse_v_nxv1i32_nxv1i32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1i32( * %0, i64 %1, @@ -346,10 +381,12 @@ i64); define @intrinsic_vlse_mask_v_nxv1i32_nxv1i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1i32( %0, * %1, @@ -366,10 +403,12 @@ i64); define @intrinsic_vlse_v_nxv2i32_nxv2i32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2i32( * %0, i64 %1, @@ -386,10 +425,12 @@ i64); define @intrinsic_vlse_mask_v_nxv2i32_nxv2i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2i32( %0, * %1, @@ -406,10 +447,12 @@ i64); define @intrinsic_vlse_v_nxv4i32_nxv4i32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4i32( * %0, i64 %1, @@ -426,10 +469,12 @@ i64); define @intrinsic_vlse_mask_v_nxv4i32_nxv4i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4i32( %0, * %1, @@ -446,10 +491,12 @@ i64); define @intrinsic_vlse_v_nxv8i32_nxv8i32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8i32( * %0, i64 %1, @@ -466,10 +513,12 @@ i64); define @intrinsic_vlse_mask_v_nxv8i32_nxv8i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8i32( %0, * %1, @@ -486,10 +535,12 @@ i64); define @intrinsic_vlse_v_nxv16i32_nxv16i32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16i32( * %0, i64 %1, @@ -506,10 +557,12 @@ i64); define @intrinsic_vlse_mask_v_nxv16i32_nxv16i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16i32( %0, * %1, @@ -526,10 +579,12 @@ i64); define @intrinsic_vlse_v_nxv1f32_nxv1f32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1f32( * %0, i64 %1, @@ -546,10 +601,12 @@ i64); define @intrinsic_vlse_mask_v_nxv1f32_nxv1f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1f32( %0, * %1, @@ -566,10 +623,12 @@ i64); define @intrinsic_vlse_v_nxv2f32_nxv2f32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2f32( * %0, i64 %1, @@ -586,10 +645,12 @@ i64); define @intrinsic_vlse_mask_v_nxv2f32_nxv2f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2f32( %0, * %1, @@ -606,10 +667,12 @@ i64); define @intrinsic_vlse_v_nxv4f32_nxv4f32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4f32( * %0, i64 %1, @@ -626,10 +689,12 @@ i64); define @intrinsic_vlse_mask_v_nxv4f32_nxv4f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4f32( %0, * %1, @@ -646,10 +711,12 @@ i64); define @intrinsic_vlse_v_nxv8f32_nxv8f32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8f32( * %0, i64 %1, @@ -666,10 +733,12 @@ i64); define @intrinsic_vlse_mask_v_nxv8f32_nxv8f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8f32( %0, * %1, @@ -686,10 +755,12 @@ i64); define @intrinsic_vlse_v_nxv16f32_nxv16f32(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16f32( * %0, i64 %1, @@ -706,10 +777,12 @@ i64); define @intrinsic_vlse_mask_v_nxv16f32_nxv16f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,tu,mu +; CHECK-NEXT: vlse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,tu,mu -; CHECK: vlse32.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16f32( %0, * %1, @@ -726,10 +799,12 @@ i64); define @intrinsic_vlse_v_nxv1i16_nxv1i16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1i16( * %0, i64 %1, @@ -746,10 +821,12 @@ i64); define @intrinsic_vlse_mask_v_nxv1i16_nxv1i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1i16( %0, * %1, @@ -766,10 +843,12 @@ i64); define @intrinsic_vlse_v_nxv2i16_nxv2i16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2i16( * %0, i64 %1, @@ -786,10 +865,12 @@ i64); define @intrinsic_vlse_mask_v_nxv2i16_nxv2i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2i16( %0, * %1, @@ -806,10 +887,12 @@ i64); define @intrinsic_vlse_v_nxv4i16_nxv4i16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4i16( * %0, i64 %1, @@ -826,10 +909,12 @@ i64); define @intrinsic_vlse_mask_v_nxv4i16_nxv4i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4i16( %0, * %1, @@ -846,10 +931,12 @@ i64); define @intrinsic_vlse_v_nxv8i16_nxv8i16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8i16( * %0, i64 %1, @@ -866,10 +953,12 @@ i64); define @intrinsic_vlse_mask_v_nxv8i16_nxv8i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8i16( %0, * %1, @@ -886,10 +975,12 @@ i64); define @intrinsic_vlse_v_nxv16i16_nxv16i16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16i16( * %0, i64 %1, @@ -906,10 +997,12 @@ i64); define @intrinsic_vlse_mask_v_nxv16i16_nxv16i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16i16( %0, * %1, @@ -926,10 +1019,12 @@ i64); define @intrinsic_vlse_v_nxv32i16_nxv32i16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv32i16( * %0, i64 %1, @@ -946,10 +1041,12 @@ i64); define @intrinsic_vlse_mask_v_nxv32i16_nxv32i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv32i16( %0, * %1, @@ -966,10 +1063,12 @@ i64); define @intrinsic_vlse_v_nxv1f16_nxv1f16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1f16( * %0, i64 %1, @@ -986,10 +1085,12 @@ i64); define @intrinsic_vlse_mask_v_nxv1f16_nxv1f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1f16( %0, * %1, @@ -1006,10 +1107,12 @@ i64); define @intrinsic_vlse_v_nxv2f16_nxv2f16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2f16( * %0, i64 %1, @@ -1026,10 +1129,12 @@ i64); define @intrinsic_vlse_mask_v_nxv2f16_nxv2f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2f16( %0, * %1, @@ -1046,10 +1151,12 @@ i64); define @intrinsic_vlse_v_nxv4f16_nxv4f16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4f16( * %0, i64 %1, @@ -1066,10 +1173,12 @@ i64); define @intrinsic_vlse_mask_v_nxv4f16_nxv4f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4f16( %0, * %1, @@ -1086,10 +1195,12 @@ i64); define @intrinsic_vlse_v_nxv8f16_nxv8f16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8f16( * %0, i64 %1, @@ -1106,10 +1217,12 @@ i64); define @intrinsic_vlse_mask_v_nxv8f16_nxv8f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8f16( %0, * %1, @@ -1126,10 +1239,12 @@ i64); define @intrinsic_vlse_v_nxv16f16_nxv16f16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16f16( * %0, i64 %1, @@ -1146,10 +1261,12 @@ i64); define @intrinsic_vlse_mask_v_nxv16f16_nxv16f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16f16( %0, * %1, @@ -1166,10 +1283,12 @@ i64); define @intrinsic_vlse_v_nxv32f16_nxv32f16(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv32f16( * %0, i64 %1, @@ -1186,10 +1305,12 @@ i64); define @intrinsic_vlse_mask_v_nxv32f16_nxv32f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,tu,mu +; CHECK-NEXT: vlse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,tu,mu -; CHECK: vlse16.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv32f16( %0, * %1, @@ -1206,10 +1327,12 @@ i64); define @intrinsic_vlse_v_nxv1i8_nxv1i8(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf8,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv1i8( * %0, i64 %1, @@ -1226,10 +1349,12 @@ i64); define @intrinsic_vlse_mask_v_nxv1i8_nxv1i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf8,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv1i8( %0, * %1, @@ -1246,10 +1371,12 @@ i64); define @intrinsic_vlse_v_nxv2i8_nxv2i8(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf4,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv2i8( * %0, i64 %1, @@ -1266,10 +1393,12 @@ i64); define @intrinsic_vlse_mask_v_nxv2i8_nxv2i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf4,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv2i8( %0, * %1, @@ -1286,10 +1415,12 @@ i64); define @intrinsic_vlse_v_nxv4i8_nxv4i8(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf2,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv4i8( * %0, i64 %1, @@ -1306,10 +1437,12 @@ i64); define @intrinsic_vlse_mask_v_nxv4i8_nxv4i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf2,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv4i8( %0, * %1, @@ -1326,10 +1459,12 @@ i64); define @intrinsic_vlse_v_nxv8i8_nxv8i8(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a2, e8,m1,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv8i8( * %0, i64 %1, @@ -1346,10 +1481,12 @@ i64); define @intrinsic_vlse_mask_v_nxv8i8_nxv8i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a2, e8,m1,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv8i8( %0, * %1, @@ -1366,10 +1503,12 @@ i64); define @intrinsic_vlse_v_nxv16i8_nxv16i8(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a2, e8,m2,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv16i8( * %0, i64 %1, @@ -1386,10 +1525,12 @@ i64); define @intrinsic_vlse_mask_v_nxv16i8_nxv16i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m2,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a2, e8,m2,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv16i8( %0, * %1, @@ -1406,10 +1547,12 @@ i64); define @intrinsic_vlse_v_nxv32i8_nxv32i8(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a2, e8,m4,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv32i8( * %0, i64 %1, @@ -1426,10 +1569,12 @@ i64); define @intrinsic_vlse_mask_v_nxv32i8_nxv32i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m4,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a2, e8,m4,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv32i8( %0, * %1, @@ -1446,10 +1591,12 @@ i64); define @intrinsic_vlse_v_nxv64i8_nxv64i8(* %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a2, e8,m8,ta,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1 %a = call @llvm.riscv.vlse.nxv64i8( * %0, i64 %1, @@ -1466,10 +1613,12 @@ i64); define @intrinsic_vlse_mask_v_nxv64i8_nxv64i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vlse_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m8,tu,mu +; CHECK-NEXT: vlse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vlse_mask_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a2, e8,m8,tu,mu -; CHECK: vlse8.v {{v[0-9]+}}, (a0), a1, v0.t %a = call @llvm.riscv.vlse.mask.nxv64i8( %0, * %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll @@ -9,8 +9,8 @@ ; CHECK-LABEL: test_vlseg2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e16.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i32 %vl) @@ -22,11 +22,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e16.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i32 %vl) @@ -43,8 +43,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8(i8* %base, i32 %vl) @@ -56,11 +56,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8(i8* %base, i32 %vl) @@ -77,8 +77,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8(i8* %base, i32 %vl) @@ -90,12 +90,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8(i8* %base, i32 %vl) @@ -112,8 +112,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* %base, i32 %vl) @@ -125,13 +125,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* %base, i32 %vl) @@ -148,8 +148,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* %base, i32 %vl) @@ -161,14 +161,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* %base, i32 %vl) @@ -185,8 +185,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* %base, i32 %vl) @@ -198,15 +198,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* %base, i32 %vl) @@ -223,8 +223,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* %base, i32 %vl) @@ -236,16 +236,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* %base, i32 %vl) @@ -262,8 +262,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* %base, i32 %vl) @@ -275,17 +275,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* %base, i32 %vl) @@ -302,8 +302,8 @@ ; CHECK-LABEL: test_vlseg2_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg2e8.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e8.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8(i8* %base, i32 %vl) @@ -315,11 +315,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg2e8.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e8.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vlseg2e8.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e8.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8(i8* %base, i32 %vl) @@ -336,8 +336,8 @@ ; CHECK-LABEL: test_vlseg3_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg3e8.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e8.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8(i8* %base, i32 %vl) @@ -349,12 +349,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg3e8.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e8.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vlseg3e8.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e8.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8(i8* %base, i32 %vl) @@ -371,8 +371,8 @@ ; CHECK-LABEL: test_vlseg4_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg4e8.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e8.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* %base, i32 %vl) @@ -384,13 +384,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg4e8.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e8.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vlseg4e8.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e8.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* %base, i32 %vl) @@ -407,8 +407,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i32 %vl) @@ -420,11 +420,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i32 %vl) @@ -441,8 +441,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32(i32* %base, i32 %vl) @@ -454,12 +454,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32(i32* %base, i32 %vl) @@ -476,8 +476,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* %base, i32 %vl) @@ -489,13 +489,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* %base, i32 %vl) @@ -512,8 +512,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* %base, i32 %vl) @@ -525,14 +525,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* %base, i32 %vl) @@ -549,8 +549,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* %base, i32 %vl) @@ -562,15 +562,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* %base, i32 %vl) @@ -587,8 +587,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* %base, i32 %vl) @@ -600,16 +600,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* %base, i32 %vl) @@ -626,8 +626,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* %base, i32 %vl) @@ -639,17 +639,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* %base, i32 %vl) @@ -666,8 +666,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16(i16* %base, i32 %vl) @@ -679,11 +679,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16(i16* %base, i32 %vl) @@ -700,8 +700,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16(i16* %base, i32 %vl) @@ -713,12 +713,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16(i16* %base, i32 %vl) @@ -735,8 +735,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* %base, i32 %vl) @@ -748,13 +748,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* %base, i32 %vl) @@ -771,8 +771,8 @@ ; CHECK-LABEL: test_vlseg5_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* %base, i32 %vl) @@ -784,14 +784,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* %base, i32 %vl) @@ -808,8 +808,8 @@ ; CHECK-LABEL: test_vlseg6_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* %base, i32 %vl) @@ -821,15 +821,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* %base, i32 %vl) @@ -846,8 +846,8 @@ ; CHECK-LABEL: test_vlseg7_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* %base, i32 %vl) @@ -859,16 +859,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* %base, i32 %vl) @@ -885,8 +885,8 @@ ; CHECK-LABEL: test_vlseg8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* %base, i32 %vl) @@ -898,17 +898,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* %base, i32 %vl) @@ -925,8 +925,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i32 %vl) @@ -938,11 +938,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i32 %vl) @@ -959,8 +959,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32(i32* %base, i32 %vl) @@ -972,12 +972,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32(i32* %base, i32 %vl) @@ -994,8 +994,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* %base, i32 %vl) @@ -1007,13 +1007,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* %base, i32 %vl) @@ -1030,8 +1030,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* %base, i32 %vl) @@ -1043,14 +1043,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* %base, i32 %vl) @@ -1067,8 +1067,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* %base, i32 %vl) @@ -1080,15 +1080,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* %base, i32 %vl) @@ -1105,8 +1105,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* %base, i32 %vl) @@ -1118,16 +1118,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* %base, i32 %vl) @@ -1144,8 +1144,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* %base, i32 %vl) @@ -1157,17 +1157,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* %base, i32 %vl) @@ -1184,8 +1184,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16(i16* %base, i32 %vl) @@ -1197,11 +1197,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16(i16* %base, i32 %vl) @@ -1218,8 +1218,8 @@ ; CHECK-LABEL: test_vlseg3_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16(i16* %base, i32 %vl) @@ -1231,12 +1231,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16(i16* %base, i32 %vl) @@ -1253,8 +1253,8 @@ ; CHECK-LABEL: test_vlseg4_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* %base, i32 %vl) @@ -1266,13 +1266,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* %base, i32 %vl) @@ -1289,8 +1289,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8(i8* %base, i32 %vl) @@ -1302,11 +1302,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8(i8* %base, i32 %vl) @@ -1323,8 +1323,8 @@ ; CHECK-LABEL: test_vlseg3_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8(i8* %base, i32 %vl) @@ -1336,12 +1336,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8(i8* %base, i32 %vl) @@ -1358,8 +1358,8 @@ ; CHECK-LABEL: test_vlseg4_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* %base, i32 %vl) @@ -1371,13 +1371,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* %base, i32 %vl) @@ -1394,8 +1394,8 @@ ; CHECK-LABEL: test_vlseg5_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* %base, i32 %vl) @@ -1407,14 +1407,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* %base, i32 %vl) @@ -1431,8 +1431,8 @@ ; CHECK-LABEL: test_vlseg6_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* %base, i32 %vl) @@ -1444,15 +1444,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* %base, i32 %vl) @@ -1469,8 +1469,8 @@ ; CHECK-LABEL: test_vlseg7_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* %base, i32 %vl) @@ -1482,16 +1482,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* %base, i32 %vl) @@ -1508,8 +1508,8 @@ ; CHECK-LABEL: test_vlseg8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* %base, i32 %vl) @@ -1521,17 +1521,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* %base, i32 %vl) @@ -1548,8 +1548,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e32.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i32 %vl) @@ -1561,11 +1561,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m4,ta,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e32.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i32 %vl) @@ -1582,8 +1582,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8(i8* %base, i32 %vl) @@ -1595,11 +1595,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8(i8* %base, i32 %vl) @@ -1616,8 +1616,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8(i8* %base, i32 %vl) @@ -1629,12 +1629,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8(i8* %base, i32 %vl) @@ -1651,8 +1651,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* %base, i32 %vl) @@ -1664,13 +1664,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* %base, i32 %vl) @@ -1687,8 +1687,8 @@ ; CHECK-LABEL: test_vlseg5_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* %base, i32 %vl) @@ -1700,14 +1700,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* %base, i32 %vl) @@ -1724,8 +1724,8 @@ ; CHECK-LABEL: test_vlseg6_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* %base, i32 %vl) @@ -1737,15 +1737,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* %base, i32 %vl) @@ -1762,8 +1762,8 @@ ; CHECK-LABEL: test_vlseg7_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* %base, i32 %vl) @@ -1775,16 +1775,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* %base, i32 %vl) @@ -1801,8 +1801,8 @@ ; CHECK-LABEL: test_vlseg8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* %base, i32 %vl) @@ -1814,17 +1814,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* %base, i32 %vl) @@ -1841,8 +1841,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16(i16* %base, i32 %vl) @@ -1854,11 +1854,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16(i16* %base, i32 %vl) @@ -1875,8 +1875,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16(i16* %base, i32 %vl) @@ -1888,12 +1888,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16(i16* %base, i32 %vl) @@ -1910,8 +1910,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* %base, i32 %vl) @@ -1923,13 +1923,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* %base, i32 %vl) @@ -1946,8 +1946,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* %base, i32 %vl) @@ -1959,14 +1959,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* %base, i32 %vl) @@ -1983,8 +1983,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* %base, i32 %vl) @@ -1996,15 +1996,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* %base, i32 %vl) @@ -2021,8 +2021,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* %base, i32 %vl) @@ -2034,16 +2034,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* %base, i32 %vl) @@ -2060,8 +2060,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* %base, i32 %vl) @@ -2073,17 +2073,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* %base, i32 %vl) @@ -2100,8 +2100,8 @@ ; CHECK-LABEL: test_vlseg2_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vlseg2e8.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e8.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8(i8* %base, i32 %vl) @@ -2113,11 +2113,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m4,ta,mu -; CHECK-NEXT: vlseg2e8.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e8.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vlseg2e8.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e8.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8(i8* %base, i32 %vl) @@ -2134,8 +2134,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8(i8* %base, i32 %vl) @@ -2147,11 +2147,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8(i8* %base, i32 %vl) @@ -2168,8 +2168,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8(i8* %base, i32 %vl) @@ -2181,12 +2181,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8(i8* %base, i32 %vl) @@ -2203,8 +2203,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* %base, i32 %vl) @@ -2216,13 +2216,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* %base, i32 %vl) @@ -2239,8 +2239,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* %base, i32 %vl) @@ -2252,14 +2252,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* %base, i32 %vl) @@ -2276,8 +2276,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* %base, i32 %vl) @@ -2289,15 +2289,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* %base, i32 %vl) @@ -2314,8 +2314,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* %base, i32 %vl) @@ -2327,16 +2327,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* %base, i32 %vl) @@ -2353,8 +2353,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* %base, i32 %vl) @@ -2366,17 +2366,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* %base, i32 %vl) @@ -2393,8 +2393,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16(i16* %base, i32 %vl) @@ -2406,11 +2406,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16(i16* %base, i32 %vl) @@ -2427,8 +2427,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16(i16* %base, i32 %vl) @@ -2440,12 +2440,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16(i16* %base, i32 %vl) @@ -2462,8 +2462,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* %base, i32 %vl) @@ -2475,13 +2475,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* %base, i32 %vl) @@ -2498,8 +2498,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* %base, i32 %vl) @@ -2511,14 +2511,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* %base, i32 %vl) @@ -2535,8 +2535,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* %base, i32 %vl) @@ -2548,15 +2548,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* %base, i32 %vl) @@ -2573,8 +2573,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* %base, i32 %vl) @@ -2586,16 +2586,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* %base, i32 %vl) @@ -2612,8 +2612,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* %base, i32 %vl) @@ -2625,17 +2625,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* %base, i32 %vl) @@ -2652,8 +2652,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i32 %vl) @@ -2665,11 +2665,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i32 %vl) @@ -2686,8 +2686,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i32 %vl) @@ -2699,12 +2699,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i32 %vl) @@ -2721,8 +2721,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* %base, i32 %vl) @@ -2734,13 +2734,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* %base, i32 %vl) @@ -2757,8 +2757,8 @@ ; CHECK-LABEL: test_vlseg2_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e16.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16(half* %base, i32 %vl) @@ -2770,11 +2770,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e16.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16(half* %base, i32 %vl) @@ -2791,8 +2791,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vlseg2e64.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e64.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64(double* %base, i32 %vl) @@ -2804,11 +2804,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m4,ta,mu -; CHECK-NEXT: vlseg2e64.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e64.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vlseg2e64.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64(double* %base, i32 %vl) @@ -2825,8 +2825,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg2e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64(double* %base, i32 %vl) @@ -2838,11 +2838,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg2e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg2e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64(double* %base, i32 %vl) @@ -2859,8 +2859,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg3e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64(double* %base, i32 %vl) @@ -2872,12 +2872,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg3e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg3e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64(double* %base, i32 %vl) @@ -2894,8 +2894,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg4e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64(double* %base, i32 %vl) @@ -2907,13 +2907,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg4e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg4e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64(double* %base, i32 %vl) @@ -2930,8 +2930,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg5e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* %base, i32 %vl) @@ -2943,14 +2943,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg5e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg5e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* %base, i32 %vl) @@ -2967,8 +2967,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg6e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* %base, i32 %vl) @@ -2980,15 +2980,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg6e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg6e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* %base, i32 %vl) @@ -3005,8 +3005,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg7e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* %base, i32 %vl) @@ -3018,16 +3018,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg7e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg7e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* %base, i32 %vl) @@ -3044,8 +3044,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg8e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* %base, i32 %vl) @@ -3057,17 +3057,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg8e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg8e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* %base, i32 %vl) @@ -3084,8 +3084,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32(float* %base, i32 %vl) @@ -3097,11 +3097,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32(float* %base, i32 %vl) @@ -3118,8 +3118,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32(float* %base, i32 %vl) @@ -3131,12 +3131,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32(float* %base, i32 %vl) @@ -3153,8 +3153,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32(float* %base, i32 %vl) @@ -3166,13 +3166,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32(float* %base, i32 %vl) @@ -3189,8 +3189,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* %base, i32 %vl) @@ -3202,14 +3202,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* %base, i32 %vl) @@ -3226,8 +3226,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* %base, i32 %vl) @@ -3239,15 +3239,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* %base, i32 %vl) @@ -3264,8 +3264,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* %base, i32 %vl) @@ -3277,16 +3277,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* %base, i32 %vl) @@ -3303,8 +3303,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* %base, i32 %vl) @@ -3316,17 +3316,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* %base, i32 %vl) @@ -3343,8 +3343,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16(half* %base, i32 %vl) @@ -3356,11 +3356,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16(half* %base, i32 %vl) @@ -3377,8 +3377,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16(half* %base, i32 %vl) @@ -3390,12 +3390,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16(half* %base, i32 %vl) @@ -3412,8 +3412,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16(half* %base, i32 %vl) @@ -3425,13 +3425,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16(half* %base, i32 %vl) @@ -3448,8 +3448,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* %base, i32 %vl) @@ -3461,14 +3461,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* %base, i32 %vl) @@ -3485,8 +3485,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* %base, i32 %vl) @@ -3498,15 +3498,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* %base, i32 %vl) @@ -3523,8 +3523,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* %base, i32 %vl) @@ -3536,16 +3536,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* %base, i32 %vl) @@ -3562,8 +3562,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* %base, i32 %vl) @@ -3575,17 +3575,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* %base, i32 %vl) @@ -3602,8 +3602,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32(float* %base, i32 %vl) @@ -3615,11 +3615,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32(float* %base, i32 %vl) @@ -3636,8 +3636,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32(float* %base, i32 %vl) @@ -3649,12 +3649,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32(float* %base, i32 %vl) @@ -3671,8 +3671,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32(float* %base, i32 %vl) @@ -3684,13 +3684,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32(float* %base, i32 %vl) @@ -3707,8 +3707,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* %base, i32 %vl) @@ -3720,14 +3720,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* %base, i32 %vl) @@ -3744,8 +3744,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* %base, i32 %vl) @@ -3757,15 +3757,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* %base, i32 %vl) @@ -3782,8 +3782,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* %base, i32 %vl) @@ -3795,16 +3795,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* %base, i32 %vl) @@ -3821,8 +3821,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* %base, i32 %vl) @@ -3834,17 +3834,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* %base, i32 %vl) @@ -3861,8 +3861,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16(half* %base, i32 %vl) @@ -3874,11 +3874,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16(half* %base, i32 %vl) @@ -3895,8 +3895,8 @@ ; CHECK-LABEL: test_vlseg3_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16(half* %base, i32 %vl) @@ -3908,12 +3908,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16(half* %base, i32 %vl) @@ -3930,8 +3930,8 @@ ; CHECK-LABEL: test_vlseg4_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16(half* %base, i32 %vl) @@ -3943,13 +3943,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16(half* %base, i32 %vl) @@ -3966,8 +3966,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e32.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32(float* %base, i32 %vl) @@ -3979,11 +3979,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m4,ta,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e32.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32(float* %base, i32 %vl) @@ -4000,8 +4000,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg2e64.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e64.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64(double* %base, i32 %vl) @@ -4013,11 +4013,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg2e64.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e64.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vlseg2e64.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64(double* %base, i32 %vl) @@ -4034,8 +4034,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg3e64.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e64.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64(double* %base, i32 %vl) @@ -4047,12 +4047,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg3e64.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e64.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vlseg3e64.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64(double* %base, i32 %vl) @@ -4069,8 +4069,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg4e64.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e64.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64(double* %base, i32 %vl) @@ -4082,13 +4082,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg4e64.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e64.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vlseg4e64.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64(double* %base, i32 %vl) @@ -4105,8 +4105,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16(half* %base, i32 %vl) @@ -4118,11 +4118,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16(half* %base, i32 %vl) @@ -4139,8 +4139,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16(half* %base, i32 %vl) @@ -4152,12 +4152,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16(half* %base, i32 %vl) @@ -4174,8 +4174,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16(half* %base, i32 %vl) @@ -4187,13 +4187,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16(half* %base, i32 %vl) @@ -4210,8 +4210,8 @@ ; CHECK-LABEL: test_vlseg5_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* %base, i32 %vl) @@ -4223,14 +4223,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* %base, i32 %vl) @@ -4247,8 +4247,8 @@ ; CHECK-LABEL: test_vlseg6_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* %base, i32 %vl) @@ -4260,15 +4260,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* %base, i32 %vl) @@ -4285,8 +4285,8 @@ ; CHECK-LABEL: test_vlseg7_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* %base, i32 %vl) @@ -4298,16 +4298,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* %base, i32 %vl) @@ -4324,8 +4324,8 @@ ; CHECK-LABEL: test_vlseg8_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* %base, i32 %vl) @@ -4337,17 +4337,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* %base, i32 %vl) @@ -4364,8 +4364,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16(half* %base, i32 %vl) @@ -4377,11 +4377,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16(half* %base, i32 %vl) @@ -4398,8 +4398,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16(half* %base, i32 %vl) @@ -4411,12 +4411,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16(half* %base, i32 %vl) @@ -4433,8 +4433,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16(half* %base, i32 %vl) @@ -4446,13 +4446,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16(half* %base, i32 %vl) @@ -4469,8 +4469,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* %base, i32 %vl) @@ -4482,14 +4482,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* %base, i32 %vl) @@ -4506,8 +4506,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* %base, i32 %vl) @@ -4519,15 +4519,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* %base, i32 %vl) @@ -4544,8 +4544,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* %base, i32 %vl) @@ -4557,16 +4557,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* %base, i32 %vl) @@ -4583,8 +4583,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* %base, i32 %vl) @@ -4596,17 +4596,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* %base, i32 %vl) @@ -4623,8 +4623,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32(float* %base, i32 %vl) @@ -4636,11 +4636,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32(float* %base, i32 %vl) @@ -4657,8 +4657,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32(float* %base, i32 %vl) @@ -4670,12 +4670,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32(float* %base, i32 %vl) @@ -4692,8 +4692,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32(float* %base, i32 %vl) @@ -4705,13 +4705,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32(float* %base, i32 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll @@ -9,8 +9,8 @@ ; CHECK-LABEL: test_vlseg2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e16.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i64 %vl) @@ -22,11 +22,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e16.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i64 %vl) @@ -43,8 +43,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i64 %vl) @@ -56,11 +56,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i32(i32* %base, i64 %vl) @@ -77,8 +77,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i64 %vl) @@ -90,12 +90,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i32(i32* %base, i64 %vl) @@ -112,8 +112,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* %base, i64 %vl) @@ -125,13 +125,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i32(i32* %base, i64 %vl) @@ -148,8 +148,8 @@ ; CHECK-LABEL: test_vlseg2_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg2e8.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e8.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8(i8* %base, i64 %vl) @@ -161,11 +161,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg2e8.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e8.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vlseg2e8.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e8.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16i8(i8* %base, i64 %vl) @@ -182,8 +182,8 @@ ; CHECK-LABEL: test_vlseg3_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg3e8.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e8.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8(i8* %base, i64 %vl) @@ -195,12 +195,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg3e8.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e8.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vlseg3e8.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e8.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv16i8(i8* %base, i64 %vl) @@ -217,8 +217,8 @@ ; CHECK-LABEL: test_vlseg4_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg4e8.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e8.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* %base, i64 %vl) @@ -230,13 +230,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m2,ta,mu -; CHECK-NEXT: vlseg4e8.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e8.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vlseg4e8.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e8.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv16i8(i8* %base, i64 %vl) @@ -253,8 +253,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg2e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i64(i64* %base, i64 %vl) @@ -266,11 +266,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg2e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg2e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i64(i64* %base, i64 %vl) @@ -287,8 +287,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg3e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i64(i64* %base, i64 %vl) @@ -300,12 +300,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg3e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg3e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i64(i64* %base, i64 %vl) @@ -322,8 +322,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg4e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i64(i64* %base, i64 %vl) @@ -335,13 +335,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg4e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg4e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i64(i64* %base, i64 %vl) @@ -358,8 +358,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg5e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i64(i64* %base, i64 %vl) @@ -371,14 +371,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg5e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg5e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i64(i64* %base, i64 %vl) @@ -395,8 +395,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg6e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i64(i64* %base, i64 %vl) @@ -408,15 +408,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg6e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg6e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i64(i64* %base, i64 %vl) @@ -433,8 +433,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg7e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i64(i64* %base, i64 %vl) @@ -446,16 +446,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg7e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg7e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i64(i64* %base, i64 %vl) @@ -472,8 +472,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg8e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i64(i64* %base, i64 %vl) @@ -485,17 +485,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg8e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg8e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i64(i64* %base, i64 %vl) @@ -512,8 +512,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i64 %vl) @@ -525,11 +525,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i32(i32* %base, i64 %vl) @@ -546,8 +546,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32(i32* %base, i64 %vl) @@ -559,12 +559,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i32(i32* %base, i64 %vl) @@ -581,8 +581,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* %base, i64 %vl) @@ -594,13 +594,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i32(i32* %base, i64 %vl) @@ -617,8 +617,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* %base, i64 %vl) @@ -630,14 +630,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i32(i32* %base, i64 %vl) @@ -654,8 +654,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* %base, i64 %vl) @@ -667,15 +667,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i32(i32* %base, i64 %vl) @@ -692,8 +692,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* %base, i64 %vl) @@ -705,16 +705,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i32(i32* %base, i64 %vl) @@ -731,8 +731,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* %base, i64 %vl) @@ -744,17 +744,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i32(i32* %base, i64 %vl) @@ -771,8 +771,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16(i16* %base, i64 %vl) @@ -784,11 +784,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i16(i16* %base, i64 %vl) @@ -805,8 +805,8 @@ ; CHECK-LABEL: test_vlseg3_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16(i16* %base, i64 %vl) @@ -818,12 +818,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i16(i16* %base, i64 %vl) @@ -840,8 +840,8 @@ ; CHECK-LABEL: test_vlseg4_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* %base, i64 %vl) @@ -853,13 +853,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i16(i16* %base, i64 %vl) @@ -876,8 +876,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8(i8* %base, i64 %vl) @@ -889,11 +889,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i8(i8* %base, i64 %vl) @@ -910,8 +910,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8(i8* %base, i64 %vl) @@ -923,12 +923,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i8(i8* %base, i64 %vl) @@ -945,8 +945,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* %base, i64 %vl) @@ -958,13 +958,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i8(i8* %base, i64 %vl) @@ -981,8 +981,8 @@ ; CHECK-LABEL: test_vlseg5_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* %base, i64 %vl) @@ -994,14 +994,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i8(i8* %base, i64 %vl) @@ -1018,8 +1018,8 @@ ; CHECK-LABEL: test_vlseg6_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* %base, i64 %vl) @@ -1031,15 +1031,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i8(i8* %base, i64 %vl) @@ -1056,8 +1056,8 @@ ; CHECK-LABEL: test_vlseg7_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* %base, i64 %vl) @@ -1069,16 +1069,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i8(i8* %base, i64 %vl) @@ -1095,8 +1095,8 @@ ; CHECK-LABEL: test_vlseg8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* %base, i64 %vl) @@ -1108,17 +1108,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf2,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i8(i8* %base, i64 %vl) @@ -1135,8 +1135,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16(i16* %base, i64 %vl) @@ -1148,11 +1148,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i16(i16* %base, i64 %vl) @@ -1169,8 +1169,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16(i16* %base, i64 %vl) @@ -1182,12 +1182,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i16(i16* %base, i64 %vl) @@ -1204,8 +1204,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* %base, i64 %vl) @@ -1217,13 +1217,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i16(i16* %base, i64 %vl) @@ -1240,8 +1240,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* %base, i64 %vl) @@ -1253,14 +1253,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i16(i16* %base, i64 %vl) @@ -1277,8 +1277,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* %base, i64 %vl) @@ -1290,15 +1290,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i16(i16* %base, i64 %vl) @@ -1315,8 +1315,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* %base, i64 %vl) @@ -1328,16 +1328,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i16(i16* %base, i64 %vl) @@ -1354,8 +1354,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* %base, i64 %vl) @@ -1367,17 +1367,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i16(i16* %base, i64 %vl) @@ -1394,8 +1394,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i64 %vl) @@ -1407,11 +1407,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i32(i32* %base, i64 %vl) @@ -1428,8 +1428,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32(i32* %base, i64 %vl) @@ -1441,12 +1441,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i32(i32* %base, i64 %vl) @@ -1463,8 +1463,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* %base, i64 %vl) @@ -1476,13 +1476,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i32(i32* %base, i64 %vl) @@ -1499,8 +1499,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* %base, i64 %vl) @@ -1512,14 +1512,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i32(i32* %base, i64 %vl) @@ -1536,8 +1536,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* %base, i64 %vl) @@ -1549,15 +1549,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i32(i32* %base, i64 %vl) @@ -1574,8 +1574,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* %base, i64 %vl) @@ -1587,16 +1587,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i32(i32* %base, i64 %vl) @@ -1613,8 +1613,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* %base, i64 %vl) @@ -1626,17 +1626,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i32(i32* %base, i64 %vl) @@ -1653,8 +1653,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8(i8* %base, i64 %vl) @@ -1666,11 +1666,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i8(i8* %base, i64 %vl) @@ -1687,8 +1687,8 @@ ; CHECK-LABEL: test_vlseg3_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8(i8* %base, i64 %vl) @@ -1700,12 +1700,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8i8(i8* %base, i64 %vl) @@ -1722,8 +1722,8 @@ ; CHECK-LABEL: test_vlseg4_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* %base, i64 %vl) @@ -1735,13 +1735,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8i8(i8* %base, i64 %vl) @@ -1758,8 +1758,8 @@ ; CHECK-LABEL: test_vlseg5_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* %base, i64 %vl) @@ -1771,14 +1771,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv8i8(i8* %base, i64 %vl) @@ -1795,8 +1795,8 @@ ; CHECK-LABEL: test_vlseg6_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* %base, i64 %vl) @@ -1808,15 +1808,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv8i8(i8* %base, i64 %vl) @@ -1833,8 +1833,8 @@ ; CHECK-LABEL: test_vlseg7_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* %base, i64 %vl) @@ -1846,16 +1846,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv8i8(i8* %base, i64 %vl) @@ -1872,8 +1872,8 @@ ; CHECK-LABEL: test_vlseg8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* %base, i64 %vl) @@ -1885,17 +1885,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m1,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv8i8(i8* %base, i64 %vl) @@ -1912,8 +1912,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vlseg2e64.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e64.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i64(i64* %base, i64 %vl) @@ -1925,11 +1925,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m4,ta,mu -; CHECK-NEXT: vlseg2e64.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e64.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vlseg2e64.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i64(i64* %base, i64 %vl) @@ -1946,8 +1946,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16(i16* %base, i64 %vl) @@ -1959,11 +1959,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4i16(i16* %base, i64 %vl) @@ -1980,8 +1980,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16(i16* %base, i64 %vl) @@ -1993,12 +1993,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4i16(i16* %base, i64 %vl) @@ -2015,8 +2015,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* %base, i64 %vl) @@ -2028,13 +2028,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4i16(i16* %base, i64 %vl) @@ -2051,8 +2051,8 @@ ; CHECK-LABEL: test_vlseg5_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* %base, i64 %vl) @@ -2064,14 +2064,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4i16(i16* %base, i64 %vl) @@ -2088,8 +2088,8 @@ ; CHECK-LABEL: test_vlseg6_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* %base, i64 %vl) @@ -2101,15 +2101,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4i16(i16* %base, i64 %vl) @@ -2126,8 +2126,8 @@ ; CHECK-LABEL: test_vlseg7_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* %base, i64 %vl) @@ -2139,16 +2139,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4i16(i16* %base, i64 %vl) @@ -2165,8 +2165,8 @@ ; CHECK-LABEL: test_vlseg8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* %base, i64 %vl) @@ -2178,17 +2178,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4i16(i16* %base, i64 %vl) @@ -2205,8 +2205,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8(i8* %base, i64 %vl) @@ -2218,11 +2218,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1i8(i8* %base, i64 %vl) @@ -2239,8 +2239,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8(i8* %base, i64 %vl) @@ -2252,12 +2252,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1i8(i8* %base, i64 %vl) @@ -2274,8 +2274,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* %base, i64 %vl) @@ -2287,13 +2287,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1i8(i8* %base, i64 %vl) @@ -2310,8 +2310,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* %base, i64 %vl) @@ -2323,14 +2323,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1i8(i8* %base, i64 %vl) @@ -2347,8 +2347,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* %base, i64 %vl) @@ -2360,15 +2360,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1i8(i8* %base, i64 %vl) @@ -2385,8 +2385,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* %base, i64 %vl) @@ -2398,16 +2398,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1i8(i8* %base, i64 %vl) @@ -2424,8 +2424,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* %base, i64 %vl) @@ -2437,17 +2437,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf8,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1i8(i8* %base, i64 %vl) @@ -2464,8 +2464,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8(i8* %base, i64 %vl) @@ -2477,11 +2477,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg2e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i8(i8* %base, i64 %vl) @@ -2498,8 +2498,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8(i8* %base, i64 %vl) @@ -2511,12 +2511,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg3e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i8(i8* %base, i64 %vl) @@ -2533,8 +2533,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* %base, i64 %vl) @@ -2546,13 +2546,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg4e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i8(i8* %base, i64 %vl) @@ -2569,8 +2569,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* %base, i64 %vl) @@ -2582,14 +2582,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg5e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i8(i8* %base, i64 %vl) @@ -2606,8 +2606,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* %base, i64 %vl) @@ -2619,15 +2619,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg6e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i8(i8* %base, i64 %vl) @@ -2644,8 +2644,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* %base, i64 %vl) @@ -2657,16 +2657,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg7e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i8(i8* %base, i64 %vl) @@ -2683,8 +2683,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* %base, i64 %vl) @@ -2696,17 +2696,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,mf4,ta,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e8.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vlseg8e8.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e8.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i8(i8* %base, i64 %vl) @@ -2723,8 +2723,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e32.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i64 %vl) @@ -2736,11 +2736,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m4,ta,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e32.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8i32(i32* %base, i64 %vl) @@ -2757,8 +2757,8 @@ ; CHECK-LABEL: test_vlseg2_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vlseg2e8.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e8.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8(i8* %base, i64 %vl) @@ -2770,11 +2770,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e8,m4,ta,mu -; CHECK-NEXT: vlseg2e8.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e8.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vlseg2e8.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e8.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv32i8(i8* %base, i64 %vl) @@ -2791,8 +2791,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16(i16* %base, i64 %vl) @@ -2804,11 +2804,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i16(i16* %base, i64 %vl) @@ -2825,8 +2825,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16(i16* %base, i64 %vl) @@ -2838,12 +2838,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i16(i16* %base, i64 %vl) @@ -2860,8 +2860,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* %base, i64 %vl) @@ -2873,13 +2873,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i16(i16* %base, i64 %vl) @@ -2896,8 +2896,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* %base, i64 %vl) @@ -2909,14 +2909,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2i16(i16* %base, i64 %vl) @@ -2933,8 +2933,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* %base, i64 %vl) @@ -2946,15 +2946,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2i16(i16* %base, i64 %vl) @@ -2971,8 +2971,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* %base, i64 %vl) @@ -2984,16 +2984,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2i16(i16* %base, i64 %vl) @@ -3010,8 +3010,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* %base, i64 %vl) @@ -3023,17 +3023,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2i16(i16* %base, i64 %vl) @@ -3050,8 +3050,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg2e64.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e64.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i64(i64* %base, i64 %vl) @@ -3063,11 +3063,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg2e64.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e64.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vlseg2e64.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2i64(i64* %base, i64 %vl) @@ -3084,8 +3084,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg3e64.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e64.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i64(i64* %base, i64 %vl) @@ -3097,12 +3097,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg3e64.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e64.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vlseg3e64.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2i64(i64* %base, i64 %vl) @@ -3119,8 +3119,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg4e64.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e64.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i64(i64* %base, i64 %vl) @@ -3132,13 +3132,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg4e64.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e64.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vlseg4e64.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2i64(i64* %base, i64 %vl) @@ -3155,8 +3155,8 @@ ; CHECK-LABEL: test_vlseg2_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e16.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16(half* %base, i64 %vl) @@ -3168,11 +3168,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e16.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vlseg2e16.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv16f16(half* %base, i64 %vl) @@ -3189,8 +3189,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vlseg2e64.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e64.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64(double* %base, i64 %vl) @@ -3202,11 +3202,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m4,ta,mu -; CHECK-NEXT: vlseg2e64.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e64.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vlseg2e64.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e64.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f64(double* %base, i64 %vl) @@ -3223,8 +3223,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg2e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64(double* %base, i64 %vl) @@ -3236,11 +3236,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg2e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg2e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f64(double* %base, i64 %vl) @@ -3257,8 +3257,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg3e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64(double* %base, i64 %vl) @@ -3270,12 +3270,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg3e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg3e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f64(double* %base, i64 %vl) @@ -3292,8 +3292,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg4e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64(double* %base, i64 %vl) @@ -3305,13 +3305,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg4e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg4e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f64(double* %base, i64 %vl) @@ -3328,8 +3328,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg5e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* %base, i64 %vl) @@ -3341,14 +3341,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg5e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg5e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f64(double* %base, i64 %vl) @@ -3365,8 +3365,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg6e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* %base, i64 %vl) @@ -3378,15 +3378,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg6e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg6e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f64(double* %base, i64 %vl) @@ -3403,8 +3403,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg7e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* %base, i64 %vl) @@ -3416,16 +3416,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg7e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg7e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f64(double* %base, i64 %vl) @@ -3442,8 +3442,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg8e64.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e64.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* %base, i64 %vl) @@ -3455,17 +3455,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m1,ta,mu -; CHECK-NEXT: vlseg8e64.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e64.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vlseg8e64.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e64.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f64(double* %base, i64 %vl) @@ -3482,8 +3482,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32(float* %base, i64 %vl) @@ -3495,11 +3495,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f32(float* %base, i64 %vl) @@ -3516,8 +3516,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32(float* %base, i64 %vl) @@ -3529,12 +3529,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f32(float* %base, i64 %vl) @@ -3551,8 +3551,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32(float* %base, i64 %vl) @@ -3564,13 +3564,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f32(float* %base, i64 %vl) @@ -3587,8 +3587,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* %base, i64 %vl) @@ -3600,14 +3600,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f32(float* %base, i64 %vl) @@ -3624,8 +3624,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* %base, i64 %vl) @@ -3637,15 +3637,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f32(float* %base, i64 %vl) @@ -3662,8 +3662,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* %base, i64 %vl) @@ -3675,16 +3675,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f32(float* %base, i64 %vl) @@ -3701,8 +3701,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* %base, i64 %vl) @@ -3714,17 +3714,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m1,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f32(float* %base, i64 %vl) @@ -3741,8 +3741,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16(half* %base, i64 %vl) @@ -3754,11 +3754,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f16(half* %base, i64 %vl) @@ -3775,8 +3775,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16(half* %base, i64 %vl) @@ -3788,12 +3788,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f16(half* %base, i64 %vl) @@ -3810,8 +3810,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16(half* %base, i64 %vl) @@ -3823,13 +3823,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f16(half* %base, i64 %vl) @@ -3846,8 +3846,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* %base, i64 %vl) @@ -3859,14 +3859,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f16(half* %base, i64 %vl) @@ -3883,8 +3883,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* %base, i64 %vl) @@ -3896,15 +3896,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f16(half* %base, i64 %vl) @@ -3921,8 +3921,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* %base, i64 %vl) @@ -3934,16 +3934,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f16(half* %base, i64 %vl) @@ -3960,8 +3960,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* %base, i64 %vl) @@ -3973,17 +3973,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf4,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f16(half* %base, i64 %vl) @@ -4000,8 +4000,8 @@ ; CHECK-LABEL: test_vlseg2_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32(float* %base, i64 %vl) @@ -4013,11 +4013,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg2e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv1f32(float* %base, i64 %vl) @@ -4034,8 +4034,8 @@ ; CHECK-LABEL: test_vlseg3_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32(float* %base, i64 %vl) @@ -4047,12 +4047,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg3e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv1f32(float* %base, i64 %vl) @@ -4069,8 +4069,8 @@ ; CHECK-LABEL: test_vlseg4_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32(float* %base, i64 %vl) @@ -4082,13 +4082,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg4e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv1f32(float* %base, i64 %vl) @@ -4105,8 +4105,8 @@ ; CHECK-LABEL: test_vlseg5_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* %base, i64 %vl) @@ -4118,14 +4118,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg5e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv1f32(float* %base, i64 %vl) @@ -4142,8 +4142,8 @@ ; CHECK-LABEL: test_vlseg6_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* %base, i64 %vl) @@ -4155,15 +4155,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg6e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv1f32(float* %base, i64 %vl) @@ -4180,8 +4180,8 @@ ; CHECK-LABEL: test_vlseg7_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* %base, i64 %vl) @@ -4193,16 +4193,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg7e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv1f32(float* %base, i64 %vl) @@ -4219,8 +4219,8 @@ ; CHECK-LABEL: test_vlseg8_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* %base, i64 %vl) @@ -4232,17 +4232,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,mf2,ta,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e32.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vlseg8e32.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e32.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv1f32(float* %base, i64 %vl) @@ -4259,8 +4259,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16(half* %base, i64 %vl) @@ -4272,11 +4272,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg2e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f16(half* %base, i64 %vl) @@ -4293,8 +4293,8 @@ ; CHECK-LABEL: test_vlseg3_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16(half* %base, i64 %vl) @@ -4306,12 +4306,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg3e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv8f16(half* %base, i64 %vl) @@ -4328,8 +4328,8 @@ ; CHECK-LABEL: test_vlseg4_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e16.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16(half* %base, i64 %vl) @@ -4341,13 +4341,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m2,ta,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e16.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vlseg4e16.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e16.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv8f16(half* %base, i64 %vl) @@ -4364,8 +4364,8 @@ ; CHECK-LABEL: test_vlseg2_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0) -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e32.v v4, (a0) +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32(float* %base, i64 %vl) @@ -4377,11 +4377,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m4,ta,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0) -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlseg2e32.v v4, (a0) +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vlseg2e32.v v12, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlseg2e32.v v4, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv8f32(float* %base, i64 %vl) @@ -4398,8 +4398,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg2e64.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e64.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64(double* %base, i64 %vl) @@ -4411,11 +4411,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg2e64.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e64.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vlseg2e64.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e64.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f64(double* %base, i64 %vl) @@ -4432,8 +4432,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg3e64.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e64.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64(double* %base, i64 %vl) @@ -4445,12 +4445,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg3e64.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e64.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vlseg3e64.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e64.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f64(double* %base, i64 %vl) @@ -4467,8 +4467,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg4e64.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e64.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64(double* %base, i64 %vl) @@ -4480,13 +4480,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e64,m2,ta,mu -; CHECK-NEXT: vlseg4e64.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e64.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vlseg4e64.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e64.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f64(double* %base, i64 %vl) @@ -4503,8 +4503,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16(half* %base, i64 %vl) @@ -4516,11 +4516,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f16(half* %base, i64 %vl) @@ -4537,8 +4537,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16(half* %base, i64 %vl) @@ -4550,12 +4550,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f16(half* %base, i64 %vl) @@ -4572,8 +4572,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16(half* %base, i64 %vl) @@ -4585,13 +4585,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f16(half* %base, i64 %vl) @@ -4608,8 +4608,8 @@ ; CHECK-LABEL: test_vlseg5_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* %base, i64 %vl) @@ -4621,14 +4621,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv4f16(half* %base, i64 %vl) @@ -4645,8 +4645,8 @@ ; CHECK-LABEL: test_vlseg6_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* %base, i64 %vl) @@ -4658,15 +4658,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv4f16(half* %base, i64 %vl) @@ -4683,8 +4683,8 @@ ; CHECK-LABEL: test_vlseg7_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* %base, i64 %vl) @@ -4696,16 +4696,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv4f16(half* %base, i64 %vl) @@ -4722,8 +4722,8 @@ ; CHECK-LABEL: test_vlseg8_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* %base, i64 %vl) @@ -4735,17 +4735,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,m1,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv4f16(half* %base, i64 %vl) @@ -4762,8 +4762,8 @@ ; CHECK-LABEL: test_vlseg2_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16(half* %base, i64 %vl) @@ -4775,11 +4775,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlseg2e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg2e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlseg2e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv2f16(half* %base, i64 %vl) @@ -4796,8 +4796,8 @@ ; CHECK-LABEL: test_vlseg3_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16(half* %base, i64 %vl) @@ -4809,12 +4809,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlseg3e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg3e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlseg3e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv2f16(half* %base, i64 %vl) @@ -4831,8 +4831,8 @@ ; CHECK-LABEL: test_vlseg4_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16(half* %base, i64 %vl) @@ -4844,13 +4844,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlseg4e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg4e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlseg4e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv2f16(half* %base, i64 %vl) @@ -4867,8 +4867,8 @@ ; CHECK-LABEL: test_vlseg5_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* %base, i64 %vl) @@ -4880,14 +4880,14 @@ ; CHECK-LABEL: test_vlseg5_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlseg5e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg5e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlseg5e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlseg5.nxv2f16(half* %base, i64 %vl) @@ -4904,8 +4904,8 @@ ; CHECK-LABEL: test_vlseg6_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* %base, i64 %vl) @@ -4917,15 +4917,15 @@ ; CHECK-LABEL: test_vlseg6_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlseg6e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg6e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlseg6e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlseg6.nxv2f16(half* %base, i64 %vl) @@ -4942,8 +4942,8 @@ ; CHECK-LABEL: test_vlseg7_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* %base, i64 %vl) @@ -4955,16 +4955,16 @@ ; CHECK-LABEL: test_vlseg7_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlseg7e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg7e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlseg7e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlseg7.nxv2f16(half* %base, i64 %vl) @@ -4981,8 +4981,8 @@ ; CHECK-LABEL: test_vlseg8_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* %base, i64 %vl) @@ -4994,17 +4994,17 @@ ; CHECK-LABEL: test_vlseg8_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e16,mf2,ta,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0) -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlseg8e16.v v7, (a0) +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vlseg8e16.v v15, (a0), v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlseg8e16.v v7, (a0), v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlseg8.nxv2f16(half* %base, i64 %vl) @@ -5021,8 +5021,8 @@ ; CHECK-LABEL: test_vlseg2_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32(float* %base, i64 %vl) @@ -5034,11 +5034,11 @@ ; CHECK-LABEL: test_vlseg2_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlseg2e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg2e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlseg2e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlseg2.nxv4f32(float* %base, i64 %vl) @@ -5055,8 +5055,8 @@ ; CHECK-LABEL: test_vlseg3_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32(float* %base, i64 %vl) @@ -5068,12 +5068,12 @@ ; CHECK-LABEL: test_vlseg3_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlseg3e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg3e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlseg3e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlseg3.nxv4f32(float* %base, i64 %vl) @@ -5090,8 +5090,8 @@ ; CHECK-LABEL: test_vlseg4_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0) -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e32.v v6, (a0) +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32(float* %base, i64 %vl) @@ -5103,13 +5103,13 @@ ; CHECK-LABEL: test_vlseg4_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a1, e32,m2,ta,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0) -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlseg4e32.v v6, (a0) +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vlseg4e32.v v14, (a0), v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlseg4e32.v v6, (a0), v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlseg4.nxv4f32(float* %base, i64 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll @@ -9,8 +9,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i32 %offset, i32 %vl) @@ -22,11 +22,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i32 %offset, i32 %vl) @@ -43,8 +43,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -56,11 +56,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -77,8 +77,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -90,12 +90,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -112,8 +112,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -125,13 +125,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -148,8 +148,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -161,14 +161,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -185,8 +185,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -198,15 +198,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -223,8 +223,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -236,16 +236,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -262,8 +262,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -275,17 +275,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i32 %offset, i32 %vl) @@ -302,8 +302,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg2e8.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i32 %offset, i32 %vl) @@ -315,11 +315,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg2e8.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,tu,mu -; CHECK-NEXT: vlsseg2e8.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i32 %offset, i32 %vl) @@ -336,8 +336,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg3e8.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i32 %offset, i32 %vl) @@ -349,12 +349,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg3e8.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,tu,mu -; CHECK-NEXT: vlsseg3e8.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i32 %offset, i32 %vl) @@ -371,8 +371,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg4e8.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i32 %offset, i32 %vl) @@ -384,13 +384,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg4e8.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,tu,mu -; CHECK-NEXT: vlsseg4e8.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i32 %offset, i32 %vl) @@ -407,8 +407,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -420,11 +420,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -441,8 +441,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -454,12 +454,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -476,8 +476,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -489,13 +489,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -512,8 +512,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -525,14 +525,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -549,8 +549,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -562,15 +562,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -587,8 +587,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -600,16 +600,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -626,8 +626,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -639,17 +639,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i32 %offset, i32 %vl) @@ -666,8 +666,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -679,11 +679,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -700,8 +700,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -713,12 +713,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -735,8 +735,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -748,13 +748,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -771,8 +771,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -784,14 +784,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -808,8 +808,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -821,15 +821,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -846,8 +846,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -859,16 +859,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -885,8 +885,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -898,17 +898,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i32 %offset, i32 %vl) @@ -925,8 +925,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -938,11 +938,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -959,8 +959,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -972,12 +972,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -994,8 +994,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1007,13 +1007,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1030,8 +1030,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1043,14 +1043,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1067,8 +1067,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1080,15 +1080,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1105,8 +1105,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1118,16 +1118,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1144,8 +1144,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1157,17 +1157,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32* %base, i32 %offset, i32 %vl) @@ -1184,8 +1184,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16(i16* %base, i32 %offset, i32 %vl) @@ -1197,11 +1197,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16(i16* %base, i32 %offset, i32 %vl) @@ -1218,8 +1218,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16(i16* %base, i32 %offset, i32 %vl) @@ -1231,12 +1231,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16(i16* %base, i32 %offset, i32 %vl) @@ -1253,8 +1253,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16* %base, i32 %offset, i32 %vl) @@ -1266,13 +1266,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16* %base, i32 %offset, i32 %vl) @@ -1289,8 +1289,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1302,11 +1302,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1323,8 +1323,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1336,12 +1336,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1358,8 +1358,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1371,13 +1371,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1394,8 +1394,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1407,14 +1407,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1431,8 +1431,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1444,15 +1444,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1469,8 +1469,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1482,16 +1482,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1508,8 +1508,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1521,17 +1521,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8* %base, i32 %offset, i32 %vl) @@ -1548,8 +1548,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32(i32* %base, i32 %offset, i32 %vl) @@ -1561,11 +1561,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m4,ta,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,tu,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32(i32* %base, i32 %offset, i32 %vl) @@ -1582,8 +1582,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1595,11 +1595,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1616,8 +1616,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1629,12 +1629,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1651,8 +1651,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1664,13 +1664,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1687,8 +1687,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1700,14 +1700,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1724,8 +1724,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1737,15 +1737,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1762,8 +1762,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1775,16 +1775,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1801,8 +1801,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1814,17 +1814,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8* %base, i32 %offset, i32 %vl) @@ -1841,8 +1841,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -1854,11 +1854,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -1875,8 +1875,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -1888,12 +1888,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -1910,8 +1910,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -1923,13 +1923,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -1946,8 +1946,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -1959,14 +1959,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -1983,8 +1983,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -1996,15 +1996,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -2021,8 +2021,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -2034,16 +2034,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -2060,8 +2060,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -2073,17 +2073,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16* %base, i32 %offset, i32 %vl) @@ -2100,8 +2100,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu -; CHECK-NEXT: vlsseg2e8.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8(i8* %base, i32 %offset, i32 %vl) @@ -2113,11 +2113,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m4,ta,mu -; CHECK-NEXT: vlsseg2e8.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e8,m4,tu,mu -; CHECK-NEXT: vlsseg2e8.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8(i8* %base, i32 %offset, i32 %vl) @@ -2134,8 +2134,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2147,11 +2147,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2168,8 +2168,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2181,12 +2181,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2203,8 +2203,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2216,13 +2216,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2239,8 +2239,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2252,14 +2252,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2276,8 +2276,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2289,15 +2289,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2314,8 +2314,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2327,16 +2327,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2353,8 +2353,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2366,17 +2366,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8* %base, i32 %offset, i32 %vl) @@ -2393,8 +2393,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2406,11 +2406,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2427,8 +2427,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2440,12 +2440,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2462,8 +2462,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2475,13 +2475,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2498,8 +2498,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2511,14 +2511,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2535,8 +2535,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2548,15 +2548,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2573,8 +2573,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2586,16 +2586,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2612,8 +2612,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2625,17 +2625,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16* %base, i32 %offset, i32 %vl) @@ -2652,8 +2652,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32(i32* %base, i32 %offset, i32 %vl) @@ -2665,11 +2665,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32(i32* %base, i32 %offset, i32 %vl) @@ -2686,8 +2686,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32(i32* %base, i32 %offset, i32 %vl) @@ -2699,12 +2699,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32(i32* %base, i32 %offset, i32 %vl) @@ -2721,8 +2721,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32* %base, i32 %offset, i32 %vl) @@ -2734,13 +2734,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32* %base, i32 %offset, i32 %vl) @@ -2757,8 +2757,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16(half* %base, i32 %offset, i32 %vl) @@ -2770,11 +2770,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16(half* %base, i32 %offset, i32 %vl) @@ -2791,8 +2791,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu -; CHECK-NEXT: vlsseg2e64.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64(double* %base, i32 %offset, i32 %vl) @@ -2804,11 +2804,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu -; CHECK-NEXT: vlsseg2e64.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e64,m4,tu,mu -; CHECK-NEXT: vlsseg2e64.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64(double* %base, i32 %offset, i32 %vl) @@ -2825,8 +2825,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg2e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -2838,11 +2838,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg2e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg2e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -2859,8 +2859,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg3e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -2872,12 +2872,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg3e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg3e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -2894,8 +2894,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg4e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -2907,13 +2907,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg4e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg4e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -2930,8 +2930,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg5e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -2943,14 +2943,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg5e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg5e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -2967,8 +2967,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg6e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -2980,15 +2980,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg6e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg6e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -3005,8 +3005,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg7e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -3018,16 +3018,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg7e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg7e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -3044,8 +3044,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg8e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -3057,17 +3057,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg8e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg8e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double* %base, i32 %offset, i32 %vl) @@ -3084,8 +3084,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3097,11 +3097,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3118,8 +3118,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3131,12 +3131,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3153,8 +3153,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3166,13 +3166,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3189,8 +3189,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3202,14 +3202,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3226,8 +3226,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3239,15 +3239,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3264,8 +3264,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3277,16 +3277,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3303,8 +3303,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3316,17 +3316,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float* %base, i32 %offset, i32 %vl) @@ -3343,8 +3343,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3356,11 +3356,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3377,8 +3377,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3390,12 +3390,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3412,8 +3412,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3425,13 +3425,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3448,8 +3448,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3461,14 +3461,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3485,8 +3485,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3498,15 +3498,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3523,8 +3523,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3536,16 +3536,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3562,8 +3562,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3575,17 +3575,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half* %base, i32 %offset, i32 %vl) @@ -3602,8 +3602,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3615,11 +3615,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3636,8 +3636,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3649,12 +3649,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3671,8 +3671,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3684,13 +3684,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3707,8 +3707,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3720,14 +3720,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3744,8 +3744,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3757,15 +3757,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3782,8 +3782,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3795,16 +3795,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3821,8 +3821,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3834,17 +3834,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float* %base, i32 %offset, i32 %vl) @@ -3861,8 +3861,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16(half* %base, i32 %offset, i32 %vl) @@ -3874,11 +3874,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16(half* %base, i32 %offset, i32 %vl) @@ -3895,8 +3895,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16(half* %base, i32 %offset, i32 %vl) @@ -3908,12 +3908,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16(half* %base, i32 %offset, i32 %vl) @@ -3930,8 +3930,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16(half* %base, i32 %offset, i32 %vl) @@ -3943,13 +3943,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16(half* %base, i32 %offset, i32 %vl) @@ -3966,8 +3966,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32(float* %base, i32 %offset, i32 %vl) @@ -3979,11 +3979,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m4,ta,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,tu,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32(float* %base, i32 %offset, i32 %vl) @@ -4000,8 +4000,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg2e64.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64(double* %base, i32 %offset, i32 %vl) @@ -4013,11 +4013,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg2e64.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu -; CHECK-NEXT: vlsseg2e64.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64(double* %base, i32 %offset, i32 %vl) @@ -4034,8 +4034,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg3e64.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64(double* %base, i32 %offset, i32 %vl) @@ -4047,12 +4047,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg3e64.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu -; CHECK-NEXT: vlsseg3e64.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64(double* %base, i32 %offset, i32 %vl) @@ -4069,8 +4069,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg4e64.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64(double* %base, i32 %offset, i32 %vl) @@ -4082,13 +4082,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg4e64.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu -; CHECK-NEXT: vlsseg4e64.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64(double* %base, i32 %offset, i32 %vl) @@ -4105,8 +4105,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4118,11 +4118,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4139,8 +4139,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4152,12 +4152,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4174,8 +4174,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4187,13 +4187,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4210,8 +4210,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4223,14 +4223,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4247,8 +4247,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4260,15 +4260,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4285,8 +4285,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4298,16 +4298,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4324,8 +4324,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4337,17 +4337,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half* %base, i32 %offset, i32 %vl) @@ -4364,8 +4364,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4377,11 +4377,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4398,8 +4398,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4411,12 +4411,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4433,8 +4433,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4446,13 +4446,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4469,8 +4469,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4482,14 +4482,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4506,8 +4506,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4519,15 +4519,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4544,8 +4544,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4557,16 +4557,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4583,8 +4583,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4596,17 +4596,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half* %base, i32 %offset, i32 %vl) @@ -4623,8 +4623,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32(float* %base, i32 %offset, i32 %vl) @@ -4636,11 +4636,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32(float* %base, i32 %offset, i32 %vl) @@ -4657,8 +4657,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32(float* %base, i32 %offset, i32 %vl) @@ -4670,12 +4670,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32(float* %base, i32 %offset, i32 %vl) @@ -4692,8 +4692,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32(float* %base, i32 %offset, i32 %vl) @@ -4705,13 +4705,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32(float* %base, i32 %offset, i32 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll @@ -9,8 +9,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i64 %offset, i64 %vl) @@ -22,11 +22,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i64 %offset, i64 %vl) @@ -43,8 +43,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32(i32* %base, i64 %offset, i64 %vl) @@ -56,11 +56,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i32(i32* %base, i64 %offset, i64 %vl) @@ -77,8 +77,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32(i32* %base, i64 %offset, i64 %vl) @@ -90,12 +90,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i32(i32* %base, i64 %offset, i64 %vl) @@ -112,8 +112,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32* %base, i64 %offset, i64 %vl) @@ -125,13 +125,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i32(i32* %base, i64 %offset, i64 %vl) @@ -148,8 +148,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg2e8.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i64 %offset, i64 %vl) @@ -161,11 +161,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg2e8.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,tu,mu -; CHECK-NEXT: vlsseg2e8.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e8.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16i8(i8* %base, i64 %offset, i64 %vl) @@ -182,8 +182,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg3e8.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i64 %offset, i64 %vl) @@ -195,12 +195,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg3e8.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,tu,mu -; CHECK-NEXT: vlsseg3e8.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e8.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv16i8(i8* %base, i64 %offset, i64 %vl) @@ -217,8 +217,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg4e8.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i64 %offset, i64 %vl) @@ -230,13 +230,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m2,ta,mu -; CHECK-NEXT: vlsseg4e8.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,tu,mu -; CHECK-NEXT: vlsseg4e8.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e8.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv16i8(i8* %base, i64 %offset, i64 %vl) @@ -253,8 +253,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg2e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -266,11 +266,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg2e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg2e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -287,8 +287,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg3e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -300,12 +300,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg3e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg3e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -322,8 +322,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg4e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -335,13 +335,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg4e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg4e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -358,8 +358,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg5e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -371,14 +371,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg5e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg5e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -395,8 +395,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg6e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -408,15 +408,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg6e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg6e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -433,8 +433,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg7e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -446,16 +446,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg7e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg7e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -472,8 +472,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg8e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -485,17 +485,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg8e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg8e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i64(i64* %base, i64 %offset, i64 %vl) @@ -512,8 +512,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -525,11 +525,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -546,8 +546,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -559,12 +559,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -581,8 +581,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -594,13 +594,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -617,8 +617,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -630,14 +630,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -654,8 +654,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -667,15 +667,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -692,8 +692,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -705,16 +705,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -731,8 +731,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -744,17 +744,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i32(i32* %base, i64 %offset, i64 %vl) @@ -771,8 +771,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16(i16* %base, i64 %offset, i64 %vl) @@ -784,11 +784,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i16(i16* %base, i64 %offset, i64 %vl) @@ -805,8 +805,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16(i16* %base, i64 %offset, i64 %vl) @@ -818,12 +818,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i16(i16* %base, i64 %offset, i64 %vl) @@ -840,8 +840,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16* %base, i64 %offset, i64 %vl) @@ -853,13 +853,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i16(i16* %base, i64 %offset, i64 %vl) @@ -876,8 +876,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -889,11 +889,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -910,8 +910,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -923,12 +923,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -945,8 +945,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -958,13 +958,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -981,8 +981,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -994,14 +994,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -1018,8 +1018,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -1031,15 +1031,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -1056,8 +1056,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -1069,16 +1069,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -1095,8 +1095,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -1108,17 +1108,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf2,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,tu,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i8(i8* %base, i64 %offset, i64 %vl) @@ -1135,8 +1135,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1148,11 +1148,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1169,8 +1169,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1182,12 +1182,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1204,8 +1204,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1217,13 +1217,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1240,8 +1240,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1253,14 +1253,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1277,8 +1277,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1290,15 +1290,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1315,8 +1315,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1328,16 +1328,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1354,8 +1354,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1367,17 +1367,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i16(i16* %base, i64 %offset, i64 %vl) @@ -1394,8 +1394,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1407,11 +1407,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1428,8 +1428,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1441,12 +1441,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1463,8 +1463,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1476,13 +1476,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1499,8 +1499,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1512,14 +1512,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1536,8 +1536,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1549,15 +1549,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1574,8 +1574,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1587,16 +1587,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1613,8 +1613,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1626,17 +1626,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i32(i32* %base, i64 %offset, i64 %vl) @@ -1653,8 +1653,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1666,11 +1666,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1687,8 +1687,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1700,12 +1700,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1722,8 +1722,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1735,13 +1735,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1758,8 +1758,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1771,14 +1771,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1795,8 +1795,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1808,15 +1808,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1833,8 +1833,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1846,16 +1846,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1872,8 +1872,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1885,17 +1885,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m1,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,tu,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv8i8(i8* %base, i64 %offset, i64 %vl) @@ -1912,8 +1912,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu -; CHECK-NEXT: vlsseg2e64.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i64(i64* %base, i64 %offset, i64 %vl) @@ -1925,11 +1925,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu -; CHECK-NEXT: vlsseg2e64.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e64,m4,tu,mu -; CHECK-NEXT: vlsseg2e64.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i64(i64* %base, i64 %offset, i64 %vl) @@ -1946,8 +1946,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -1959,11 +1959,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -1980,8 +1980,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -1993,12 +1993,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2015,8 +2015,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2028,13 +2028,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2051,8 +2051,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2064,14 +2064,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2088,8 +2088,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2101,15 +2101,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2126,8 +2126,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2139,16 +2139,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2165,8 +2165,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2178,17 +2178,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4i16(i16* %base, i64 %offset, i64 %vl) @@ -2205,8 +2205,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2218,11 +2218,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2239,8 +2239,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2252,12 +2252,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2274,8 +2274,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2287,13 +2287,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2310,8 +2310,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2323,14 +2323,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2347,8 +2347,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2360,15 +2360,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2385,8 +2385,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2398,16 +2398,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2424,8 +2424,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2437,17 +2437,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf8,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,tu,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1i8(i8* %base, i64 %offset, i64 %vl) @@ -2464,8 +2464,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2477,11 +2477,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg2e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2498,8 +2498,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2511,12 +2511,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg3e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2533,8 +2533,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2546,13 +2546,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg4e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2569,8 +2569,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2582,14 +2582,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg5e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2606,8 +2606,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2619,15 +2619,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg6e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2644,8 +2644,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2657,16 +2657,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg7e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2683,8 +2683,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2696,17 +2696,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,mf4,ta,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,tu,mu -; CHECK-NEXT: vlsseg8e8.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e8.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i8(i8* %base, i64 %offset, i64 %vl) @@ -2723,8 +2723,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32(i32* %base, i64 %offset, i64 %vl) @@ -2736,11 +2736,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m4,ta,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,tu,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8i32(i32* %base, i64 %offset, i64 %vl) @@ -2757,8 +2757,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu -; CHECK-NEXT: vlsseg2e8.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8(i8* %base, i64 %offset, i64 %vl) @@ -2770,11 +2770,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e8,m4,ta,mu -; CHECK-NEXT: vlsseg2e8.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e8,m4,tu,mu -; CHECK-NEXT: vlsseg2e8.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e8.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv32i8(i8* %base, i64 %offset, i64 %vl) @@ -2791,8 +2791,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2804,11 +2804,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2825,8 +2825,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2838,12 +2838,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2860,8 +2860,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2873,13 +2873,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2896,8 +2896,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2909,14 +2909,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2933,8 +2933,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2946,15 +2946,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2971,8 +2971,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -2984,16 +2984,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -3010,8 +3010,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -3023,17 +3023,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2i16(i16* %base, i64 %offset, i64 %vl) @@ -3050,8 +3050,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg2e64.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i64(i64* %base, i64 %offset, i64 %vl) @@ -3063,11 +3063,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg2e64.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu -; CHECK-NEXT: vlsseg2e64.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2i64(i64* %base, i64 %offset, i64 %vl) @@ -3084,8 +3084,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg3e64.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i64(i64* %base, i64 %offset, i64 %vl) @@ -3097,12 +3097,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg3e64.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu -; CHECK-NEXT: vlsseg3e64.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2i64(i64* %base, i64 %offset, i64 %vl) @@ -3119,8 +3119,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg4e64.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i64(i64* %base, i64 %offset, i64 %vl) @@ -3132,13 +3132,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg4e64.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu -; CHECK-NEXT: vlsseg4e64.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2i64(i64* %base, i64 %offset, i64 %vl) @@ -3155,8 +3155,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16(half* %base, i64 %offset, i64 %vl) @@ -3168,11 +3168,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu -; CHECK-NEXT: vlsseg2e16.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv16f16(half* %base, i64 %offset, i64 %vl) @@ -3189,8 +3189,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu -; CHECK-NEXT: vlsseg2e64.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64(double* %base, i64 %offset, i64 %vl) @@ -3202,11 +3202,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m4,ta,mu -; CHECK-NEXT: vlsseg2e64.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e64,m4,tu,mu -; CHECK-NEXT: vlsseg2e64.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e64.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f64(double* %base, i64 %offset, i64 %vl) @@ -3223,8 +3223,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg2e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3236,11 +3236,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg2e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg2e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3257,8 +3257,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg3e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3270,12 +3270,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg3e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg3e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3292,8 +3292,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg4e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3305,13 +3305,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg4e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg4e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3328,8 +3328,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg5e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3341,14 +3341,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg5e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg5e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3365,8 +3365,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg6e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3378,15 +3378,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg6e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg6e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3403,8 +3403,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg7e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3416,16 +3416,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg7e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg7e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3442,8 +3442,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg8e64.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3455,17 +3455,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m1,ta,mu -; CHECK-NEXT: vlsseg8e64.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,tu,mu -; CHECK-NEXT: vlsseg8e64.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e64.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f64(double* %base, i64 %offset, i64 %vl) @@ -3482,8 +3482,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3495,11 +3495,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3516,8 +3516,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3529,12 +3529,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3551,8 +3551,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3564,13 +3564,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3587,8 +3587,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3600,14 +3600,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3624,8 +3624,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3637,15 +3637,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3662,8 +3662,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3675,16 +3675,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3701,8 +3701,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3714,17 +3714,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m1,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,tu,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f32(float* %base, i64 %offset, i64 %vl) @@ -3741,8 +3741,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3754,11 +3754,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3775,8 +3775,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3788,12 +3788,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3810,8 +3810,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3823,13 +3823,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3846,8 +3846,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3859,14 +3859,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3883,8 +3883,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3896,15 +3896,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3921,8 +3921,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3934,16 +3934,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3960,8 +3960,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -3973,17 +3973,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf4,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f16(half* %base, i64 %offset, i64 %vl) @@ -4000,8 +4000,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4013,11 +4013,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg2e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4034,8 +4034,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4047,12 +4047,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg3e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4069,8 +4069,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4082,13 +4082,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg4e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4105,8 +4105,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4118,14 +4118,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg5e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4142,8 +4142,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4155,15 +4155,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg6e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4180,8 +4180,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4193,16 +4193,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg7e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4219,8 +4219,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4232,17 +4232,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,mf2,ta,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,tu,mu -; CHECK-NEXT: vlsseg8e32.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e32.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv1f32(float* %base, i64 %offset, i64 %vl) @@ -4259,8 +4259,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16(half* %base, i64 %offset, i64 %vl) @@ -4272,11 +4272,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg2e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f16(half* %base, i64 %offset, i64 %vl) @@ -4293,8 +4293,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16(half* %base, i64 %offset, i64 %vl) @@ -4306,12 +4306,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg3e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv8f16(half* %base, i64 %offset, i64 %vl) @@ -4328,8 +4328,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16(half* %base, i64 %offset, i64 %vl) @@ -4341,13 +4341,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,tu,mu -; CHECK-NEXT: vlsseg4e16.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e16.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv8f16(half* %base, i64 %offset, i64 %vl) @@ -4364,8 +4364,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1 -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32(float* %base, i64 %offset, i64 %vl) @@ -4377,11 +4377,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m4,ta,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1 -; CHECK-NEXT: vmv4r.v v16, v12 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1 +; CHECK-NEXT: vmv4r.v v8, v4 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,tu,mu -; CHECK-NEXT: vlsseg2e32.v v12, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 killed $v12m4_v16m4 +; CHECK-NEXT: vlsseg2e32.v v4, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv8f32(float* %base, i64 %offset, i64 %vl) @@ -4398,8 +4398,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg2e64.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64(double* %base, i64 %offset, i64 %vl) @@ -4411,11 +4411,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg2e64.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu -; CHECK-NEXT: vlsseg2e64.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e64.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f64(double* %base, i64 %offset, i64 %vl) @@ -4432,8 +4432,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg3e64.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64(double* %base, i64 %offset, i64 %vl) @@ -4445,12 +4445,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg3e64.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu -; CHECK-NEXT: vlsseg3e64.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e64.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f64(double* %base, i64 %offset, i64 %vl) @@ -4467,8 +4467,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg4e64.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64(double* %base, i64 %offset, i64 %vl) @@ -4480,13 +4480,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e64,m2,ta,mu -; CHECK-NEXT: vlsseg4e64.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,tu,mu -; CHECK-NEXT: vlsseg4e64.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e64.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f64(double* %base, i64 %offset, i64 %vl) @@ -4503,8 +4503,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4516,11 +4516,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4537,8 +4537,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4550,12 +4550,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4572,8 +4572,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4585,13 +4585,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4608,8 +4608,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4621,14 +4621,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4645,8 +4645,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4658,15 +4658,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4683,8 +4683,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4696,16 +4696,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4722,8 +4722,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4735,17 +4735,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,m1,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv4f16(half* %base, i64 %offset, i64 %vl) @@ -4762,8 +4762,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4775,11 +4775,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg2e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16 +; CHECK-NEXT: vlsseg2e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4796,8 +4796,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4809,12 +4809,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg3e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17 +; CHECK-NEXT: vlsseg3e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4831,8 +4831,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4844,13 +4844,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg4e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18 +; CHECK-NEXT: vlsseg4e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4867,8 +4867,8 @@ ; CHECK-LABEL: test_vlsseg5_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4880,14 +4880,14 @@ ; CHECK-LABEL: test_vlsseg5_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg5e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19 +; CHECK-NEXT: vlsseg5e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,} @llvm.riscv.vlsseg5.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4904,8 +4904,8 @@ ; CHECK-LABEL: test_vlsseg6_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4917,15 +4917,15 @@ ; CHECK-LABEL: test_vlsseg6_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg6e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20 +; CHECK-NEXT: vlsseg6e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,} @llvm.riscv.vlsseg6.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4942,8 +4942,8 @@ ; CHECK-LABEL: test_vlsseg7_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4955,16 +4955,16 @@ ; CHECK-LABEL: test_vlsseg7_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg7e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21 +; CHECK-NEXT: vlsseg7e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,} @llvm.riscv.vlsseg7.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4981,8 +4981,8 @@ ; CHECK-LABEL: test_vlsseg8_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -4994,17 +4994,17 @@ ; CHECK-LABEL: test_vlsseg8_mask_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e16,mf2,ta,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1 -; CHECK-NEXT: vmv1r.v v16, v15 -; CHECK-NEXT: vmv1r.v v17, v15 -; CHECK-NEXT: vmv1r.v v18, v15 -; CHECK-NEXT: vmv1r.v v19, v15 -; CHECK-NEXT: vmv1r.v v20, v15 -; CHECK-NEXT: vmv1r.v v21, v15 -; CHECK-NEXT: vmv1r.v v22, v15 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1 +; CHECK-NEXT: vmv1r.v v8, v7 +; CHECK-NEXT: vmv1r.v v9, v7 +; CHECK-NEXT: vmv1r.v v10, v7 +; CHECK-NEXT: vmv1r.v v11, v7 +; CHECK-NEXT: vmv1r.v v12, v7 +; CHECK-NEXT: vmv1r.v v13, v7 +; CHECK-NEXT: vmv1r.v v14, v7 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,tu,mu -; CHECK-NEXT: vlsseg8e16.v v15, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16 killed $v16 killed $v15_v16_v17_v18_v19_v20_v21_v22 +; CHECK-NEXT: vlsseg8e16.v v7, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14 ; CHECK-NEXT: ret entry: %0 = tail call {,,,,,,,} @llvm.riscv.vlsseg8.nxv2f16(half* %base, i64 %offset, i64 %vl) @@ -5021,8 +5021,8 @@ ; CHECK-LABEL: test_vlsseg2_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32(float* %base, i64 %offset, i64 %vl) @@ -5034,11 +5034,11 @@ ; CHECK-LABEL: test_vlsseg2_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg2e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2 +; CHECK-NEXT: vlsseg2e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2 ; CHECK-NEXT: ret entry: %0 = tail call {,} @llvm.riscv.vlsseg2.nxv4f32(float* %base, i64 %offset, i64 %vl) @@ -5055,8 +5055,8 @@ ; CHECK-LABEL: test_vlsseg3_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32(float* %base, i64 %offset, i64 %vl) @@ -5068,12 +5068,12 @@ ; CHECK-LABEL: test_vlsseg3_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg3e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2 +; CHECK-NEXT: vlsseg3e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,} @llvm.riscv.vlsseg3.nxv4f32(float* %base, i64 %offset, i64 %vl) @@ -5090,8 +5090,8 @@ ; CHECK-LABEL: test_vlsseg4_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1 -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32(float* %base, i64 %offset, i64 %vl) @@ -5103,13 +5103,13 @@ ; CHECK-LABEL: test_vlsseg4_mask_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, a2, e32,m2,ta,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1 -; CHECK-NEXT: vmv2r.v v16, v14 -; CHECK-NEXT: vmv2r.v v18, v14 -; CHECK-NEXT: vmv2r.v v20, v14 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1 +; CHECK-NEXT: vmv2r.v v8, v6 +; CHECK-NEXT: vmv2r.v v10, v6 +; CHECK-NEXT: vmv2r.v v12, v6 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,tu,mu -; CHECK-NEXT: vlsseg4e32.v v14, (a0), a1, v0.t -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 killed $v14m2_v16m2_v18m2_v20m2 +; CHECK-NEXT: vlsseg4e32.v v6, (a0), a1, v0.t +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2 ; CHECK-NEXT: ret entry: %0 = tail call {,,,} @llvm.riscv.vlsseg4.nxv4f32(float* %base, i64 %offset, i64 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmacc.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv16i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv32i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv16i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i32.nxv1i32( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i32.nxv2i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i32.nxv4i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i32.nxv8i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i8.i8( %0, i8 %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i8.i8( %0, i8 %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i8.i8( %0, i8 %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i8.i8( %0, i8 %1, @@ -721,10 +790,12 @@ i32); define @intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i8.i8( %0, i8 %1, @@ -742,10 +813,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i8.i8( %0, i8 %1, @@ -763,10 +836,12 @@ i32); define @intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i8.i8( %0, i8 %1, @@ -784,10 +859,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i8.i8( %0, i8 %1, @@ -805,10 +882,12 @@ i32); define @intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv16i8.i8( %0, i8 %1, @@ -826,10 +905,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv16i8.i8( %0, i8 %1, @@ -847,10 +928,12 @@ i32); define @intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv32i8.i8( %0, i8 %1, @@ -868,10 +951,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv32i8.i8( %0, i8 %1, @@ -889,10 +974,12 @@ i32); define @intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i16.i16( %0, i16 %1, @@ -910,10 +997,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i16.i16( %0, i16 %1, @@ -931,10 +1020,12 @@ i32); define @intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i16.i16( %0, i16 %1, @@ -952,10 +1043,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i16.i16( %0, i16 %1, @@ -973,10 +1066,12 @@ i32); define @intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i16.i16( %0, i16 %1, @@ -994,10 +1089,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i16.i16( %0, i16 %1, @@ -1015,10 +1112,12 @@ i32); define @intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i16.i16( %0, i16 %1, @@ -1036,10 +1135,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i16.i16( %0, i16 %1, @@ -1057,10 +1158,12 @@ i32); define @intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv16i16.i16( %0, i16 %1, @@ -1078,10 +1181,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv16i16.i16( %0, i16 %1, @@ -1099,10 +1204,12 @@ i32); define @intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i32.i32( %0, i32 %1, @@ -1120,10 +1227,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i32.i32( %0, i32 %1, @@ -1141,10 +1250,12 @@ i32); define @intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i32.i32( %0, i32 %1, @@ -1162,10 +1273,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i32.i32( %0, i32 %1, @@ -1183,10 +1296,12 @@ i32); define @intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i32.i32( %0, i32 %1, @@ -1204,10 +1319,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i32.i32( %0, i32 %1, @@ -1225,10 +1342,12 @@ i32); define @intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1365,12 @@ i32); define @intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i32.i32( %0, i32 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmacc.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv16i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv32i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv16i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i32.nxv1i32( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i32.nxv2i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i32.nxv4i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i32.nxv8i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vmacc_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i64.nxv1i64( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vmacc_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i64.nxv2i64( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmacc.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vmacc_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i64.nxv4i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmacc.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i8.i8( %0, i8 %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i8.i8( %0, i8 %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i8.i8( %0, i8 %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i8.i8( %0, i8 %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i8.i8( %0, i8 %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i8.i8( %0, i8 %1, @@ -889,10 +974,12 @@ i64); define @intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i8.i8( %0, i8 %1, @@ -910,10 +997,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i8.i8( %0, i8 %1, @@ -931,10 +1020,12 @@ i64); define @intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv16i8.i8( %0, i8 %1, @@ -952,10 +1043,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv16i8.i8( %0, i8 %1, @@ -973,10 +1066,12 @@ i64); define @intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv32i8.i8( %0, i8 %1, @@ -994,10 +1089,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv32i8.i8( %0, i8 %1, @@ -1015,10 +1112,12 @@ i64); define @intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i16.i16( %0, i16 %1, @@ -1036,10 +1135,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i16.i16( %0, i16 %1, @@ -1057,10 +1158,12 @@ i64); define @intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i16.i16( %0, i16 %1, @@ -1078,10 +1181,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i16.i16( %0, i16 %1, @@ -1099,10 +1204,12 @@ i64); define @intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i16.i16( %0, i16 %1, @@ -1120,10 +1227,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i16.i16( %0, i16 %1, @@ -1141,10 +1250,12 @@ i64); define @intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i16.i16( %0, i16 %1, @@ -1162,10 +1273,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i16.i16( %0, i16 %1, @@ -1183,10 +1296,12 @@ i64); define @intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv16i16.i16( %0, i16 %1, @@ -1204,10 +1319,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv16i16.i16( %0, i16 %1, @@ -1225,10 +1342,12 @@ i64); define @intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i32.i32( %0, i32 %1, @@ -1246,10 +1365,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i32.i32( %0, i32 %1, @@ -1267,10 +1388,12 @@ i64); define @intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i32.i32( %0, i32 %1, @@ -1288,10 +1411,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i32.i32( %0, i32 %1, @@ -1309,10 +1434,12 @@ i64); define @intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i32.i32( %0, i32 %1, @@ -1330,10 +1457,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i32.i32( %0, i32 %1, @@ -1351,10 +1480,12 @@ i64); define @intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv8i32.i32( %0, i32 %1, @@ -1372,10 +1503,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv8i32.i32( %0, i32 %1, @@ -1393,10 +1526,12 @@ i64); define @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv1i64.i64( %0, i64 %1, @@ -1414,10 +1549,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv1i64.i64( %0, i64 %1, @@ -1435,10 +1572,12 @@ i64); define @intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv2i64.i64( %0, i64 %1, @@ -1456,10 +1595,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv2i64.i64( %0, i64 %1, @@ -1477,10 +1618,12 @@ i64); define @intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmacc.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1641,12 @@ i64); define @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmacc.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmacc.mask.nxv4i64.i64( %0, i64 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmadc.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmadc_vv_nxv1i1_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i8.nxv1i8( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmadc_vv_nxv2i1_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i8.nxv2i8( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmadc_vv_nxv4i1_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i8.nxv4i8( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmadc_vv_nxv8i1_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i8.nxv8i8( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmadc_vv_nxv16i1_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i8.nxv16i8( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmadc_vv_nxv32i1_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv32i1_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv32i1_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv32i8.nxv32i8( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmadc_vv_nxv64i1_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv64i1_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv64i1_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv64i8.nxv64i8( %0, %1, @@ -132,10 +147,12 @@ i32); define @intrinsic_vmadc_vv_nxv1i1_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i16.nxv1i16( %0, %1, @@ -150,10 +167,12 @@ i32); define @intrinsic_vmadc_vv_nxv2i1_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i16.nxv2i16( %0, %1, @@ -168,10 +187,12 @@ i32); define @intrinsic_vmadc_vv_nxv4i1_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i16.nxv4i16( %0, %1, @@ -186,10 +207,12 @@ i32); define @intrinsic_vmadc_vv_nxv8i1_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i16.nxv8i16( %0, %1, @@ -204,10 +227,12 @@ i32); define @intrinsic_vmadc_vv_nxv16i1_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i16.nxv16i16( %0, %1, @@ -222,10 +247,12 @@ i32); define @intrinsic_vmadc_vv_nxv32i1_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv32i1_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv32i1_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv32i16.nxv32i16( %0, %1, @@ -240,10 +267,12 @@ i32); define @intrinsic_vmadc_vv_nxv1i1_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i32.nxv1i32( %0, %1, @@ -258,10 +287,12 @@ i32); define @intrinsic_vmadc_vv_nxv2i1_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i32.nxv2i32( %0, %1, @@ -276,10 +307,12 @@ i32); define @intrinsic_vmadc_vv_nxv4i1_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i32.nxv4i32( %0, %1, @@ -294,10 +327,12 @@ i32); define @intrinsic_vmadc_vv_nxv8i1_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i32.nxv8i32( %0, %1, @@ -312,10 +347,12 @@ i32); define @intrinsic_vmadc_vv_nxv16i1_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i32.nxv16i32( %0, %1, @@ -330,10 +367,12 @@ i32); define @intrinsic_vmadc_vx_nxv1i1_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i8.i8( %0, i8 %1, @@ -348,10 +387,12 @@ i32); define @intrinsic_vmadc_vx_nxv2i1_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i8.i8( %0, i8 %1, @@ -366,10 +407,12 @@ i32); define @intrinsic_vmadc_vx_nxv4i1_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i8.i8( %0, i8 %1, @@ -384,10 +427,12 @@ i32); define @intrinsic_vmadc_vx_nxv8i1_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i8.i8( %0, i8 %1, @@ -402,10 +447,12 @@ i32); define @intrinsic_vmadc_vx_nxv16i1_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i8.i8( %0, i8 %1, @@ -420,10 +467,12 @@ i32); define @intrinsic_vmadc_vx_nxv32i1_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv32i8.i8( %0, i8 %1, @@ -438,10 +487,12 @@ i32); define @intrinsic_vmadc_vx_nxv64i1_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv64i8.i8( %0, i8 %1, @@ -456,10 +507,12 @@ i32); define @intrinsic_vmadc_vx_nxv1i1_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i16.i16( %0, i16 %1, @@ -474,10 +527,12 @@ i32); define @intrinsic_vmadc_vx_nxv2i1_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i16.i16( %0, i16 %1, @@ -492,10 +547,12 @@ i32); define @intrinsic_vmadc_vx_nxv4i1_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i16.i16( %0, i16 %1, @@ -510,10 +567,12 @@ i32); define @intrinsic_vmadc_vx_nxv8i1_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i16.i16( %0, i16 %1, @@ -528,10 +587,12 @@ i32); define @intrinsic_vmadc_vx_nxv16i1_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i16.i16( %0, i16 %1, @@ -546,10 +607,12 @@ i32); define @intrinsic_vmadc_vx_nxv32i1_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv32i16.i16( %0, i16 %1, @@ -564,10 +627,12 @@ i32); define @intrinsic_vmadc_vx_nxv1i1_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i32.i32( %0, i32 %1, @@ -582,10 +647,12 @@ i32); define @intrinsic_vmadc_vx_nxv2i1_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i32.i32( %0, i32 %1, @@ -600,10 +667,12 @@ i32); define @intrinsic_vmadc_vx_nxv4i1_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i32.i32( %0, i32 %1, @@ -618,10 +687,12 @@ i32); define @intrinsic_vmadc_vx_nxv8i1_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i32.i32( %0, i32 %1, @@ -636,10 +707,12 @@ i32); define @intrinsic_vmadc_vx_nxv16i1_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i32.i32( %0, i32 %1, @@ -649,10 +722,12 @@ } define @intrinsic_vmadc_vi_nxv1i1_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv1i8.i8( %0, i8 9, @@ -662,10 +737,12 @@ } define @intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv2i8.i8( %0, i8 -9, @@ -675,10 +752,12 @@ } define @intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv4i8.i8( %0, i8 9, @@ -688,10 +767,12 @@ } define @intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv8i8.i8( %0, i8 -9, @@ -701,10 +782,12 @@ } define @intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv16i8.i8( %0, i8 9, @@ -714,10 +797,12 @@ } define @intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv32i8.i8( %0, i8 -9, @@ -727,10 +812,12 @@ } define @intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv64i8.i8( %0, i8 9, @@ -740,10 +827,12 @@ } define @intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv1i16.i16( %0, i16 -9, @@ -753,10 +842,12 @@ } define @intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv2i16.i16( %0, i16 9, @@ -766,10 +857,12 @@ } define @intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv4i16.i16( %0, i16 -9, @@ -779,10 +872,12 @@ } define @intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv8i16.i16( %0, i16 9, @@ -792,10 +887,12 @@ } define @intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv16i16.i16( %0, i16 -9, @@ -805,10 +902,12 @@ } define @intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv32i16.i16( %0, i16 9, @@ -818,10 +917,12 @@ } define @intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv1i32.i32( %0, i32 -9, @@ -831,10 +932,12 @@ } define @intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv2i32.i32( %0, i32 9, @@ -844,10 +947,12 @@ } define @intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv4i32.i32( %0, i32 -9, @@ -857,10 +962,12 @@ } define @intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv8i32.i32( %0, i32 9, @@ -870,10 +977,12 @@ } define @intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv16i32.i32( %0, i32 -9, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmadc.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmadc_vv_nxv1i1_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i8.nxv1i8( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmadc_vv_nxv2i1_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i8.nxv2i8( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmadc_vv_nxv4i1_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i8.nxv4i8( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmadc_vv_nxv8i1_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i8.nxv8i8( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmadc_vv_nxv16i1_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i8.nxv16i8( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmadc_vv_nxv32i1_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv32i1_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv32i1_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv32i8.nxv32i8( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmadc_vv_nxv64i1_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv64i1_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv64i1_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv64i8.nxv64i8( %0, %1, @@ -132,10 +147,12 @@ i64); define @intrinsic_vmadc_vv_nxv1i1_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i16.nxv1i16( %0, %1, @@ -150,10 +167,12 @@ i64); define @intrinsic_vmadc_vv_nxv2i1_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i16.nxv2i16( %0, %1, @@ -168,10 +187,12 @@ i64); define @intrinsic_vmadc_vv_nxv4i1_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i16.nxv4i16( %0, %1, @@ -186,10 +207,12 @@ i64); define @intrinsic_vmadc_vv_nxv8i1_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i16.nxv8i16( %0, %1, @@ -204,10 +227,12 @@ i64); define @intrinsic_vmadc_vv_nxv16i1_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i16.nxv16i16( %0, %1, @@ -222,10 +247,12 @@ i64); define @intrinsic_vmadc_vv_nxv32i1_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv32i1_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv32i1_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv32i16.nxv32i16( %0, %1, @@ -240,10 +267,12 @@ i64); define @intrinsic_vmadc_vv_nxv1i1_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i32.nxv1i32( %0, %1, @@ -258,10 +287,12 @@ i64); define @intrinsic_vmadc_vv_nxv2i1_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i32.nxv2i32( %0, %1, @@ -276,10 +307,12 @@ i64); define @intrinsic_vmadc_vv_nxv4i1_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i32.nxv4i32( %0, %1, @@ -294,10 +327,12 @@ i64); define @intrinsic_vmadc_vv_nxv8i1_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i32.nxv8i32( %0, %1, @@ -312,10 +347,12 @@ i64); define @intrinsic_vmadc_vv_nxv16i1_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv16i1_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i32.nxv16i32( %0, %1, @@ -330,10 +367,12 @@ i64); define @intrinsic_vmadc_vv_nxv1i1_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv1i1_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i64.nxv1i64( %0, %1, @@ -348,10 +387,12 @@ i64); define @intrinsic_vmadc_vv_nxv2i1_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv2i1_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i64.nxv2i64( %0, %1, @@ -366,10 +407,12 @@ i64); define @intrinsic_vmadc_vv_nxv4i1_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv4i1_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i64.nxv4i64( %0, %1, @@ -384,10 +427,12 @@ i64); define @intrinsic_vmadc_vv_nxv8i1_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmadc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vv_nxv8i1_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmadc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i64.nxv8i64( %0, %1, @@ -402,10 +447,12 @@ i64); define @intrinsic_vmadc_vx_nxv1i1_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i8.i8( %0, i8 %1, @@ -420,10 +467,12 @@ i64); define @intrinsic_vmadc_vx_nxv2i1_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i8.i8( %0, i8 %1, @@ -438,10 +487,12 @@ i64); define @intrinsic_vmadc_vx_nxv4i1_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i8.i8( %0, i8 %1, @@ -456,10 +507,12 @@ i64); define @intrinsic_vmadc_vx_nxv8i1_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i8.i8( %0, i8 %1, @@ -474,10 +527,12 @@ i64); define @intrinsic_vmadc_vx_nxv16i1_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i8.i8( %0, i8 %1, @@ -492,10 +547,12 @@ i64); define @intrinsic_vmadc_vx_nxv32i1_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv32i8.i8( %0, i8 %1, @@ -510,10 +567,12 @@ i64); define @intrinsic_vmadc_vx_nxv64i1_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv64i8.i8( %0, i8 %1, @@ -528,10 +587,12 @@ i64); define @intrinsic_vmadc_vx_nxv1i1_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i16.i16( %0, i16 %1, @@ -546,10 +607,12 @@ i64); define @intrinsic_vmadc_vx_nxv2i1_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i16.i16( %0, i16 %1, @@ -564,10 +627,12 @@ i64); define @intrinsic_vmadc_vx_nxv4i1_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i16.i16( %0, i16 %1, @@ -582,10 +647,12 @@ i64); define @intrinsic_vmadc_vx_nxv8i1_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i16.i16( %0, i16 %1, @@ -600,10 +667,12 @@ i64); define @intrinsic_vmadc_vx_nxv16i1_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i16.i16( %0, i16 %1, @@ -618,10 +687,12 @@ i64); define @intrinsic_vmadc_vx_nxv32i1_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv32i16.i16( %0, i16 %1, @@ -636,10 +707,12 @@ i64); define @intrinsic_vmadc_vx_nxv1i1_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i32.i32( %0, i32 %1, @@ -654,10 +727,12 @@ i64); define @intrinsic_vmadc_vx_nxv2i1_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i32.i32( %0, i32 %1, @@ -672,10 +747,12 @@ i64); define @intrinsic_vmadc_vx_nxv4i1_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i32.i32( %0, i32 %1, @@ -690,10 +767,12 @@ i64); define @intrinsic_vmadc_vx_nxv8i1_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i32.i32( %0, i32 %1, @@ -708,10 +787,12 @@ i64); define @intrinsic_vmadc_vx_nxv16i1_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv16i32.i32( %0, i32 %1, @@ -726,10 +807,12 @@ i64); define @intrinsic_vmadc_vx_nxv1i1_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv1i1_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv1i64.i64( %0, i64 %1, @@ -744,10 +827,12 @@ i64); define @intrinsic_vmadc_vx_nxv2i1_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv2i1_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv2i64.i64( %0, i64 %1, @@ -762,10 +847,12 @@ i64); define @intrinsic_vmadc_vx_nxv4i1_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv4i1_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv4i64.i64( %0, i64 %1, @@ -780,10 +867,12 @@ i64); define @intrinsic_vmadc_vx_nxv8i1_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmadc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vx_nxv8i1_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmadc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmadc.nxv8i64.i64( %0, i64 %1, @@ -793,10 +882,12 @@ } define @intrinsic_vmadc_vi_nxv1i1_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv1i8.i8( %0, i8 9, @@ -806,10 +897,12 @@ } define @intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv2i8.i8( %0, i8 -9, @@ -819,10 +912,12 @@ } define @intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv4i8.i8( %0, i8 9, @@ -832,10 +927,12 @@ } define @intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv8i8.i8( %0, i8 -9, @@ -845,10 +942,12 @@ } define @intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv16i8.i8( %0, i8 9, @@ -858,10 +957,12 @@ } define @intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv32i8.i8( %0, i8 -9, @@ -871,10 +972,12 @@ } define @intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv64i8.i8( %0, i8 9, @@ -884,10 +987,12 @@ } define @intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv1i16.i16( %0, i16 -9, @@ -897,10 +1002,12 @@ } define @intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv2i16.i16( %0, i16 9, @@ -910,10 +1017,12 @@ } define @intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv4i16.i16( %0, i16 -9, @@ -923,10 +1032,12 @@ } define @intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv8i16.i16( %0, i16 9, @@ -936,10 +1047,12 @@ } define @intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv16i16.i16( %0, i16 -9, @@ -949,10 +1062,12 @@ } define @intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv32i16.i16( %0, i16 9, @@ -962,10 +1077,12 @@ } define @intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv1i32.i32( %0, i32 -9, @@ -975,10 +1092,12 @@ } define @intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv2i32.i32( %0, i32 9, @@ -988,10 +1107,12 @@ } define @intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv4i32.i32( %0, i32 -9, @@ -1001,10 +1122,12 @@ } define @intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv8i32.i32( %0, i32 9, @@ -1014,10 +1137,12 @@ } define @intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv16i32.i32( %0, i32 -9, @@ -1027,10 +1152,12 @@ } define @intrinsic_vmadc_vi_nxv1i1_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv1i1_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv1i64.i64( %0, i64 9, @@ -1040,10 +1167,12 @@ } define @intrinsic_vmadc_vi_nxv2i1_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv2i1_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv2i64.i64( %0, i64 -9, @@ -1053,10 +1182,12 @@ } define @intrinsic_vmadc_vi_nxv4i1_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv4i1_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmadc.nxv4i64.i64( %0, i64 9, @@ -1066,10 +1197,12 @@ } define @intrinsic_vmadc_vi_nxv8i1_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmadc.vi v0, v8, -9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc_vi_nxv8i1_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmadc.vi {{v[0-9]+}}, {{v[0-9]+}}, -9 %a = call @llvm.riscv.vmadc.nxv8i64.i64( %0, i64 -9, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8( @@ -7,10 +8,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +31,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +54,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +77,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +100,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +123,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +146,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +169,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +192,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +215,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +238,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +261,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +284,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +307,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +330,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +353,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +376,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +399,13 @@ i32); define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +422,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8( %0, i8 %1, @@ -387,10 +445,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8( %0, i8 %1, @@ -407,10 +468,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i8.i8( %0, i8 %1, @@ -427,10 +491,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i8.i8( %0, i8 %1, @@ -447,10 +514,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i8.i8( %0, i8 %1, @@ -467,10 +537,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i8.i8( %0, i8 %1, @@ -487,10 +560,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv64i8.i8( %0, i8 %1, @@ -507,10 +583,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i16.i16( %0, i16 %1, @@ -527,10 +606,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i16.i16( %0, i16 %1, @@ -547,10 +629,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i16.i16( %0, i16 %1, @@ -567,10 +652,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i16.i16( %0, i16 %1, @@ -587,10 +675,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i16.i16( %0, i16 %1, @@ -607,10 +698,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i16.i16( %0, i16 %1, @@ -627,10 +721,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i32.i32( %0, i32 %1, @@ -647,10 +744,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i32.i32( %0, i32 %1, @@ -667,10 +767,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i32.i32( %0, i32 %1, @@ -687,10 +790,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i32.i32( %0, i32 %1, @@ -707,10 +813,13 @@ i32); define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i32.i32( %0, i32 %1, @@ -721,10 +830,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8( %0, i8 9, @@ -735,10 +847,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8( %0, i8 9, @@ -749,10 +864,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i8.i8( %0, i8 9, @@ -763,10 +881,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i8.i8( %0, i8 9, @@ -777,10 +898,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i8.i8( %0, i8 9, @@ -791,10 +915,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i8.i8( %0, i8 9, @@ -805,10 +932,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv64i8.i8( %0, i8 9, @@ -819,10 +949,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i16.i16( %0, i16 9, @@ -833,10 +966,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i16.i16( %0, i16 9, @@ -847,10 +983,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i16.i16( %0, i16 9, @@ -861,10 +1000,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i16.i16( %0, i16 9, @@ -875,10 +1017,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i16.i16( %0, i16 9, @@ -889,10 +1034,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i16.i16( %0, i16 9, @@ -903,10 +1051,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i32.i32( %0, i32 9, @@ -917,10 +1068,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i32.i32( %0, i32 9, @@ -931,10 +1085,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i32.i32( %0, i32 9, @@ -945,10 +1102,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i32.i32( %0, i32 9, @@ -959,10 +1119,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i32.i32( %0, i32 9, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8( @@ -7,10 +8,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +31,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +54,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +77,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +100,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +123,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +146,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv64i1_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +169,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +192,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +215,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +238,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +261,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +284,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv32i1_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +307,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +330,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +353,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +376,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +399,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv16i1_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +422,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv1i1_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i64.nxv1i64( %0, %1, @@ -387,10 +445,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv2i1_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i64.nxv2i64( %0, %1, @@ -407,10 +468,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv4i1_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i64.nxv4i64( %0, %1, @@ -427,10 +491,13 @@ i64); define @intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i64_nxv8i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmadc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vvm_nxv8i1_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmadc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i64.nxv8i64( %0, %1, @@ -447,10 +514,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8( %0, i8 %1, @@ -467,10 +537,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8( %0, i8 %1, @@ -487,10 +560,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i8.i8( %0, i8 %1, @@ -507,10 +583,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i8.i8( %0, i8 %1, @@ -527,10 +606,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i8.i8( %0, i8 %1, @@ -547,10 +629,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i8.i8( %0, i8 %1, @@ -567,10 +652,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv64i8.i8( %0, i8 %1, @@ -587,10 +675,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i16.i16( %0, i16 %1, @@ -607,10 +698,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i16.i16( %0, i16 %1, @@ -627,10 +721,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i16.i16( %0, i16 %1, @@ -647,10 +744,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i16.i16( %0, i16 %1, @@ -667,10 +767,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i16.i16( %0, i16 %1, @@ -687,10 +790,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i16.i16( %0, i16 %1, @@ -707,10 +813,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i32.i32( %0, i32 %1, @@ -727,10 +836,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i32.i32( %0, i32 %1, @@ -747,10 +859,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i32.i32( %0, i32 %1, @@ -767,10 +882,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i32.i32( %0, i32 %1, @@ -787,10 +905,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i32.i32( %0, i32 %1, @@ -807,10 +928,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv1i1_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i64.i64( %0, i64 %1, @@ -827,10 +951,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv2i1_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i64.i64( %0, i64 %1, @@ -847,10 +974,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv4i1_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i64.i64( %0, i64 %1, @@ -867,10 +997,13 @@ i64); define @intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmadc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vxm_nxv8i1_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmadc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i64.i64( %0, i64 %1, @@ -881,10 +1014,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i8.i8( %0, i8 9, @@ -895,10 +1031,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i8.i8( %0, i8 9, @@ -909,10 +1048,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i8.i8( %0, i8 9, @@ -923,10 +1065,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i8.i8( %0, i8 9, @@ -937,10 +1082,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i8.i8( %0, i8 9, @@ -951,10 +1099,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i8.i8( %0, i8 9, @@ -965,10 +1116,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv64i8.i8( %0, i8 9, @@ -979,10 +1133,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i16.i16( %0, i16 9, @@ -993,10 +1150,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i16.i16( %0, i16 9, @@ -1007,10 +1167,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i16.i16( %0, i16 9, @@ -1021,10 +1184,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i16.i16( %0, i16 9, @@ -1035,10 +1201,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i16.i16( %0, i16 9, @@ -1049,10 +1218,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv32i16.i16( %0, i16 9, @@ -1063,10 +1235,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i32.i32( %0, i32 9, @@ -1077,10 +1252,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i32.i32( %0, i32 9, @@ -1091,10 +1269,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i32.i32( %0, i32 9, @@ -1105,10 +1286,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i32.i32( %0, i32 9, @@ -1119,10 +1303,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv16i32.i32( %0, i32 9, @@ -1133,10 +1320,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv1i1_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv1i64.i64( %0, i64 9, @@ -1147,10 +1337,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv2i1_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv2i64.i64( %0, i64 9, @@ -1161,10 +1354,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv4i1_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv4i64.i64( %0, i64 9, @@ -1175,10 +1371,13 @@ } define @intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmadc.vim v25, v8, 9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadc.carry.in_vim_nxv8i1_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmadc.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmadc.carry.in.nxv8i64.i64( %0, i64 9, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmadd.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv16i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv32i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv16i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i32.nxv1i32( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i32.nxv2i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i32.nxv4i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i32.nxv8i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i8.i8( %0, i8 %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i8.i8( %0, i8 %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i8.i8( %0, i8 %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i8.i8( %0, i8 %1, @@ -721,10 +790,12 @@ i32); define @intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i8.i8( %0, i8 %1, @@ -742,10 +813,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i8.i8( %0, i8 %1, @@ -763,10 +836,12 @@ i32); define @intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i8.i8( %0, i8 %1, @@ -784,10 +859,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i8.i8( %0, i8 %1, @@ -805,10 +882,12 @@ i32); define @intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv16i8.i8( %0, i8 %1, @@ -826,10 +905,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv16i8.i8( %0, i8 %1, @@ -847,10 +928,12 @@ i32); define @intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv32i8.i8( %0, i8 %1, @@ -868,10 +951,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv32i8.i8( %0, i8 %1, @@ -889,10 +974,12 @@ i32); define @intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i16.i16( %0, i16 %1, @@ -910,10 +997,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i16.i16( %0, i16 %1, @@ -931,10 +1020,12 @@ i32); define @intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i16.i16( %0, i16 %1, @@ -952,10 +1043,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i16.i16( %0, i16 %1, @@ -973,10 +1066,12 @@ i32); define @intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i16.i16( %0, i16 %1, @@ -994,10 +1089,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i16.i16( %0, i16 %1, @@ -1015,10 +1112,12 @@ i32); define @intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i16.i16( %0, i16 %1, @@ -1036,10 +1135,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i16.i16( %0, i16 %1, @@ -1057,10 +1158,12 @@ i32); define @intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv16i16.i16( %0, i16 %1, @@ -1078,10 +1181,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv16i16.i16( %0, i16 %1, @@ -1099,10 +1204,12 @@ i32); define @intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i32.i32( %0, i32 %1, @@ -1120,10 +1227,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i32.i32( %0, i32 %1, @@ -1141,10 +1250,12 @@ i32); define @intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i32.i32( %0, i32 %1, @@ -1162,10 +1273,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i32.i32( %0, i32 %1, @@ -1183,10 +1296,12 @@ i32); define @intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i32.i32( %0, i32 %1, @@ -1204,10 +1319,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i32.i32( %0, i32 %1, @@ -1225,10 +1342,12 @@ i32); define @intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1365,12 @@ i32); define @intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i32.i32( %0, i32 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmadd.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv16i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv32i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv16i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i32.nxv1i32( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i32.nxv2i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i32.nxv4i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i32.nxv8i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vmadd_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i64.nxv1i64( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vmadd_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i64.nxv2i64( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vmadd_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i64.nxv4i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i8.i8( %0, i8 %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i8.i8( %0, i8 %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i8.i8( %0, i8 %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i8.i8( %0, i8 %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i8.i8( %0, i8 %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i8.i8( %0, i8 %1, @@ -889,10 +974,12 @@ i64); define @intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i8.i8( %0, i8 %1, @@ -910,10 +997,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i8.i8( %0, i8 %1, @@ -931,10 +1020,12 @@ i64); define @intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv16i8.i8( %0, i8 %1, @@ -952,10 +1043,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv16i8.i8( %0, i8 %1, @@ -973,10 +1066,12 @@ i64); define @intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv32i8.i8( %0, i8 %1, @@ -994,10 +1089,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv32i8.i8( %0, i8 %1, @@ -1015,10 +1112,12 @@ i64); define @intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i16.i16( %0, i16 %1, @@ -1036,10 +1135,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i16.i16( %0, i16 %1, @@ -1057,10 +1158,12 @@ i64); define @intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i16.i16( %0, i16 %1, @@ -1078,10 +1181,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i16.i16( %0, i16 %1, @@ -1099,10 +1204,12 @@ i64); define @intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i16.i16( %0, i16 %1, @@ -1120,10 +1227,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i16.i16( %0, i16 %1, @@ -1141,10 +1250,12 @@ i64); define @intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i16.i16( %0, i16 %1, @@ -1162,10 +1273,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i16.i16( %0, i16 %1, @@ -1183,10 +1296,12 @@ i64); define @intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv16i16.i16( %0, i16 %1, @@ -1204,10 +1319,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv16i16.i16( %0, i16 %1, @@ -1225,10 +1342,12 @@ i64); define @intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i32.i32( %0, i32 %1, @@ -1246,10 +1365,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i32.i32( %0, i32 %1, @@ -1267,10 +1388,12 @@ i64); define @intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i32.i32( %0, i32 %1, @@ -1288,10 +1411,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i32.i32( %0, i32 %1, @@ -1309,10 +1434,12 @@ i64); define @intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i32.i32( %0, i32 %1, @@ -1330,10 +1457,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i32.i32( %0, i32 %1, @@ -1351,10 +1480,12 @@ i64); define @intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv8i32.i32( %0, i32 %1, @@ -1372,10 +1503,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv8i32.i32( %0, i32 %1, @@ -1393,10 +1526,12 @@ i64); define @intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv1i64.i64( %0, i64 %1, @@ -1414,10 +1549,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv1i64.i64( %0, i64 %1, @@ -1435,10 +1572,12 @@ i64); define @intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv2i64.i64( %0, i64 %1, @@ -1456,10 +1595,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv2i64.i64( %0, i64 %1, @@ -1477,10 +1618,12 @@ i64); define @intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vmadd.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1641,12 @@ i64); define @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmadd.mask.nxv4i64.i64( %0, i64 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmand.nxv1i1( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmand_mm_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmand_mm_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmand_mm_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmand_mm_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmand_mm_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmand_mm_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmand_mm_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmand.nxv1i1( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmand_mm_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmand_mm_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmand_mm_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmand_mm_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmand_mm_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmand_mm_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmand_mm_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmand.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmandnot.nxv1i1( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmandnot_mm_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmandnot_mm_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmandnot_mm_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmandnot_mm_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmandnot_mm_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmandnot_mm_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmandnot_mm_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmandnot.nxv1i1( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmandnot_mm_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmandnot_mm_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmandnot_mm_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmandnot_mm_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmandnot_mm_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmandnot_mm_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmandnot_mm_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmandnot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmandnot.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vmand_vv_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmand.mm v0, v0, v16 +; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -16,7 +16,7 @@ ; CHECK-LABEL: vmand_vv_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmand.mm v0, v0, v16 +; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -26,7 +26,7 @@ ; CHECK-LABEL: vmand_vv_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmand.mm v0, v0, v16 +; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -36,7 +36,7 @@ ; CHECK-LABEL: vmand_vv_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmand.mm v0, v0, v16 +; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -46,7 +46,7 @@ ; CHECK-LABEL: vmand_vv_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmand.mm v0, v0, v16 +; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb ret %vc @@ -56,7 +56,7 @@ ; CHECK-LABEL: vmor_vv_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmor.mm v0, v0, v16 +; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb ret %vc @@ -66,7 +66,7 @@ ; CHECK-LABEL: vmor_vv_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmor.mm v0, v0, v16 +; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb ret %vc @@ -76,7 +76,7 @@ ; CHECK-LABEL: vmor_vv_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmor.mm v0, v0, v16 +; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK-LABEL: vmor_vv_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmor.mm v0, v0, v16 +; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb ret %vc @@ -96,7 +96,7 @@ ; CHECK-LABEL: vmor_vv_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmor.mm v0, v0, v16 +; CHECK-NEXT: vmor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb ret %vc @@ -106,7 +106,7 @@ ; CHECK-LABEL: vmxor_vv_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmxor.mm v0, v0, v16 +; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -116,7 +116,7 @@ ; CHECK-LABEL: vmxor_vv_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmxor.mm v0, v0, v16 +; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -126,7 +126,7 @@ ; CHECK-LABEL: vmxor_vv_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmxor.mm v0, v0, v16 +; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -136,7 +136,7 @@ ; CHECK-LABEL: vmxor_vv_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmxor.mm v0, v0, v16 +; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -146,7 +146,7 @@ ; CHECK-LABEL: vmxor_vv_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmxor.mm v0, v0, v16 +; CHECK-NEXT: vmxor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -156,7 +156,7 @@ ; CHECK-LABEL: vmnand_vv_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmnand.mm v0, v0, v16 +; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -169,7 +169,7 @@ ; CHECK-LABEL: vmnand_vv_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmnand.mm v0, v0, v16 +; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -182,7 +182,7 @@ ; CHECK-LABEL: vmnand_vv_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmnand.mm v0, v0, v16 +; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -195,7 +195,7 @@ ; CHECK-LABEL: vmnand_vv_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmnand.mm v0, v0, v16 +; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -208,7 +208,7 @@ ; CHECK-LABEL: vmnand_vv_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmnand.mm v0, v0, v16 +; CHECK-NEXT: vmnand.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = and %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -221,7 +221,7 @@ ; CHECK-LABEL: vmnor_vv_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmnor.mm v0, v0, v16 +; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -234,7 +234,7 @@ ; CHECK-LABEL: vmnor_vv_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmnor.mm v0, v0, v16 +; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -247,7 +247,7 @@ ; CHECK-LABEL: vmnor_vv_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmnor.mm v0, v0, v16 +; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -260,7 +260,7 @@ ; CHECK-LABEL: vmnor_vv_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmnor.mm v0, v0, v16 +; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -273,7 +273,7 @@ ; CHECK-LABEL: vmnor_vv_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmnor.mm v0, v0, v16 +; CHECK-NEXT: vmnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = or %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -286,7 +286,7 @@ ; CHECK-LABEL: vmxnor_vv_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmxnor.mm v0, v0, v16 +; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -299,7 +299,7 @@ ; CHECK-LABEL: vmxnor_vv_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmxnor.mm v0, v0, v16 +; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -312,7 +312,7 @@ ; CHECK-LABEL: vmxnor_vv_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmxnor.mm v0, v0, v16 +; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -325,7 +325,7 @@ ; CHECK-LABEL: vmxnor_vv_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmxnor.mm v0, v0, v16 +; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -338,7 +338,7 @@ ; CHECK-LABEL: vmxnor_vv_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmxnor.mm v0, v0, v16 +; CHECK-NEXT: vmxnor.mm v0, v0, v8 ; CHECK-NEXT: ret %vc = xor %va, %vb %head = insertelement undef, i1 1, i32 0 @@ -351,7 +351,7 @@ ; CHECK-LABEL: vmandnot_vv_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmandnot.mm v0, v0, v16 +; CHECK-NEXT: vmandnot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -364,7 +364,7 @@ ; CHECK-LABEL: vmandnot_vv_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmandnot.mm v0, v0, v16 +; CHECK-NEXT: vmandnot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -377,7 +377,7 @@ ; CHECK-LABEL: vmandnot_vv_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmandnot.mm v0, v0, v16 +; CHECK-NEXT: vmandnot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -390,7 +390,7 @@ ; CHECK-LABEL: vmandnot_vv_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmandnot.mm v0, v0, v16 +; CHECK-NEXT: vmandnot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -403,7 +403,7 @@ ; CHECK-LABEL: vmandnot_vv_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmandnot.mm v0, v0, v16 +; CHECK-NEXT: vmandnot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -416,7 +416,7 @@ ; CHECK-LABEL: vmornot_vv_nxv1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmornot.mm v0, v0, v16 +; CHECK-NEXT: vmornot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -429,7 +429,7 @@ ; CHECK-LABEL: vmornot_vv_nxv2i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmornot.mm v0, v0, v16 +; CHECK-NEXT: vmornot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -442,7 +442,7 @@ ; CHECK-LABEL: vmornot_vv_nxv4i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmornot.mm v0, v0, v16 +; CHECK-NEXT: vmornot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -455,7 +455,7 @@ ; CHECK-LABEL: vmornot_vv_nxv8i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmornot.mm v0, v0, v16 +; CHECK-NEXT: vmornot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -468,7 +468,7 @@ ; CHECK-LABEL: vmornot_vv_nxv16i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmornot.mm v0, v0, v16 +; CHECK-NEXT: vmornot.mm v0, v0, v8 ; CHECK-NEXT: ret %head = insertelement undef, i1 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmax.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vmax_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vmax_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vmax_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vmax_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vmax_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vmax_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vmax_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vmax_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vmax_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vmax_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vmax_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vmax_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vmax_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vmax_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vmax_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vmax_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vmax_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vmax_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vmax_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vmax_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vmax_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vmax_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vmax_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmax.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vmax_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmax.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vmax_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmax.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vmax_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vmax_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vmax_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vmax_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmax.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vmax_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmax.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vmax_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmax.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vmax_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vmax_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vmax_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmax.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vmax_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmax.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vmax_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vmax_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmax.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmax.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vmax_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vmax_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vmax_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vmax_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vmax_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vmax_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vmax_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vmax_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vmax_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vmax_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vmax_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vmax_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vmax_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vmax_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vmax_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vmax_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vmax_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vmax_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmax.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vmax_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmax.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vmax_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vmax_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmax.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vmax_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vmax.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vmax_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vmax_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vmax_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vmax_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vmax_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmax.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vmax_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmax.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vmax_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmax.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vmax_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vmax_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vmax_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vmax_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmax.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vmax_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmax.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vmax_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmax.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vmax_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vmax_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vmax_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmax.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vmax_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmax.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vmax_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmax.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vmax_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmax.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vmax_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmax.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vmax_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmax.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vmax_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmax_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmax.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmax.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vmax_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vmax.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmax_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmax.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmax.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -16,7 +16,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -30,7 +30,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,7 +43,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -54,7 +54,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -81,7 +81,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -92,7 +92,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,7 +106,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -119,7 +119,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -130,7 +130,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -144,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vmax_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v18 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -168,7 +168,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -195,7 +195,7 @@ ; CHECK-LABEL: vmax_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v20 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -206,7 +206,7 @@ ; CHECK-LABEL: vmax_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -220,7 +220,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,9 +232,8 @@ define @vmax_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -245,7 +244,7 @@ ; CHECK-LABEL: vmax_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -259,7 +258,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -272,7 +271,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -283,7 +282,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -297,7 +296,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -335,7 +334,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +347,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -359,7 +358,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,7 +372,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -386,7 +385,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v18 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -397,7 +396,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -411,7 +410,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -424,7 +423,7 @@ ; CHECK-LABEL: vmax_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v20 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -435,7 +434,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,9 +460,8 @@ define @vmax_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -474,7 +472,7 @@ ; CHECK-LABEL: vmax_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +486,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -501,7 +499,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -512,7 +510,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -526,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -550,7 +548,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -564,7 +562,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v18 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -588,7 +586,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -602,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -615,7 +613,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v20 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -626,7 +624,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,7 +638,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -652,9 +650,8 @@ define @vmax_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -665,7 +662,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +676,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -710,7 +707,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vmax.vv v16, v16, v25 +; CHECK-NEXT: vmax.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -724,7 +721,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -737,7 +734,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v18 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -755,7 +752,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vmax.vv v16, v16, v26 +; CHECK-NEXT: vmax.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -769,7 +766,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -782,7 +779,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v20 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -796,11 +793,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vmax.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vmax.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -814,7 +811,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -826,9 +823,8 @@ define @vmax_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -839,14 +835,14 @@ ; CHECK-LABEL: vmax_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmax.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -860,7 +856,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -16,7 +16,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -30,7 +30,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,7 +43,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -54,7 +54,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -81,7 +81,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -92,7 +92,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,7 +106,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -119,7 +119,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -130,7 +130,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -144,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vmax_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v18 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -168,7 +168,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -195,7 +195,7 @@ ; CHECK-LABEL: vmax_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v20 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -206,7 +206,7 @@ ; CHECK-LABEL: vmax_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -220,7 +220,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,9 +232,8 @@ define @vmax_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -245,7 +244,7 @@ ; CHECK-LABEL: vmax_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -259,7 +258,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -272,7 +271,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -283,7 +282,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -297,7 +296,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -335,7 +334,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +347,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -359,7 +358,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,7 +372,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -386,7 +385,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v18 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -397,7 +396,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -411,7 +410,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -424,7 +423,7 @@ ; CHECK-LABEL: vmax_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v20 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -435,7 +434,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,9 +460,8 @@ define @vmax_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -474,7 +472,7 @@ ; CHECK-LABEL: vmax_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +486,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -501,7 +499,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -512,7 +510,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -526,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -550,7 +548,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -564,7 +562,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v18 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -588,7 +586,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -602,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -615,7 +613,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v20 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -626,7 +624,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,7 +638,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -652,9 +650,8 @@ define @vmax_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -665,7 +662,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +676,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v17 +; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -703,7 +700,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -717,7 +714,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -730,7 +727,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v18 +; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -741,7 +738,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -755,7 +752,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -768,7 +765,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmax.vv v16, v16, v20 +; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -779,7 +776,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -793,7 +790,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -805,9 +802,8 @@ define @vmax_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmax.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp sgt %va, %vb %vc = select %cmp, %va, %vb @@ -818,7 +814,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -832,7 +828,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmax.vx v16, v16, a0 +; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vmaxu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vmaxu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vmaxu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vmaxu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vmaxu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vmaxu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vmaxu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vmaxu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vmaxu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vmaxu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vmaxu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vmaxu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vmaxu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vmaxu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vmaxu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vmaxu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vmaxu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vmaxu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vmaxu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vmaxu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vmaxu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vmaxu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vmaxu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vmaxu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vmaxu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vmaxu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vmaxu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vmaxu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vmaxu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vmaxu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vmaxu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vmaxu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vmaxu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vmaxu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vmaxu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vmaxu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmaxu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vmaxu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vmaxu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vmaxu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vmaxu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vmaxu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vmaxu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vmaxu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vmaxu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vmaxu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vmaxu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vmaxu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vmaxu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vmaxu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vmaxu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vmaxu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vmaxu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vmaxu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vmaxu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vmaxu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vmaxu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vmaxu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vmaxu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmaxu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vmaxu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vmaxu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vmaxu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vmaxu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vmaxu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vmaxu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vmaxu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vmaxu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vmaxu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vmaxu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vmaxu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vmaxu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vmaxu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vmaxu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vmaxu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vmaxu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vmaxu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vmaxu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vmaxu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmaxu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmaxu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vmaxu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vmaxu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmaxu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmaxu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmaxu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -16,7 +16,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -30,7 +30,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,7 +43,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -54,7 +54,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -81,7 +81,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -92,7 +92,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,7 +106,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -119,7 +119,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -130,7 +130,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -144,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vmax_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v18 +; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -168,7 +168,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -195,7 +195,7 @@ ; CHECK-LABEL: vmax_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v20 +; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -206,7 +206,7 @@ ; CHECK-LABEL: vmax_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -220,7 +220,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,9 +232,8 @@ define @vmax_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmaxu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -245,7 +244,7 @@ ; CHECK-LABEL: vmax_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -259,7 +258,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -272,7 +271,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -283,7 +282,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -297,7 +296,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -335,7 +334,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +347,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -359,7 +358,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,7 +372,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -386,7 +385,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v18 +; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -397,7 +396,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -411,7 +410,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -424,7 +423,7 @@ ; CHECK-LABEL: vmax_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v20 +; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -435,7 +434,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,9 +460,8 @@ define @vmax_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmaxu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -474,7 +472,7 @@ ; CHECK-LABEL: vmax_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +486,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -501,7 +499,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -512,7 +510,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -526,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -550,7 +548,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -564,7 +562,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v18 +; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -588,7 +586,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -602,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -615,7 +613,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v20 +; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -626,7 +624,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,7 +638,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -652,9 +650,8 @@ define @vmax_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmaxu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -665,7 +662,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +676,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -710,7 +707,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vmaxu.vv v16, v16, v25 +; CHECK-NEXT: vmaxu.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -724,7 +721,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -737,7 +734,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v18 +; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -755,7 +752,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vmaxu.vv v16, v16, v26 +; CHECK-NEXT: vmaxu.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -769,7 +766,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -782,7 +779,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v20 +; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -796,11 +793,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vmaxu.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vmaxu.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -814,7 +811,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -826,9 +823,8 @@ define @vmax_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmaxu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -839,14 +835,14 @@ ; CHECK-LABEL: vmax_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmaxu.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -860,7 +856,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -16,7 +16,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -30,7 +30,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,7 +43,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -54,7 +54,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -81,7 +81,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -92,7 +92,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,7 +106,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -119,7 +119,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -130,7 +130,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -144,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vmax_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v18 +; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -168,7 +168,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -195,7 +195,7 @@ ; CHECK-LABEL: vmax_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v20 +; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -206,7 +206,7 @@ ; CHECK-LABEL: vmax_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -220,7 +220,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,9 +232,8 @@ define @vmax_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmaxu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -245,7 +244,7 @@ ; CHECK-LABEL: vmax_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -259,7 +258,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -272,7 +271,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -283,7 +282,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -297,7 +296,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -335,7 +334,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +347,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -359,7 +358,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,7 +372,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -386,7 +385,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v18 +; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -397,7 +396,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -411,7 +410,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -424,7 +423,7 @@ ; CHECK-LABEL: vmax_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v20 +; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -435,7 +434,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,9 +460,8 @@ define @vmax_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmaxu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -474,7 +472,7 @@ ; CHECK-LABEL: vmax_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +486,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -501,7 +499,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -512,7 +510,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -526,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -550,7 +548,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -564,7 +562,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v18 +; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -588,7 +586,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -602,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -615,7 +613,7 @@ ; CHECK-LABEL: vmax_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v20 +; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -626,7 +624,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,7 +638,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -652,9 +650,8 @@ define @vmax_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmaxu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -665,7 +662,7 @@ ; CHECK-LABEL: vmax_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +676,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK-LABEL: vmax_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v17 +; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -703,7 +700,7 @@ ; CHECK-LABEL: vmax_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -717,7 +714,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -730,7 +727,7 @@ ; CHECK-LABEL: vmax_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v18 +; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -741,7 +738,7 @@ ; CHECK-LABEL: vmax_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -755,7 +752,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -768,7 +765,7 @@ ; CHECK-LABEL: vmax_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmaxu.vv v16, v16, v20 +; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -779,7 +776,7 @@ ; CHECK-LABEL: vmax_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -793,7 +790,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -805,9 +802,8 @@ define @vmax_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmax_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmaxu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ugt %va, %vb %vc = select %cmp, %va, %vb @@ -818,7 +814,7 @@ ; CHECK-LABEL: vmax_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -832,7 +828,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmaxu.vx v16, v16, a0 +; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmclr-rv32.ll @@ -1,13 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmclr.nxv1i1( i32); define @intrinsic_vmclr_m_pseudo_nxv1i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv1i1( i32 %0) @@ -18,10 +21,12 @@ i32); define @intrinsic_vmclr_m_pseudo_nxv2i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv2i1( i32 %0) @@ -32,10 +37,12 @@ i32); define @intrinsic_vmclr_m_pseudo_nxv4i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv4i1( i32 %0) @@ -46,10 +53,12 @@ i32); define @intrinsic_vmclr_m_pseudo_nxv8i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv8i1( i32 %0) @@ -60,10 +69,12 @@ i32); define @intrinsic_vmclr_m_pseudo_nxv16i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv16i1( i32 %0) @@ -74,10 +85,12 @@ i32); define @intrinsic_vmclr_m_pseudo_nxv32i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv32i1( i32 %0) @@ -88,10 +101,12 @@ i32); define @intrinsic_vmclr_m_pseudo_nxv64i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv64i1( i32 %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmclr-rv64.ll @@ -1,13 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmclr.nxv1i1( i64); define @intrinsic_vmclr_m_pseudo_nxv1i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv1i1( i64 %0) @@ -18,10 +21,12 @@ i64); define @intrinsic_vmclr_m_pseudo_nxv2i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv2i1( i64 %0) @@ -32,10 +37,12 @@ i64); define @intrinsic_vmclr_m_pseudo_nxv4i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv4i1( i64 %0) @@ -46,10 +53,12 @@ i64); define @intrinsic_vmclr_m_pseudo_nxv8i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv8i1( i64 %0) @@ -60,10 +69,12 @@ i64); define @intrinsic_vmclr_m_pseudo_nxv16i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv16i1( i64 %0) @@ -74,10 +85,12 @@ i64); define @intrinsic_vmclr_m_pseudo_nxv32i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv32i1( i64 %0) @@ -88,10 +101,12 @@ i64); define @intrinsic_vmclr_m_pseudo_nxv64i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmclr.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmclr_m_pseudo_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8 -; CHECK: vmclr.m {{v[0-9]+}} %a = call @llvm.riscv.vmclr.nxv64i1( i64 %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmerge.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +30,12 @@ i32); define @intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +52,12 @@ i32); define @intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +74,12 @@ i32); define @intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +96,12 @@ i32); define @intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +118,12 @@ i32); define @intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +140,12 @@ i32); define @intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +162,12 @@ i32); define @intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +184,12 @@ i32); define @intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +206,12 @@ i32); define @intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +228,12 @@ i32); define @intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +250,12 @@ i32); define @intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +272,12 @@ i32); define @intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +294,12 @@ i32); define @intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +316,12 @@ i32); define @intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +338,12 @@ i32); define @intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +360,12 @@ i32); define @intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +382,12 @@ i32); define @intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +404,12 @@ i32); define @intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i8.i8( %0, i8 %1, @@ -387,10 +426,12 @@ i32); define @intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i8.i8( %0, i8 %1, @@ -407,10 +448,12 @@ i32); define @intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i8.i8( %0, i8 %1, @@ -427,10 +470,12 @@ i32); define @intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i8.i8( %0, i8 %1, @@ -447,10 +492,12 @@ i32); define @intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i8.i8( %0, i8 %1, @@ -467,10 +514,12 @@ i32); define @intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv32i8.i8( %0, i8 %1, @@ -487,10 +536,12 @@ i32); define @intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv64i8.i8( %0, i8 %1, @@ -507,10 +558,12 @@ i32); define @intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i16.i16( %0, i16 %1, @@ -527,10 +580,12 @@ i32); define @intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i16.i16( %0, i16 %1, @@ -547,10 +602,12 @@ i32); define @intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i16.i16( %0, i16 %1, @@ -567,10 +624,12 @@ i32); define @intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i16.i16( %0, i16 %1, @@ -587,10 +646,12 @@ i32); define @intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i16.i16( %0, i16 %1, @@ -607,10 +668,12 @@ i32); define @intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv32i16.i16( %0, i16 %1, @@ -627,10 +690,12 @@ i32); define @intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i32.i32( %0, i32 %1, @@ -647,10 +712,12 @@ i32); define @intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i32.i32( %0, i32 %1, @@ -667,10 +734,12 @@ i32); define @intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i32.i32( %0, i32 %1, @@ -687,10 +756,12 @@ i32); define @intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i32.i32( %0, i32 %1, @@ -707,10 +778,12 @@ i32); define @intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i32.i32( %0, i32 %1, @@ -721,10 +794,12 @@ } define @intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv1i8.i8( %0, i8 9, @@ -735,10 +810,12 @@ } define @intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv2i8.i8( %0, i8 9, @@ -749,10 +826,12 @@ } define @intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv4i8.i8( %0, i8 9, @@ -763,10 +842,12 @@ } define @intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv8i8.i8( %0, i8 9, @@ -777,10 +858,12 @@ } define @intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv16i8.i8( %0, i8 9, @@ -791,10 +874,12 @@ } define @intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv32i8.i8( %0, i8 9, @@ -805,10 +890,12 @@ } define @intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv64i8.i8( %0, i8 9, @@ -819,10 +906,12 @@ } define @intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv1i16.i16( %0, i16 9, @@ -833,10 +922,12 @@ } define @intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv2i16.i16( %0, i16 9, @@ -847,10 +938,12 @@ } define @intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv4i16.i16( %0, i16 9, @@ -861,10 +954,12 @@ } define @intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv8i16.i16( %0, i16 9, @@ -875,10 +970,12 @@ } define @intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv16i16.i16( %0, i16 9, @@ -889,10 +986,12 @@ } define @intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv32i16.i16( %0, i16 9, @@ -903,10 +1002,12 @@ } define @intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv1i32.i32( %0, i32 9, @@ -917,10 +1018,12 @@ } define @intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv2i32.i32( %0, i32 9, @@ -931,10 +1034,12 @@ } define @intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv4i32.i32( %0, i32 9, @@ -945,10 +1050,12 @@ } define @intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv8i32.i32( %0, i32 9, @@ -959,10 +1066,12 @@ } define @intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv16i32.i32( %0, i32 9, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmerge.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +30,12 @@ i64); define @intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +52,12 @@ i64); define @intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +74,12 @@ i64); define @intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +96,12 @@ i64); define @intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +118,12 @@ i64); define @intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +140,12 @@ i64); define @intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +162,12 @@ i64); define @intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +184,12 @@ i64); define @intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +206,12 @@ i64); define @intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +228,12 @@ i64); define @intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +250,12 @@ i64); define @intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +272,12 @@ i64); define @intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +294,12 @@ i64); define @intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +316,12 @@ i64); define @intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +338,12 @@ i64); define @intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +360,12 @@ i64); define @intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +382,12 @@ i64); define @intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +404,12 @@ i64); define @intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i64.nxv1i64( %0, %1, @@ -387,10 +426,12 @@ i64); define @intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i64.nxv2i64( %0, %1, @@ -407,10 +448,12 @@ i64); define @intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i64.nxv4i64( %0, %1, @@ -427,10 +470,12 @@ i64); define @intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8 -; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i64.nxv8i64( %0, %1, @@ -447,10 +492,12 @@ i64); define @intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i8.i8( %0, i8 %1, @@ -467,10 +514,12 @@ i64); define @intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i8.i8( %0, i8 %1, @@ -487,10 +536,12 @@ i64); define @intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i8.i8( %0, i8 %1, @@ -507,10 +558,12 @@ i64); define @intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i8.i8( %0, i8 %1, @@ -527,10 +580,12 @@ i64); define @intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i8.i8( %0, i8 %1, @@ -547,10 +602,12 @@ i64); define @intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv32i8.i8( %0, i8 %1, @@ -567,10 +624,12 @@ i64); define @intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv64i8.i8( %0, i8 %1, @@ -587,10 +646,12 @@ i64); define @intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i16.i16( %0, i16 %1, @@ -607,10 +668,12 @@ i64); define @intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i16.i16( %0, i16 %1, @@ -627,10 +690,12 @@ i64); define @intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i16.i16( %0, i16 %1, @@ -647,10 +712,12 @@ i64); define @intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i16.i16( %0, i16 %1, @@ -667,10 +734,12 @@ i64); define @intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i16.i16( %0, i16 %1, @@ -687,10 +756,12 @@ i64); define @intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv32i16.i16( %0, i16 %1, @@ -707,10 +778,12 @@ i64); define @intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i32.i32( %0, i32 %1, @@ -727,10 +800,12 @@ i64); define @intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i32.i32( %0, i32 %1, @@ -747,10 +822,12 @@ i64); define @intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i32.i32( %0, i32 %1, @@ -767,10 +844,12 @@ i64); define @intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i32.i32( %0, i32 %1, @@ -787,10 +866,12 @@ i64); define @intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv16i32.i32( %0, i32 %1, @@ -807,10 +888,12 @@ i64); define @intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv1i64.i64( %0, i64 %1, @@ -827,10 +910,12 @@ i64); define @intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv2i64.i64( %0, i64 %1, @@ -847,10 +932,12 @@ i64); define @intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv4i64.i64( %0, i64 %1, @@ -867,10 +954,12 @@ i64); define @intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8 -; CHECK: vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmerge.nxv8i64.i64( %0, i64 %1, @@ -881,10 +970,12 @@ } define @intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv1i8.i8( %0, i8 9, @@ -895,10 +986,12 @@ } define @intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv2i8.i8( %0, i8 9, @@ -909,10 +1002,12 @@ } define @intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv4i8.i8( %0, i8 9, @@ -923,10 +1018,12 @@ } define @intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv8i8.i8( %0, i8 9, @@ -937,10 +1034,12 @@ } define @intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv16i8.i8( %0, i8 9, @@ -951,10 +1050,12 @@ } define @intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv32i8.i8( %0, i8 9, @@ -965,10 +1066,12 @@ } define @intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv64i8.i8( %0, i8 9, @@ -979,10 +1082,12 @@ } define @intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv1i16.i16( %0, i16 9, @@ -993,10 +1098,12 @@ } define @intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv2i16.i16( %0, i16 9, @@ -1007,10 +1114,12 @@ } define @intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv4i16.i16( %0, i16 9, @@ -1021,10 +1130,12 @@ } define @intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv8i16.i16( %0, i16 9, @@ -1035,10 +1146,12 @@ } define @intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv16i16.i16( %0, i16 9, @@ -1049,10 +1162,12 @@ } define @intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv32i16.i16( %0, i16 9, @@ -1063,10 +1178,12 @@ } define @intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv1i32.i32( %0, i32 9, @@ -1077,10 +1194,12 @@ } define @intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv2i32.i32( %0, i32 9, @@ -1091,10 +1210,12 @@ } define @intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv4i32.i32( %0, i32 9, @@ -1105,10 +1226,12 @@ } define @intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv8i32.i32( %0, i32 9, @@ -1119,10 +1242,12 @@ } define @intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv16i32.i32( %0, i32 9, @@ -1133,10 +1258,12 @@ } define @intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv1i64.i64( %0, i64 9, @@ -1147,10 +1274,12 @@ } define @intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv2i64.i64( %0, i64 9, @@ -1161,10 +1290,12 @@ } define @intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv4i64.i64( %0, i64 9, @@ -1175,10 +1306,12 @@ } define @intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vim v8, v8, 9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8 -; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0 %a = call @llvm.riscv.vmerge.nxv8i64.i64( %0, i64 9, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfeq.nxv1f16( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmfeq_vv_nxv1f16_nxv1f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f16( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv1f16( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmfeq_vv_nxv2f16_nxv2f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f16( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv2f16( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmfeq_vv_nxv4f16_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f16( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv4f16( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmfeq_vv_nxv8f16_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv8f16( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv8f16( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmfeq_vv_nxv16f16_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv16f16( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv16f16( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmfeq_vv_nxv1f32_nxv1f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f32( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv1f32( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmfeq_vv_nxv2f32_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f32( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv2f32( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmfeq_vv_nxv4f32_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f32( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv4f32( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmfeq_vv_nxv8f32_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv8f32( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv8f32( %1, %2, @@ -402,10 +475,13 @@ i32); define @intrinsic_vmfeq_vf_nxv1f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f16.f16( %0, half %1, @@ -422,10 +498,16 @@ i32); define @intrinsic_vmfeq_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv1f16.f16( %0, %1, @@ -442,10 +524,13 @@ i32); define @intrinsic_vmfeq_vf_nxv2f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f16.f16( %0, half %1, @@ -462,10 +547,16 @@ i32); define @intrinsic_vmfeq_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv2f16.f16( %0, %1, @@ -482,10 +573,13 @@ i32); define @intrinsic_vmfeq_vf_nxv4f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f16.f16( %0, half %1, @@ -502,10 +596,16 @@ i32); define @intrinsic_vmfeq_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv4f16.f16( %0, %1, @@ -522,10 +622,13 @@ i32); define @intrinsic_vmfeq_vf_nxv8f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv8f16.f16( %0, half %1, @@ -542,10 +645,16 @@ i32); define @intrinsic_vmfeq_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv8f16.f16( %0, %1, @@ -562,10 +671,13 @@ i32); define @intrinsic_vmfeq_vf_nxv16f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv16f16.f16( %0, half %1, @@ -582,10 +694,16 @@ i32); define @intrinsic_vmfeq_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv16f16.f16( %0, %1, @@ -602,10 +720,13 @@ i32); define @intrinsic_vmfeq_vf_nxv1f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f32.f32( %0, float %1, @@ -622,10 +743,16 @@ i32); define @intrinsic_vmfeq_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv1f32.f32( %0, %1, @@ -642,10 +769,13 @@ i32); define @intrinsic_vmfeq_vf_nxv2f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f32.f32( %0, float %1, @@ -662,10 +792,16 @@ i32); define @intrinsic_vmfeq_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv2f32.f32( %0, %1, @@ -682,10 +818,13 @@ i32); define @intrinsic_vmfeq_vf_nxv4f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f32.f32( %0, float %1, @@ -702,10 +841,16 @@ i32); define @intrinsic_vmfeq_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv4f32.f32( %0, %1, @@ -722,10 +867,13 @@ i32); define @intrinsic_vmfeq_vf_nxv8f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv8f32.f32( %0, float %1, @@ -742,10 +890,16 @@ i32); define @intrinsic_vmfeq_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfeq.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmfeq_vv_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f16( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv1f16( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmfeq_vv_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f16( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv2f16( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmfeq_vv_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f16( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv4f16( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmfeq_vv_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv8f16( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv8f16( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmfeq_vv_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv16f16( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv16f16( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmfeq_vv_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f32( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv1f32( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmfeq_vv_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f32( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv2f32( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmfeq_vv_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f32( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv4f32( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmfeq_vv_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv8f32( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv8f32( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmfeq_vv_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f64( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv1f64( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmfeq_vv_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f64( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv2f64( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmfeq_vv_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f64( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmfeq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfeq.nxv4f64( %1, %2, @@ -534,10 +631,13 @@ i64); define @intrinsic_vmfeq_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f16.f16( %0, half %1, @@ -554,10 +654,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv1f16.f16( %0, %1, @@ -574,10 +680,13 @@ i64); define @intrinsic_vmfeq_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f16.f16( %0, half %1, @@ -594,10 +703,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv2f16.f16( %0, %1, @@ -614,10 +729,13 @@ i64); define @intrinsic_vmfeq_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f16.f16( %0, half %1, @@ -634,10 +752,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv4f16.f16( %0, %1, @@ -654,10 +778,13 @@ i64); define @intrinsic_vmfeq_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv8f16.f16( %0, half %1, @@ -674,10 +801,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv8f16.f16( %0, %1, @@ -694,10 +827,13 @@ i64); define @intrinsic_vmfeq_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv16f16.f16( %0, half %1, @@ -714,10 +850,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv16f16.f16( %0, %1, @@ -734,10 +876,13 @@ i64); define @intrinsic_vmfeq_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f32.f32( %0, float %1, @@ -754,10 +899,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv1f32.f32( %0, %1, @@ -774,10 +925,13 @@ i64); define @intrinsic_vmfeq_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f32.f32( %0, float %1, @@ -794,10 +948,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv2f32.f32( %0, %1, @@ -814,10 +974,13 @@ i64); define @intrinsic_vmfeq_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f32.f32( %0, float %1, @@ -834,10 +997,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv4f32.f32( %0, %1, @@ -854,10 +1023,13 @@ i64); define @intrinsic_vmfeq_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv8f32.f32( %0, float %1, @@ -874,10 +1046,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv8f32.f32( %0, %1, @@ -894,10 +1072,13 @@ i64); define @intrinsic_vmfeq_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv1f64.f64( %0, double %1, @@ -914,10 +1095,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv1f64.f64( %0, %1, @@ -934,10 +1121,13 @@ i64); define @intrinsic_vmfeq_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv2f64.f64( %0, double %1, @@ -954,10 +1144,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv2f64.f64( %0, %1, @@ -974,10 +1170,13 @@ i64); define @intrinsic_vmfeq_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vmfeq.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfeq.nxv4f64.f64( %0, double %1, @@ -994,10 +1193,16 @@ i64); define @intrinsic_vmfeq_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfeq.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfeq.mask.nxv4f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfge.nxv1f16.f16( @@ -6,10 +7,13 @@ i32); define @intrinsic_vmfge_vf_nxv1f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv1f16.f16( %0, half %1, @@ -26,10 +30,16 @@ i32); define @intrinsic_vmfge_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv1f16.f16( %0, %1, @@ -46,10 +56,13 @@ i32); define @intrinsic_vmfge_vf_nxv2f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv2f16.f16( %0, half %1, @@ -66,10 +79,16 @@ i32); define @intrinsic_vmfge_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv2f16.f16( %0, %1, @@ -86,10 +105,13 @@ i32); define @intrinsic_vmfge_vf_nxv4f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv4f16.f16( %0, half %1, @@ -106,10 +128,16 @@ i32); define @intrinsic_vmfge_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv4f16.f16( %0, %1, @@ -126,10 +154,13 @@ i32); define @intrinsic_vmfge_vf_nxv8f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv8f16.f16( %0, half %1, @@ -146,10 +177,16 @@ i32); define @intrinsic_vmfge_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv8f16.f16( %0, %1, @@ -166,10 +203,13 @@ i32); define @intrinsic_vmfge_vf_nxv16f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv16f16.f16( %0, half %1, @@ -186,10 +226,16 @@ i32); define @intrinsic_vmfge_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv16f16.f16( %0, %1, @@ -206,10 +252,13 @@ i32); define @intrinsic_vmfge_vf_nxv1f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv1f32.f32( %0, float %1, @@ -226,10 +275,16 @@ i32); define @intrinsic_vmfge_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv1f32.f32( %0, %1, @@ -246,10 +301,13 @@ i32); define @intrinsic_vmfge_vf_nxv2f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv2f32.f32( %0, float %1, @@ -266,10 +324,16 @@ i32); define @intrinsic_vmfge_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv2f32.f32( %0, %1, @@ -286,10 +350,13 @@ i32); define @intrinsic_vmfge_vf_nxv4f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv4f32.f32( %0, float %1, @@ -306,10 +373,16 @@ i32); define @intrinsic_vmfge_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv4f32.f32( %0, %1, @@ -326,10 +399,13 @@ i32); define @intrinsic_vmfge_vf_nxv8f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv8f32.f32( %0, float %1, @@ -346,10 +422,16 @@ i32); define @intrinsic_vmfge_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfge.nxv1f16.f16( @@ -6,10 +7,13 @@ i64); define @intrinsic_vmfge_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv1f16.f16( %0, half %1, @@ -26,10 +30,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv1f16.f16( %0, %1, @@ -46,10 +56,13 @@ i64); define @intrinsic_vmfge_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv2f16.f16( %0, half %1, @@ -66,10 +79,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv2f16.f16( %0, %1, @@ -86,10 +105,13 @@ i64); define @intrinsic_vmfge_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv4f16.f16( %0, half %1, @@ -106,10 +128,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv4f16.f16( %0, %1, @@ -126,10 +154,13 @@ i64); define @intrinsic_vmfge_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv8f16.f16( %0, half %1, @@ -146,10 +177,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv8f16.f16( %0, %1, @@ -166,10 +203,13 @@ i64); define @intrinsic_vmfge_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv16f16.f16( %0, half %1, @@ -186,10 +226,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv16f16.f16( %0, %1, @@ -206,10 +252,13 @@ i64); define @intrinsic_vmfge_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv1f32.f32( %0, float %1, @@ -226,10 +275,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv1f32.f32( %0, %1, @@ -246,10 +301,13 @@ i64); define @intrinsic_vmfge_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv2f32.f32( %0, float %1, @@ -266,10 +324,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv2f32.f32( %0, %1, @@ -286,10 +350,13 @@ i64); define @intrinsic_vmfge_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv4f32.f32( %0, float %1, @@ -306,10 +373,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv4f32.f32( %0, %1, @@ -326,10 +399,13 @@ i64); define @intrinsic_vmfge_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv8f32.f32( %0, float %1, @@ -346,10 +422,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv8f32.f32( %0, %1, @@ -366,10 +448,13 @@ i64); define @intrinsic_vmfge_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv1f64.f64( %0, double %1, @@ -386,10 +471,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv1f64.f64( %0, %1, @@ -406,10 +497,13 @@ i64); define @intrinsic_vmfge_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv2f64.f64( %0, double %1, @@ -426,10 +520,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv2f64.f64( %0, %1, @@ -446,10 +546,13 @@ i64); define @intrinsic_vmfge_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vmfge.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfge.nxv4f64.f64( %0, double %1, @@ -466,10 +569,16 @@ i64); define @intrinsic_vmfge_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfge.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfge.mask.nxv4f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfgt.nxv1f16.f16( @@ -6,10 +7,13 @@ i32); define @intrinsic_vmfgt_vf_nxv1f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv1f16.f16( %0, half %1, @@ -26,10 +30,16 @@ i32); define @intrinsic_vmfgt_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv1f16.f16( %0, %1, @@ -46,10 +56,13 @@ i32); define @intrinsic_vmfgt_vf_nxv2f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv2f16.f16( %0, half %1, @@ -66,10 +79,16 @@ i32); define @intrinsic_vmfgt_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv2f16.f16( %0, %1, @@ -86,10 +105,13 @@ i32); define @intrinsic_vmfgt_vf_nxv4f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv4f16.f16( %0, half %1, @@ -106,10 +128,16 @@ i32); define @intrinsic_vmfgt_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv4f16.f16( %0, %1, @@ -126,10 +154,13 @@ i32); define @intrinsic_vmfgt_vf_nxv8f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv8f16.f16( %0, half %1, @@ -146,10 +177,16 @@ i32); define @intrinsic_vmfgt_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv8f16.f16( %0, %1, @@ -166,10 +203,13 @@ i32); define @intrinsic_vmfgt_vf_nxv16f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv16f16.f16( %0, half %1, @@ -186,10 +226,16 @@ i32); define @intrinsic_vmfgt_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv16f16.f16( %0, %1, @@ -206,10 +252,13 @@ i32); define @intrinsic_vmfgt_vf_nxv1f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv1f32.f32( %0, float %1, @@ -226,10 +275,16 @@ i32); define @intrinsic_vmfgt_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv1f32.f32( %0, %1, @@ -246,10 +301,13 @@ i32); define @intrinsic_vmfgt_vf_nxv2f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv2f32.f32( %0, float %1, @@ -266,10 +324,16 @@ i32); define @intrinsic_vmfgt_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv2f32.f32( %0, %1, @@ -286,10 +350,13 @@ i32); define @intrinsic_vmfgt_vf_nxv4f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv4f32.f32( %0, float %1, @@ -306,10 +373,16 @@ i32); define @intrinsic_vmfgt_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv4f32.f32( %0, %1, @@ -326,10 +399,13 @@ i32); define @intrinsic_vmfgt_vf_nxv8f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv8f32.f32( %0, float %1, @@ -346,10 +422,16 @@ i32); define @intrinsic_vmfgt_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfgt.nxv1f16.f16( @@ -6,10 +7,13 @@ i64); define @intrinsic_vmfgt_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv1f16.f16( %0, half %1, @@ -26,10 +30,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv1f16.f16( %0, %1, @@ -46,10 +56,13 @@ i64); define @intrinsic_vmfgt_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv2f16.f16( %0, half %1, @@ -66,10 +79,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv2f16.f16( %0, %1, @@ -86,10 +105,13 @@ i64); define @intrinsic_vmfgt_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv4f16.f16( %0, half %1, @@ -106,10 +128,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv4f16.f16( %0, %1, @@ -126,10 +154,13 @@ i64); define @intrinsic_vmfgt_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv8f16.f16( %0, half %1, @@ -146,10 +177,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv8f16.f16( %0, %1, @@ -166,10 +203,13 @@ i64); define @intrinsic_vmfgt_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv16f16.f16( %0, half %1, @@ -186,10 +226,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv16f16.f16( %0, %1, @@ -206,10 +252,13 @@ i64); define @intrinsic_vmfgt_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv1f32.f32( %0, float %1, @@ -226,10 +275,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv1f32.f32( %0, %1, @@ -246,10 +301,13 @@ i64); define @intrinsic_vmfgt_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv2f32.f32( %0, float %1, @@ -266,10 +324,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv2f32.f32( %0, %1, @@ -286,10 +350,13 @@ i64); define @intrinsic_vmfgt_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv4f32.f32( %0, float %1, @@ -306,10 +373,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv4f32.f32( %0, %1, @@ -326,10 +399,13 @@ i64); define @intrinsic_vmfgt_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv8f32.f32( %0, float %1, @@ -346,10 +422,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv8f32.f32( %0, %1, @@ -366,10 +448,13 @@ i64); define @intrinsic_vmfgt_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv1f64.f64( %0, double %1, @@ -386,10 +471,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv1f64.f64( %0, %1, @@ -406,10 +497,13 @@ i64); define @intrinsic_vmfgt_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv2f64.f64( %0, double %1, @@ -426,10 +520,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv2f64.f64( %0, %1, @@ -446,10 +546,13 @@ i64); define @intrinsic_vmfgt_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vmfgt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfgt.nxv4f64.f64( %0, double %1, @@ -466,10 +569,16 @@ i64); define @intrinsic_vmfgt_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfgt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfgt.mask.nxv4f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfle.nxv1f16( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmfle_vv_nxv1f16_nxv1f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f16( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv1f16( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmfle_vv_nxv2f16_nxv2f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f16( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv2f16( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmfle_vv_nxv4f16_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f16( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv4f16( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmfle_vv_nxv8f16_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv8f16( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv8f16( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmfle_vv_nxv16f16_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv16f16( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv16f16( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmfle_vv_nxv1f32_nxv1f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f32( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv1f32( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmfle_vv_nxv2f32_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f32( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv2f32( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmfle_vv_nxv4f32_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f32( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv4f32( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmfle_vv_nxv8f32_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv8f32( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv8f32( %1, %2, @@ -402,10 +475,13 @@ i32); define @intrinsic_vmfle_vf_nxv1f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f16.f16( %0, half %1, @@ -422,10 +498,16 @@ i32); define @intrinsic_vmfle_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv1f16.f16( %0, %1, @@ -442,10 +524,13 @@ i32); define @intrinsic_vmfle_vf_nxv2f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f16.f16( %0, half %1, @@ -462,10 +547,16 @@ i32); define @intrinsic_vmfle_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv2f16.f16( %0, %1, @@ -482,10 +573,13 @@ i32); define @intrinsic_vmfle_vf_nxv4f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f16.f16( %0, half %1, @@ -502,10 +596,16 @@ i32); define @intrinsic_vmfle_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv4f16.f16( %0, %1, @@ -522,10 +622,13 @@ i32); define @intrinsic_vmfle_vf_nxv8f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv8f16.f16( %0, half %1, @@ -542,10 +645,16 @@ i32); define @intrinsic_vmfle_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv8f16.f16( %0, %1, @@ -562,10 +671,13 @@ i32); define @intrinsic_vmfle_vf_nxv16f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv16f16.f16( %0, half %1, @@ -582,10 +694,16 @@ i32); define @intrinsic_vmfle_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv16f16.f16( %0, %1, @@ -602,10 +720,13 @@ i32); define @intrinsic_vmfle_vf_nxv1f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f32.f32( %0, float %1, @@ -622,10 +743,16 @@ i32); define @intrinsic_vmfle_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv1f32.f32( %0, %1, @@ -642,10 +769,13 @@ i32); define @intrinsic_vmfle_vf_nxv2f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f32.f32( %0, float %1, @@ -662,10 +792,16 @@ i32); define @intrinsic_vmfle_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv2f32.f32( %0, %1, @@ -682,10 +818,13 @@ i32); define @intrinsic_vmfle_vf_nxv4f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f32.f32( %0, float %1, @@ -702,10 +841,16 @@ i32); define @intrinsic_vmfle_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv4f32.f32( %0, %1, @@ -722,10 +867,13 @@ i32); define @intrinsic_vmfle_vf_nxv8f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv8f32.f32( %0, float %1, @@ -742,10 +890,16 @@ i32); define @intrinsic_vmfle_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfle.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmfle_vv_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f16( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv1f16( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmfle_vv_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f16( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv2f16( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmfle_vv_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f16( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv4f16( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmfle_vv_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv8f16( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv8f16( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmfle_vv_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv16f16( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv16f16( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmfle_vv_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f32( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv1f32( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmfle_vv_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f32( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv2f32( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmfle_vv_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f32( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv4f32( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmfle_vv_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv8f32( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv8f32( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmfle_vv_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f64( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv1f64( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmfle_vv_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f64( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv2f64( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmfle_vv_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f64( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfle.nxv4f64( %1, %2, @@ -534,10 +631,13 @@ i64); define @intrinsic_vmfle_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f16.f16( %0, half %1, @@ -554,10 +654,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv1f16.f16( %0, %1, @@ -574,10 +680,13 @@ i64); define @intrinsic_vmfle_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f16.f16( %0, half %1, @@ -594,10 +703,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv2f16.f16( %0, %1, @@ -614,10 +729,13 @@ i64); define @intrinsic_vmfle_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f16.f16( %0, half %1, @@ -634,10 +752,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv4f16.f16( %0, %1, @@ -654,10 +778,13 @@ i64); define @intrinsic_vmfle_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv8f16.f16( %0, half %1, @@ -674,10 +801,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv8f16.f16( %0, %1, @@ -694,10 +827,13 @@ i64); define @intrinsic_vmfle_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv16f16.f16( %0, half %1, @@ -714,10 +850,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv16f16.f16( %0, %1, @@ -734,10 +876,13 @@ i64); define @intrinsic_vmfle_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f32.f32( %0, float %1, @@ -754,10 +899,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv1f32.f32( %0, %1, @@ -774,10 +925,13 @@ i64); define @intrinsic_vmfle_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f32.f32( %0, float %1, @@ -794,10 +948,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv2f32.f32( %0, %1, @@ -814,10 +974,13 @@ i64); define @intrinsic_vmfle_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f32.f32( %0, float %1, @@ -834,10 +997,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv4f32.f32( %0, %1, @@ -854,10 +1023,13 @@ i64); define @intrinsic_vmfle_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv8f32.f32( %0, float %1, @@ -874,10 +1046,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv8f32.f32( %0, %1, @@ -894,10 +1072,13 @@ i64); define @intrinsic_vmfle_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv1f64.f64( %0, double %1, @@ -914,10 +1095,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv1f64.f64( %0, %1, @@ -934,10 +1121,13 @@ i64); define @intrinsic_vmfle_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv2f64.f64( %0, double %1, @@ -954,10 +1144,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv2f64.f64( %0, %1, @@ -974,10 +1170,13 @@ i64); define @intrinsic_vmfle_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vmfle.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfle.nxv4f64.f64( %0, double %1, @@ -994,10 +1193,16 @@ i64); define @intrinsic_vmfle_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfle.mask.nxv4f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmflt.nxv1f16( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmflt_vv_nxv1f16_nxv1f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f16( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv1f16( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmflt_vv_nxv2f16_nxv2f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f16( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv2f16( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmflt_vv_nxv4f16_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f16( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv4f16( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmflt_vv_nxv8f16_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv8f16( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv8f16( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmflt_vv_nxv16f16_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv16f16( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv16f16( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmflt_vv_nxv1f32_nxv1f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f32( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv1f32( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmflt_vv_nxv2f32_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f32( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv2f32( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmflt_vv_nxv4f32_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f32( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv4f32( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmflt_vv_nxv8f32_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv8f32( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv8f32( %1, %2, @@ -402,10 +475,13 @@ i32); define @intrinsic_vmflt_vf_nxv1f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f16.f16( %0, half %1, @@ -422,10 +498,16 @@ i32); define @intrinsic_vmflt_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv1f16.f16( %0, %1, @@ -442,10 +524,13 @@ i32); define @intrinsic_vmflt_vf_nxv2f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f16.f16( %0, half %1, @@ -462,10 +547,16 @@ i32); define @intrinsic_vmflt_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv2f16.f16( %0, %1, @@ -482,10 +573,13 @@ i32); define @intrinsic_vmflt_vf_nxv4f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f16.f16( %0, half %1, @@ -502,10 +596,16 @@ i32); define @intrinsic_vmflt_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv4f16.f16( %0, %1, @@ -522,10 +622,13 @@ i32); define @intrinsic_vmflt_vf_nxv8f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv8f16.f16( %0, half %1, @@ -542,10 +645,16 @@ i32); define @intrinsic_vmflt_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv8f16.f16( %0, %1, @@ -562,10 +671,13 @@ i32); define @intrinsic_vmflt_vf_nxv16f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv16f16.f16( %0, half %1, @@ -582,10 +694,16 @@ i32); define @intrinsic_vmflt_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv16f16.f16( %0, %1, @@ -602,10 +720,13 @@ i32); define @intrinsic_vmflt_vf_nxv1f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f32.f32( %0, float %1, @@ -622,10 +743,16 @@ i32); define @intrinsic_vmflt_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv1f32.f32( %0, %1, @@ -642,10 +769,13 @@ i32); define @intrinsic_vmflt_vf_nxv2f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f32.f32( %0, float %1, @@ -662,10 +792,16 @@ i32); define @intrinsic_vmflt_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv2f32.f32( %0, %1, @@ -682,10 +818,13 @@ i32); define @intrinsic_vmflt_vf_nxv4f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f32.f32( %0, float %1, @@ -702,10 +841,16 @@ i32); define @intrinsic_vmflt_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv4f32.f32( %0, %1, @@ -722,10 +867,13 @@ i32); define @intrinsic_vmflt_vf_nxv8f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv8f32.f32( %0, float %1, @@ -742,10 +890,16 @@ i32); define @intrinsic_vmflt_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmflt.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmflt_vv_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f16( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv1f16( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmflt_vv_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f16( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv2f16( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmflt_vv_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f16( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv4f16( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmflt_vv_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv8f16( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv8f16( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmflt_vv_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv16f16( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv16f16( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmflt_vv_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f32( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv1f32( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmflt_vv_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f32( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv2f32( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmflt_vv_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f32( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv4f32( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmflt_vv_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv8f32( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv8f32( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmflt_vv_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f64( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv1f64( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmflt_vv_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f64( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv2f64( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmflt_vv_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f64( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmflt.nxv4f64( %1, %2, @@ -534,10 +631,13 @@ i64); define @intrinsic_vmflt_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f16.f16( %0, half %1, @@ -554,10 +654,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv1f16.f16( %0, %1, @@ -574,10 +680,13 @@ i64); define @intrinsic_vmflt_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f16.f16( %0, half %1, @@ -594,10 +703,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv2f16.f16( %0, %1, @@ -614,10 +729,13 @@ i64); define @intrinsic_vmflt_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f16.f16( %0, half %1, @@ -634,10 +752,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv4f16.f16( %0, %1, @@ -654,10 +778,13 @@ i64); define @intrinsic_vmflt_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv8f16.f16( %0, half %1, @@ -674,10 +801,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv8f16.f16( %0, %1, @@ -694,10 +827,13 @@ i64); define @intrinsic_vmflt_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv16f16.f16( %0, half %1, @@ -714,10 +850,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv16f16.f16( %0, %1, @@ -734,10 +876,13 @@ i64); define @intrinsic_vmflt_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f32.f32( %0, float %1, @@ -754,10 +899,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv1f32.f32( %0, %1, @@ -774,10 +925,13 @@ i64); define @intrinsic_vmflt_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f32.f32( %0, float %1, @@ -794,10 +948,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv2f32.f32( %0, %1, @@ -814,10 +974,13 @@ i64); define @intrinsic_vmflt_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f32.f32( %0, float %1, @@ -834,10 +997,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv4f32.f32( %0, %1, @@ -854,10 +1023,13 @@ i64); define @intrinsic_vmflt_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv8f32.f32( %0, float %1, @@ -874,10 +1046,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv8f32.f32( %0, %1, @@ -894,10 +1072,13 @@ i64); define @intrinsic_vmflt_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv1f64.f64( %0, double %1, @@ -914,10 +1095,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv1f64.f64( %0, %1, @@ -934,10 +1121,13 @@ i64); define @intrinsic_vmflt_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv2f64.f64( %0, double %1, @@ -954,10 +1144,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv2f64.f64( %0, %1, @@ -974,10 +1170,13 @@ i64); define @intrinsic_vmflt_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vmflt.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmflt.nxv4f64.f64( %0, double %1, @@ -994,10 +1193,16 @@ i64); define @intrinsic_vmflt_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmflt.mask.nxv4f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfne.nxv1f16( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmfne_vv_nxv1f16_nxv1f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f16( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv1f16( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmfne_vv_nxv2f16_nxv2f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f16( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv2f16( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmfne_vv_nxv4f16_nxv4f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f16( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv4f16( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmfne_vv_nxv8f16_nxv8f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv8f16( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv8f16( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmfne_vv_nxv16f16_nxv16f16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv16f16( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv16f16( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmfne_vv_nxv1f32_nxv1f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f32( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv1f32( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmfne_vv_nxv2f32_nxv2f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f32( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv2f32( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmfne_vv_nxv4f32_nxv4f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f32( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv4f32( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmfne_vv_nxv8f32_nxv8f32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv8f32( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv8f32( %1, %2, @@ -402,10 +475,13 @@ i32); define @intrinsic_vmfne_vf_nxv1f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f16.f16( %0, half %1, @@ -422,10 +498,16 @@ i32); define @intrinsic_vmfne_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv1f16.f16( %0, %1, @@ -442,10 +524,13 @@ i32); define @intrinsic_vmfne_vf_nxv2f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f16.f16( %0, half %1, @@ -462,10 +547,16 @@ i32); define @intrinsic_vmfne_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv2f16.f16( %0, %1, @@ -482,10 +573,13 @@ i32); define @intrinsic_vmfne_vf_nxv4f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f16.f16( %0, half %1, @@ -502,10 +596,16 @@ i32); define @intrinsic_vmfne_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv4f16.f16( %0, %1, @@ -522,10 +622,13 @@ i32); define @intrinsic_vmfne_vf_nxv8f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv8f16.f16( %0, half %1, @@ -542,10 +645,16 @@ i32); define @intrinsic_vmfne_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv8f16.f16( %0, %1, @@ -562,10 +671,13 @@ i32); define @intrinsic_vmfne_vf_nxv16f16_f16( %0, half %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv16f16.f16( %0, half %1, @@ -582,10 +694,16 @@ i32); define @intrinsic_vmfne_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv16f16.f16( %0, %1, @@ -602,10 +720,13 @@ i32); define @intrinsic_vmfne_vf_nxv1f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f32.f32( %0, float %1, @@ -622,10 +743,16 @@ i32); define @intrinsic_vmfne_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv1f32.f32( %0, %1, @@ -642,10 +769,13 @@ i32); define @intrinsic_vmfne_vf_nxv2f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f32.f32( %0, float %1, @@ -662,10 +792,16 @@ i32); define @intrinsic_vmfne_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv2f32.f32( %0, %1, @@ -682,10 +818,13 @@ i32); define @intrinsic_vmfne_vf_nxv4f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f32.f32( %0, float %1, @@ -702,10 +841,16 @@ i32); define @intrinsic_vmfne_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv4f32.f32( %0, %1, @@ -722,10 +867,13 @@ i32); define @intrinsic_vmfne_vf_nxv8f32_f32( %0, float %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv8f32.f32( %0, float %1, @@ -742,10 +890,16 @@ i32); define @intrinsic_vmfne_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv8f32.f32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmfne.nxv1f16( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmfne_vv_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f16( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv1f16( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmfne_vv_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f16( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv2f16( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmfne_vv_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f16( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv4f16( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmfne_vv_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv8f16( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv8f16( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmfne_vv_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv16f16( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv16f16( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmfne_vv_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f32( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv1f32( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmfne_vv_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f32( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv2f32( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmfne_vv_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f32( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv4f32( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmfne_vv_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv8f32( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv8f32( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmfne_vv_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f64( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv1f64( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmfne_vv_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f64( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv2f64( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmfne_vv_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f64( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmfne.nxv4f64( %1, %2, @@ -534,10 +631,13 @@ i64); define @intrinsic_vmfne_vf_nxv1f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f16.f16( %0, half %1, @@ -554,10 +654,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv1f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv1f16.f16( %0, %1, @@ -574,10 +680,13 @@ i64); define @intrinsic_vmfne_vf_nxv2f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f16.f16( %0, half %1, @@ -594,10 +703,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv2f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv2f16.f16( %0, %1, @@ -614,10 +729,13 @@ i64); define @intrinsic_vmfne_vf_nxv4f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f16.f16( %0, half %1, @@ -634,10 +752,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv4f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv4f16.f16( %0, %1, @@ -654,10 +778,13 @@ i64); define @intrinsic_vmfne_vf_nxv8f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv8f16.f16( %0, half %1, @@ -674,10 +801,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv8f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv8f16.f16( %0, %1, @@ -694,10 +827,13 @@ i64); define @intrinsic_vmfne_vf_nxv16f16_f16( %0, half %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv16f16.f16( %0, half %1, @@ -714,10 +850,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv16f16_f16( %0, %1, half %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.h.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv16f16.f16( %0, %1, @@ -734,10 +876,13 @@ i64); define @intrinsic_vmfne_vf_nxv1f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f32.f32( %0, float %1, @@ -754,10 +899,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv1f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv1f32.f32( %0, %1, @@ -774,10 +925,13 @@ i64); define @intrinsic_vmfne_vf_nxv2f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f32.f32( %0, float %1, @@ -794,10 +948,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv2f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv2f32.f32( %0, %1, @@ -814,10 +974,13 @@ i64); define @intrinsic_vmfne_vf_nxv4f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f32.f32( %0, float %1, @@ -834,10 +997,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv4f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv4f32.f32( %0, %1, @@ -854,10 +1023,13 @@ i64); define @intrinsic_vmfne_vf_nxv8f32_f32( %0, float %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv8f32.f32( %0, float %1, @@ -874,10 +1046,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv8f32_f32( %0, %1, float %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.w.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv8f32.f32( %0, %1, @@ -894,10 +1072,13 @@ i64); define @intrinsic_vmfne_vf_nxv1f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv1f64.f64( %0, double %1, @@ -914,10 +1095,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv1f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv1f64.f64( %0, %1, @@ -934,10 +1121,13 @@ i64); define @intrinsic_vmfne_vf_nxv2f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv2f64.f64( %0, double %1, @@ -954,10 +1144,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv2f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv2f64.f64( %0, %1, @@ -974,10 +1170,13 @@ i64); define @intrinsic_vmfne_vf_nxv4f64_f64( %0, double %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,ta,mu +; CHECK-NEXT: vmfne.vf v0, v8, ft0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}} %a = call @llvm.riscv.vmfne.nxv4f64.f64( %0, double %1, @@ -994,10 +1193,16 @@ i64); define @intrinsic_vmfne_mask_vf_nxv4f64_f64( %0, %1, double %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: fmv.d.x ft0, a0 +; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t %a = call @llvm.riscv.vmfne.mask.nxv4f64.f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmin.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vmin_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vmin_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vmin_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vmin_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vmin_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vmin_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vmin_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vmin_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vmin_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vmin_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vmin_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vmin_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vmin_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vmin_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vmin_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vmin_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vmin_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vmin_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vmin_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vmin_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vmin_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vmin_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vmin_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmin.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vmin_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmin.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vmin_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmin.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vmin_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vmin_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vmin_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vmin_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmin.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vmin_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmin.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vmin_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmin.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vmin_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vmin_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vmin_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmin.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vmin_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmin.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vmin_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vmin_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmin.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmin.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vmin_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vmin_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vmin_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vmin_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vmin_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vmin_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vmin_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vmin_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vmin_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vmin_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vmin_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vmin_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vmin_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vmin_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vmin_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vmin_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vmin_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vmin_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmin.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vmin_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmin.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vmin_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vmin_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmin.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vmin_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vmin.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vmin_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vmin_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vmin_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vmin_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vmin_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmin.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vmin_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmin.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vmin_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmin.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vmin_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vmin_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vmin_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vmin_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmin.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vmin_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmin.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vmin_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmin.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vmin_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vmin_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vmin_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmin.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vmin_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmin.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vmin_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmin.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vmin_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmin.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vmin_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmin.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vmin_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmin.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vmin_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmin_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmin.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmin.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vmin_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vmin.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmin_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmin.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmin.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -16,7 +16,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -30,7 +30,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,7 +43,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -54,7 +54,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -81,7 +81,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -92,7 +92,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,7 +106,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -119,7 +119,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -130,7 +130,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -144,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vmin_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v18 +; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -168,7 +168,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -195,7 +195,7 @@ ; CHECK-LABEL: vmin_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v20 +; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -206,7 +206,7 @@ ; CHECK-LABEL: vmin_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -220,7 +220,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,9 +232,8 @@ define @vmin_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -245,7 +244,7 @@ ; CHECK-LABEL: vmin_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -259,7 +258,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -272,7 +271,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -283,7 +282,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -297,7 +296,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -335,7 +334,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +347,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -359,7 +358,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,7 +372,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -386,7 +385,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v18 +; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -397,7 +396,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -411,7 +410,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -424,7 +423,7 @@ ; CHECK-LABEL: vmin_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v20 +; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -435,7 +434,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,9 +460,8 @@ define @vmin_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -474,7 +472,7 @@ ; CHECK-LABEL: vmin_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +486,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -501,7 +499,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -512,7 +510,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -526,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -550,7 +548,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -564,7 +562,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v18 +; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -588,7 +586,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -602,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -615,7 +613,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v20 +; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -626,7 +624,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,7 +638,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -652,9 +650,8 @@ define @vmin_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -665,7 +662,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +676,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -710,7 +707,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vmin.vv v16, v16, v25 +; CHECK-NEXT: vmin.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -724,7 +721,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -737,7 +734,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v18 +; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -755,7 +752,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vmin.vv v16, v16, v26 +; CHECK-NEXT: vmin.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -769,7 +766,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -782,7 +779,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v20 +; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -796,11 +793,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vmin.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vmin.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -814,7 +811,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -826,9 +823,8 @@ define @vmin_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -839,14 +835,14 @@ ; CHECK-LABEL: vmin_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmin.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -860,7 +856,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -16,7 +16,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -30,7 +30,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,7 +43,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -54,7 +54,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -81,7 +81,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -92,7 +92,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,7 +106,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -119,7 +119,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -130,7 +130,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -144,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vmin_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v18 +; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -168,7 +168,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -195,7 +195,7 @@ ; CHECK-LABEL: vmin_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v20 +; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -206,7 +206,7 @@ ; CHECK-LABEL: vmin_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -220,7 +220,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,9 +232,8 @@ define @vmin_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -245,7 +244,7 @@ ; CHECK-LABEL: vmin_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -259,7 +258,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -272,7 +271,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -283,7 +282,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -297,7 +296,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -335,7 +334,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +347,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -359,7 +358,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,7 +372,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -386,7 +385,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v18 +; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -397,7 +396,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -411,7 +410,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -424,7 +423,7 @@ ; CHECK-LABEL: vmin_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v20 +; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -435,7 +434,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,9 +460,8 @@ define @vmin_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -474,7 +472,7 @@ ; CHECK-LABEL: vmin_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +486,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -501,7 +499,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -512,7 +510,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -526,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -550,7 +548,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -564,7 +562,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v18 +; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -588,7 +586,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -602,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -615,7 +613,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v20 +; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -626,7 +624,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,7 +638,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -652,9 +650,8 @@ define @vmin_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -665,7 +662,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +676,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v17 +; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -703,7 +700,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -717,7 +714,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -730,7 +727,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v18 +; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -741,7 +738,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -755,7 +752,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -768,7 +765,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmin.vv v16, v16, v20 +; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -779,7 +776,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -793,7 +790,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -805,9 +802,8 @@ define @vmin_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmin.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp slt %va, %vb %vc = select %cmp, %va, %vb @@ -818,7 +814,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -832,7 +828,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmin.vx v16, v16, a0 +; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vminu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vminu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vminu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vminu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vminu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vminu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vminu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vminu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vminu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vminu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vminu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vminu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vminu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vminu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vminu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vminu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vminu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vminu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vminu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vminu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vminu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vminu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vminu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vminu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vminu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vminu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vminu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vminu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vminu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vminu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vminu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vminu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vminu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vminu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vminu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vminu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vminu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vminu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vminu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vminu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vminu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vminu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vminu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vminu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vminu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vminu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vminu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vminu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vminu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vminu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vminu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vminu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vminu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vminu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vminu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vminu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vminu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vminu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vminu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vminu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vminu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vminu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vminu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vminu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vminu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vminu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vminu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vminu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vminu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vminu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vminu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vminu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vminu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vminu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vminu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vminu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vminu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vminu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vminu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vminu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vminu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vminu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vminu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vminu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vminu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vminu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vminu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vminu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vminu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vminu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vminu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vminu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vminu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vminu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vminu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vminu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vminu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vminu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vminu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vminu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vminu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vminu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vminu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vminu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vminu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vminu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vminu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vminu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vminu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vminu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vminu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vminu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vminu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vminu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vminu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vminu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -16,7 +16,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -30,7 +30,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,7 +43,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -54,7 +54,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -81,7 +81,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -92,7 +92,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,7 +106,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -119,7 +119,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -130,7 +130,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -144,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vmin_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v18 +; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -168,7 +168,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -195,7 +195,7 @@ ; CHECK-LABEL: vmin_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v20 +; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -206,7 +206,7 @@ ; CHECK-LABEL: vmin_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -220,7 +220,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,9 +232,8 @@ define @vmin_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vminu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -245,7 +244,7 @@ ; CHECK-LABEL: vmin_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -259,7 +258,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -272,7 +271,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -283,7 +282,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -297,7 +296,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -335,7 +334,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +347,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -359,7 +358,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,7 +372,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -386,7 +385,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v18 +; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -397,7 +396,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -411,7 +410,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -424,7 +423,7 @@ ; CHECK-LABEL: vmin_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v20 +; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -435,7 +434,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,9 +460,8 @@ define @vmin_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vminu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -474,7 +472,7 @@ ; CHECK-LABEL: vmin_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +486,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -501,7 +499,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -512,7 +510,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -526,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -550,7 +548,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -564,7 +562,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v18 +; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -588,7 +586,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -602,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -615,7 +613,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v20 +; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -626,7 +624,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,7 +638,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -652,9 +650,8 @@ define @vmin_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vminu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -665,7 +662,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +676,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -710,7 +707,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vminu.vv v16, v16, v25 +; CHECK-NEXT: vminu.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -724,7 +721,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -737,7 +734,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v18 +; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -755,7 +752,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vminu.vv v16, v16, v26 +; CHECK-NEXT: vminu.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -769,7 +766,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -782,7 +779,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v20 +; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -796,11 +793,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vminu.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vminu.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -814,7 +811,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -826,9 +823,8 @@ define @vmin_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vminu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -839,14 +835,14 @@ ; CHECK-LABEL: vmin_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vminu.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -860,7 +856,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -16,7 +16,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -30,7 +30,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,7 +43,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -54,7 +54,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -68,7 +68,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -81,7 +81,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -92,7 +92,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -106,7 +106,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -119,7 +119,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -130,7 +130,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -144,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vmin_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v18 +; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -168,7 +168,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -195,7 +195,7 @@ ; CHECK-LABEL: vmin_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v20 +; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -206,7 +206,7 @@ ; CHECK-LABEL: vmin_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -220,7 +220,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,9 +232,8 @@ define @vmin_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vminu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -245,7 +244,7 @@ ; CHECK-LABEL: vmin_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -259,7 +258,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -272,7 +271,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -283,7 +282,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -297,7 +296,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -310,7 +309,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -335,7 +334,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +347,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -359,7 +358,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -373,7 +372,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -386,7 +385,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v18 +; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -397,7 +396,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -411,7 +410,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -424,7 +423,7 @@ ; CHECK-LABEL: vmin_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v20 +; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -435,7 +434,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,9 +460,8 @@ define @vmin_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vminu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -474,7 +472,7 @@ ; CHECK-LABEL: vmin_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +486,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -501,7 +499,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -512,7 +510,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -526,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -550,7 +548,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -564,7 +562,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v18 +; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -588,7 +586,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -602,7 +600,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -615,7 +613,7 @@ ; CHECK-LABEL: vmin_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v20 +; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -626,7 +624,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -640,7 +638,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -652,9 +650,8 @@ define @vmin_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vminu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -665,7 +662,7 @@ ; CHECK-LABEL: vmin_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +676,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -692,7 +689,7 @@ ; CHECK-LABEL: vmin_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v17 +; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -703,7 +700,7 @@ ; CHECK-LABEL: vmin_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -717,7 +714,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -730,7 +727,7 @@ ; CHECK-LABEL: vmin_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v18 +; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -741,7 +738,7 @@ ; CHECK-LABEL: vmin_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -755,7 +752,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -768,7 +765,7 @@ ; CHECK-LABEL: vmin_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vminu.vv v16, v16, v20 +; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -779,7 +776,7 @@ ; CHECK-LABEL: vmin_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -793,7 +790,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -805,9 +802,8 @@ define @vmin_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmin_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vminu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret %cmp = icmp ult %va, %vb %vc = select %cmp, %va, %vb @@ -818,7 +814,7 @@ ; CHECK-LABEL: vmin_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -832,7 +828,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -3 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vminu.vx v16, v16, a0 +; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmnand.nxv1i1( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmnand_mm_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmnand_mm_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmnand_mm_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmnand_mm_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmnand_mm_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmnand_mm_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmnand_mm_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmnand.nxv1i1( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmnand_mm_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmnand_mm_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmnand_mm_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmnand_mm_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmnand_mm_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmnand_mm_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmnand_mm_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmnand.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnand.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmnor.nxv1i1( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmnor_mm_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmnor_mm_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmnor_mm_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmnor_mm_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmnor_mm_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmnor_mm_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmnor_mm_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmnor.nxv1i1( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmnor_mm_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmnor_mm_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmnor_mm_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmnor_mm_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmnor_mm_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmnor_mm_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmnor_mm_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmnor.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmor.nxv1i1( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmor_mm_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmor_mm_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmor_mm_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmor_mm_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmor_mm_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmor_mm_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmor_mm_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmor.nxv1i1( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmor_mm_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmor_mm_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmor_mm_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmor_mm_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmor_mm_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmor_mm_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmor_mm_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmor.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmornot.nxv1i1( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmornot_mm_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmornot_mm_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmornot_mm_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmornot_mm_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmornot_mm_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmornot_mm_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmornot_mm_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmornot.nxv1i1( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmornot_mm_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmornot_mm_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmornot_mm_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmornot_mm_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmornot_mm_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmornot_mm_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmornot_mm_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmornot_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmornot.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmornot_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmornot.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmsbc_vv_nxv1i1_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmsbc_vv_nxv2i1_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmsbc_vv_nxv4i1_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i8.nxv4i8( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmsbc_vv_nxv8i1_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i8.nxv8i8( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmsbc_vv_nxv16i1_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i8.nxv16i8( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmsbc_vv_nxv32i1_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv32i8.nxv32i8( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmsbc_vv_nxv64i1_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv64i1_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv64i1_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv64i8.nxv64i8( %0, %1, @@ -132,10 +147,12 @@ i32); define @intrinsic_vmsbc_vv_nxv1i1_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i16.nxv1i16( %0, %1, @@ -150,10 +167,12 @@ i32); define @intrinsic_vmsbc_vv_nxv2i1_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i16.nxv2i16( %0, %1, @@ -168,10 +187,12 @@ i32); define @intrinsic_vmsbc_vv_nxv4i1_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i16.nxv4i16( %0, %1, @@ -186,10 +207,12 @@ i32); define @intrinsic_vmsbc_vv_nxv8i1_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i16.nxv8i16( %0, %1, @@ -204,10 +227,12 @@ i32); define @intrinsic_vmsbc_vv_nxv16i1_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i16.nxv16i16( %0, %1, @@ -222,10 +247,12 @@ i32); define @intrinsic_vmsbc_vv_nxv32i1_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv32i16.nxv32i16( %0, %1, @@ -240,10 +267,12 @@ i32); define @intrinsic_vmsbc_vv_nxv1i1_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i32.nxv1i32( %0, %1, @@ -258,10 +287,12 @@ i32); define @intrinsic_vmsbc_vv_nxv2i1_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i32.nxv2i32( %0, %1, @@ -276,10 +307,12 @@ i32); define @intrinsic_vmsbc_vv_nxv4i1_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i32.nxv4i32( %0, %1, @@ -294,10 +327,12 @@ i32); define @intrinsic_vmsbc_vv_nxv8i1_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i32.nxv8i32( %0, %1, @@ -312,10 +347,12 @@ i32); define @intrinsic_vmsbc_vv_nxv16i1_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i32.nxv16i32( %0, %1, @@ -330,10 +367,12 @@ i32); define @intrinsic_vmsbc_vx_nxv1i1_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i8.i8( %0, i8 %1, @@ -348,10 +387,12 @@ i32); define @intrinsic_vmsbc_vx_nxv2i1_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i8.i8( %0, i8 %1, @@ -366,10 +407,12 @@ i32); define @intrinsic_vmsbc_vx_nxv4i1_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i8.i8( %0, i8 %1, @@ -384,10 +427,12 @@ i32); define @intrinsic_vmsbc_vx_nxv8i1_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i8.i8( %0, i8 %1, @@ -402,10 +447,12 @@ i32); define @intrinsic_vmsbc_vx_nxv16i1_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i8.i8( %0, i8 %1, @@ -420,10 +467,12 @@ i32); define @intrinsic_vmsbc_vx_nxv32i1_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv32i8.i8( %0, i8 %1, @@ -438,10 +487,12 @@ i32); define @intrinsic_vmsbc_vx_nxv64i1_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv64i8.i8( %0, i8 %1, @@ -456,10 +507,12 @@ i32); define @intrinsic_vmsbc_vx_nxv1i1_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i16.i16( %0, i16 %1, @@ -474,10 +527,12 @@ i32); define @intrinsic_vmsbc_vx_nxv2i1_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i16.i16( %0, i16 %1, @@ -492,10 +547,12 @@ i32); define @intrinsic_vmsbc_vx_nxv4i1_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i16.i16( %0, i16 %1, @@ -510,10 +567,12 @@ i32); define @intrinsic_vmsbc_vx_nxv8i1_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i16.i16( %0, i16 %1, @@ -528,10 +587,12 @@ i32); define @intrinsic_vmsbc_vx_nxv16i1_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i16.i16( %0, i16 %1, @@ -546,10 +607,12 @@ i32); define @intrinsic_vmsbc_vx_nxv32i1_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv32i16.i16( %0, i16 %1, @@ -564,10 +627,12 @@ i32); define @intrinsic_vmsbc_vx_nxv1i1_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i32.i32( %0, i32 %1, @@ -582,10 +647,12 @@ i32); define @intrinsic_vmsbc_vx_nxv2i1_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i32.i32( %0, i32 %1, @@ -600,10 +667,12 @@ i32); define @intrinsic_vmsbc_vx_nxv4i1_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i32.i32( %0, i32 %1, @@ -618,10 +687,12 @@ i32); define @intrinsic_vmsbc_vx_nxv8i1_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i32.i32( %0, i32 %1, @@ -636,10 +707,12 @@ i32); define @intrinsic_vmsbc_vx_nxv16i1_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i32.i32( %0, i32 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbc-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsbc.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmsbc_vv_nxv1i1_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i8.nxv1i8( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmsbc_vv_nxv2i1_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i8.nxv2i8( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmsbc_vv_nxv4i1_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i8.nxv4i8( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmsbc_vv_nxv8i1_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i8.nxv8i8( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmsbc_vv_nxv16i1_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i8.nxv16i8( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmsbc_vv_nxv32i1_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv32i8.nxv32i8( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmsbc_vv_nxv64i1_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv64i1_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv64i1_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv64i8.nxv64i8( %0, %1, @@ -132,10 +147,12 @@ i64); define @intrinsic_vmsbc_vv_nxv1i1_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i16.nxv1i16( %0, %1, @@ -150,10 +167,12 @@ i64); define @intrinsic_vmsbc_vv_nxv2i1_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i16.nxv2i16( %0, %1, @@ -168,10 +187,12 @@ i64); define @intrinsic_vmsbc_vv_nxv4i1_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i16.nxv4i16( %0, %1, @@ -186,10 +207,12 @@ i64); define @intrinsic_vmsbc_vv_nxv8i1_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i16.nxv8i16( %0, %1, @@ -204,10 +227,12 @@ i64); define @intrinsic_vmsbc_vv_nxv16i1_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i16.nxv16i16( %0, %1, @@ -222,10 +247,12 @@ i64); define @intrinsic_vmsbc_vv_nxv32i1_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv32i1_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv32i16.nxv32i16( %0, %1, @@ -240,10 +267,12 @@ i64); define @intrinsic_vmsbc_vv_nxv1i1_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i32.nxv1i32( %0, %1, @@ -258,10 +287,12 @@ i64); define @intrinsic_vmsbc_vv_nxv2i1_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i32.nxv2i32( %0, %1, @@ -276,10 +307,12 @@ i64); define @intrinsic_vmsbc_vv_nxv4i1_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i32.nxv4i32( %0, %1, @@ -294,10 +327,12 @@ i64); define @intrinsic_vmsbc_vv_nxv8i1_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i32.nxv8i32( %0, %1, @@ -312,10 +347,12 @@ i64); define @intrinsic_vmsbc_vv_nxv16i1_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv16i1_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i32.nxv16i32( %0, %1, @@ -330,10 +367,12 @@ i64); define @intrinsic_vmsbc_vv_nxv1i1_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv1i1_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i64.nxv1i64( %0, %1, @@ -348,10 +387,12 @@ i64); define @intrinsic_vmsbc_vv_nxv2i1_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv2i1_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i64.nxv2i64( %0, %1, @@ -366,10 +407,12 @@ i64); define @intrinsic_vmsbc_vv_nxv4i1_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv4i1_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i64.nxv4i64( %0, %1, @@ -384,10 +427,12 @@ i64); define @intrinsic_vmsbc_vv_nxv8i1_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmsbc.vv v0, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vv_nxv8i1_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmsbc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i64.nxv8i64( %0, %1, @@ -402,10 +447,12 @@ i64); define @intrinsic_vmsbc_vx_nxv1i1_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i8.i8( %0, i8 %1, @@ -420,10 +467,12 @@ i64); define @intrinsic_vmsbc_vx_nxv2i1_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i8.i8( %0, i8 %1, @@ -438,10 +487,12 @@ i64); define @intrinsic_vmsbc_vx_nxv4i1_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i8.i8( %0, i8 %1, @@ -456,10 +507,12 @@ i64); define @intrinsic_vmsbc_vx_nxv8i1_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i8.i8( %0, i8 %1, @@ -474,10 +527,12 @@ i64); define @intrinsic_vmsbc_vx_nxv16i1_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i8.i8( %0, i8 %1, @@ -492,10 +547,12 @@ i64); define @intrinsic_vmsbc_vx_nxv32i1_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv32i8.i8( %0, i8 %1, @@ -510,10 +567,12 @@ i64); define @intrinsic_vmsbc_vx_nxv64i1_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv64i8.i8( %0, i8 %1, @@ -528,10 +587,12 @@ i64); define @intrinsic_vmsbc_vx_nxv1i1_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i16.i16( %0, i16 %1, @@ -546,10 +607,12 @@ i64); define @intrinsic_vmsbc_vx_nxv2i1_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i16.i16( %0, i16 %1, @@ -564,10 +627,12 @@ i64); define @intrinsic_vmsbc_vx_nxv4i1_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i16.i16( %0, i16 %1, @@ -582,10 +647,12 @@ i64); define @intrinsic_vmsbc_vx_nxv8i1_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i16.i16( %0, i16 %1, @@ -600,10 +667,12 @@ i64); define @intrinsic_vmsbc_vx_nxv16i1_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i16.i16( %0, i16 %1, @@ -618,10 +687,12 @@ i64); define @intrinsic_vmsbc_vx_nxv32i1_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv32i16.i16( %0, i16 %1, @@ -636,10 +707,12 @@ i64); define @intrinsic_vmsbc_vx_nxv1i1_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i32.i32( %0, i32 %1, @@ -654,10 +727,12 @@ i64); define @intrinsic_vmsbc_vx_nxv2i1_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i32.i32( %0, i32 %1, @@ -672,10 +747,12 @@ i64); define @intrinsic_vmsbc_vx_nxv4i1_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i32.i32( %0, i32 %1, @@ -690,10 +767,12 @@ i64); define @intrinsic_vmsbc_vx_nxv8i1_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i32.i32( %0, i32 %1, @@ -708,10 +787,12 @@ i64); define @intrinsic_vmsbc_vx_nxv16i1_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv16i32.i32( %0, i32 %1, @@ -726,10 +807,12 @@ i64); define @intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv1i1_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv1i64.i64( %0, i64 %1, @@ -744,10 +827,12 @@ i64); define @intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv2i1_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv2i64.i64( %0, i64 %1, @@ -762,10 +847,12 @@ i64); define @intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv4i1_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv4i64.i64( %0, i64 %1, @@ -780,10 +867,12 @@ i64); define @intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmsbc.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc_vx_nxv8i1_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmsbc.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsbc.nxv8i64.i64( %0, i64 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8( @@ -7,10 +8,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +31,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +54,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +77,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +100,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +123,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +146,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +169,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +192,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +215,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +238,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +261,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +284,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +307,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +330,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +353,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +376,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +399,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +422,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8( %0, i8 %1, @@ -387,10 +445,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8( %0, i8 %1, @@ -407,10 +468,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.i8( %0, i8 %1, @@ -427,10 +491,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i8.i8( %0, i8 %1, @@ -447,10 +514,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i8.i8( %0, i8 %1, @@ -467,10 +537,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i8.i8( %0, i8 %1, @@ -487,10 +560,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv64i8.i8( %0, i8 %1, @@ -507,10 +583,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i16.i16( %0, i16 %1, @@ -527,10 +606,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i16.i16( %0, i16 %1, @@ -547,10 +629,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i16.i16( %0, i16 %1, @@ -567,10 +652,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i16.i16( %0, i16 %1, @@ -587,10 +675,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i16.i16( %0, i16 %1, @@ -607,10 +698,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i16.i16( %0, i16 %1, @@ -627,10 +721,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i32.i32( %0, i32 %1, @@ -647,10 +744,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i32.i32( %0, i32 %1, @@ -667,10 +767,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i32.i32( %0, i32 %1, @@ -687,10 +790,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i32.i32( %0, i32 %1, @@ -707,10 +813,13 @@ i32); define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i32.i32( %0, i32 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8( @@ -7,10 +8,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +31,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +54,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +77,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +100,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +123,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +146,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv64i1_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +169,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +192,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +215,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +238,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +261,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +284,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv32i1_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +307,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +330,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +353,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +376,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +399,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv16i1_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +422,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v9, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv1i1_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i64.nxv1i64( %0, %1, @@ -387,10 +445,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v10, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv2i1_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i64.nxv2i64( %0, %1, @@ -407,10 +468,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v12, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv4i1_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i64.nxv4i64( %0, %1, @@ -427,10 +491,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmsbc.vvm v25, v8, v16, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vvm_nxv8i1_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i64.nxv8i64( %0, %1, @@ -447,10 +514,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i8.i8( %0, i8 %1, @@ -467,10 +537,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i8.i8( %0, i8 %1, @@ -487,10 +560,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i8.i8( %0, i8 %1, @@ -507,10 +583,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i8.i8( %0, i8 %1, @@ -527,10 +606,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i8.i8( %0, i8 %1, @@ -547,10 +629,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i8.i8( %0, i8 %1, @@ -567,10 +652,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv64i1_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv64i8.i8( %0, i8 %1, @@ -587,10 +675,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i16.i16( %0, i16 %1, @@ -607,10 +698,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i16.i16( %0, i16 %1, @@ -627,10 +721,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i16.i16( %0, i16 %1, @@ -647,10 +744,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i16.i16( %0, i16 %1, @@ -667,10 +767,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i16.i16( %0, i16 %1, @@ -687,10 +790,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv32i1_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv32i16.i16( %0, i16 %1, @@ -707,10 +813,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i32.i32( %0, i32 %1, @@ -727,10 +836,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i32.i32( %0, i32 %1, @@ -747,10 +859,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i32.i32( %0, i32 %1, @@ -767,10 +882,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i32.i32( %0, i32 %1, @@ -787,10 +905,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv16i1_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv16i32.i32( %0, i32 %1, @@ -807,10 +928,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv1i1_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv1i64.i64( %0, i64 %1, @@ -827,10 +951,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv2i1_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv2i64.i64( %0, i64 %1, @@ -847,10 +974,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv4i1_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv4i64.i64( %0, i64 %1, @@ -867,10 +997,13 @@ i64); define @intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmsbc.vxm v25, v8, a0, v0 +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsbc.borrow.in_vxm_nxv8i1_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vmsbc.borrow.in.nxv8i64.i64( %0, i64 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll @@ -30,8 +30,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -72,8 +72,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -114,8 +114,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -156,8 +156,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -198,8 +198,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -240,8 +240,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -282,8 +282,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll @@ -30,8 +30,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -72,8 +72,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -114,8 +114,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -156,8 +156,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -198,8 +198,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -240,8 +240,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -282,8 +282,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsbf.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsbf.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmseq.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmseq_vv_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmseq_vv_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmseq_vv_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmseq_vv_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmseq_vv_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmseq_vv_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmseq_vv_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmseq_vv_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmseq_vv_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i32); define @intrinsic_vmseq_vv_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i32); define @intrinsic_vmseq_vv_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i32); define @intrinsic_vmseq_vv_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i32); define @intrinsic_vmseq_vv_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i32); define @intrinsic_vmseq_vv_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i32); define @intrinsic_vmseq_vv_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i32); define @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i32); define @intrinsic_vmseq_vx_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i8.i8( %0, i8 %1, @@ -686,10 +809,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i8.i8( %0, %1, @@ -706,10 +834,12 @@ i32); define @intrinsic_vmseq_vx_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i8.i8( %0, i8 %1, @@ -726,10 +856,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i8.i8( %0, %1, @@ -746,10 +881,12 @@ i32); define @intrinsic_vmseq_vx_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i8.i8( %0, i8 %1, @@ -766,10 +903,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i8.i8( %0, %1, @@ -786,10 +928,12 @@ i32); define @intrinsic_vmseq_vx_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i8.i8( %0, i8 %1, @@ -806,10 +950,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i8.i8( %0, %1, @@ -826,10 +975,12 @@ i32); define @intrinsic_vmseq_vx_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv16i8.i8( %0, i8 %1, @@ -846,10 +997,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv16i8.i8( %0, %1, @@ -866,10 +1022,12 @@ i32); define @intrinsic_vmseq_vx_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv32i8.i8( %0, i8 %1, @@ -886,10 +1044,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv32i8.i8( %0, %1, @@ -906,10 +1069,12 @@ i32); define @intrinsic_vmseq_vx_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i16.i16( %0, i16 %1, @@ -926,10 +1091,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i16.i16( %0, %1, @@ -946,10 +1116,12 @@ i32); define @intrinsic_vmseq_vx_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i16.i16( %0, i16 %1, @@ -966,10 +1138,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i16.i16( %0, %1, @@ -986,10 +1163,12 @@ i32); define @intrinsic_vmseq_vx_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i16.i16( %0, i16 %1, @@ -1006,10 +1185,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i16.i16( %0, %1, @@ -1026,10 +1210,12 @@ i32); define @intrinsic_vmseq_vx_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i16.i16( %0, i16 %1, @@ -1046,10 +1232,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i16.i16( %0, %1, @@ -1066,10 +1257,12 @@ i32); define @intrinsic_vmseq_vx_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv16i16.i16( %0, i16 %1, @@ -1086,10 +1279,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv16i16.i16( %0, %1, @@ -1106,10 +1304,12 @@ i32); define @intrinsic_vmseq_vx_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i32.i32( %0, i32 %1, @@ -1126,10 +1326,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i32.i32( %0, %1, @@ -1146,10 +1351,12 @@ i32); define @intrinsic_vmseq_vx_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i32.i32( %0, i32 %1, @@ -1166,10 +1373,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i32.i32( %0, %1, @@ -1186,10 +1398,12 @@ i32); define @intrinsic_vmseq_vx_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i32.i32( %0, i32 %1, @@ -1206,10 +1420,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i32.i32( %0, %1, @@ -1226,10 +1445,12 @@ i32); define @intrinsic_vmseq_vx_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1467,15 @@ i32); define @intrinsic_vmseq_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i32.i32( %0, %1, @@ -1261,10 +1487,12 @@ } define @intrinsic_vmseq_vi_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv1i8.i8( %0, i8 9, @@ -1274,10 +1502,15 @@ } define @intrinsic_vmseq_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i8.i8( %0, %1, @@ -1289,10 +1522,12 @@ } define @intrinsic_vmseq_vi_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv2i8.i8( %0, i8 9, @@ -1302,10 +1537,15 @@ } define @intrinsic_vmseq_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i8.i8( %0, %1, @@ -1317,10 +1557,12 @@ } define @intrinsic_vmseq_vi_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv4i8.i8( %0, i8 9, @@ -1330,10 +1572,15 @@ } define @intrinsic_vmseq_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i8.i8( %0, %1, @@ -1345,10 +1592,12 @@ } define @intrinsic_vmseq_vi_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv8i8.i8( %0, i8 9, @@ -1358,10 +1607,15 @@ } define @intrinsic_vmseq_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i8.i8( %0, %1, @@ -1373,10 +1627,12 @@ } define @intrinsic_vmseq_vi_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv16i8.i8( %0, i8 9, @@ -1386,10 +1642,15 @@ } define @intrinsic_vmseq_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv16i8.i8( %0, %1, @@ -1401,10 +1662,12 @@ } define @intrinsic_vmseq_vi_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv32i8.i8( %0, i8 9, @@ -1414,10 +1677,15 @@ } define @intrinsic_vmseq_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv32i8.i8( %0, %1, @@ -1429,10 +1697,12 @@ } define @intrinsic_vmseq_vi_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv1i16.i16( %0, i16 9, @@ -1442,10 +1712,15 @@ } define @intrinsic_vmseq_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i16.i16( %0, %1, @@ -1457,10 +1732,12 @@ } define @intrinsic_vmseq_vi_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv2i16.i16( %0, i16 9, @@ -1470,10 +1747,15 @@ } define @intrinsic_vmseq_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i16.i16( %0, %1, @@ -1485,10 +1767,12 @@ } define @intrinsic_vmseq_vi_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv4i16.i16( %0, i16 9, @@ -1498,10 +1782,15 @@ } define @intrinsic_vmseq_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i16.i16( %0, %1, @@ -1513,10 +1802,12 @@ } define @intrinsic_vmseq_vi_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv8i16.i16( %0, i16 9, @@ -1526,10 +1817,15 @@ } define @intrinsic_vmseq_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i16.i16( %0, %1, @@ -1541,10 +1837,12 @@ } define @intrinsic_vmseq_vi_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv16i16.i16( %0, i16 9, @@ -1554,10 +1852,15 @@ } define @intrinsic_vmseq_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv16i16.i16( %0, %1, @@ -1569,10 +1872,12 @@ } define @intrinsic_vmseq_vi_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv1i32.i32( %0, i32 9, @@ -1582,10 +1887,15 @@ } define @intrinsic_vmseq_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i32.i32( %0, %1, @@ -1597,10 +1907,12 @@ } define @intrinsic_vmseq_vi_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv2i32.i32( %0, i32 9, @@ -1610,10 +1922,15 @@ } define @intrinsic_vmseq_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i32.i32( %0, %1, @@ -1625,10 +1942,12 @@ } define @intrinsic_vmseq_vi_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv4i32.i32( %0, i32 9, @@ -1638,10 +1957,15 @@ } define @intrinsic_vmseq_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i32.i32( %0, %1, @@ -1653,10 +1977,12 @@ } define @intrinsic_vmseq_vi_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv8i32.i32( %0, i32 9, @@ -1666,10 +1992,15 @@ } define @intrinsic_vmseq_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmseq.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmseq_vv_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmseq_vv_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmseq_vv_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmseq_vv_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmseq_vv_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmseq_vv_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmseq_vv_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmseq_vv_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmseq_vv_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmseq_vv_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmseq_vv_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmseq_vv_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i64); define @intrinsic_vmseq_vv_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i64); define @intrinsic_vmseq_vv_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i64); define @intrinsic_vmseq_vv_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i64); define @intrinsic_vmseq_vv_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i64( %0, %1, @@ -686,10 +809,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmseq.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv1i64( %1, %2, @@ -710,10 +839,12 @@ i64); define @intrinsic_vmseq_vv_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i64( %0, %1, @@ -730,10 +861,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmseq.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv2i64( %1, %2, @@ -754,10 +891,12 @@ i64); define @intrinsic_vmseq_vv_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i64( %0, %1, @@ -774,10 +913,16 @@ i64); define @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmseq.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmseq.nxv4i64( %1, %2, @@ -798,10 +943,12 @@ i64); define @intrinsic_vmseq_vx_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i8.i8( %0, i8 %1, @@ -818,10 +965,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i8.i8( %0, %1, @@ -838,10 +990,12 @@ i64); define @intrinsic_vmseq_vx_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i8.i8( %0, i8 %1, @@ -858,10 +1012,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i8.i8( %0, %1, @@ -878,10 +1037,12 @@ i64); define @intrinsic_vmseq_vx_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i8.i8( %0, i8 %1, @@ -898,10 +1059,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i8.i8( %0, %1, @@ -918,10 +1084,12 @@ i64); define @intrinsic_vmseq_vx_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i8.i8( %0, i8 %1, @@ -938,10 +1106,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i8.i8( %0, %1, @@ -958,10 +1131,12 @@ i64); define @intrinsic_vmseq_vx_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv16i8.i8( %0, i8 %1, @@ -978,10 +1153,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv16i8.i8( %0, %1, @@ -998,10 +1178,12 @@ i64); define @intrinsic_vmseq_vx_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv32i8.i8( %0, i8 %1, @@ -1018,10 +1200,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv32i8.i8( %0, %1, @@ -1038,10 +1225,12 @@ i64); define @intrinsic_vmseq_vx_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i16.i16( %0, i16 %1, @@ -1058,10 +1247,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i16.i16( %0, %1, @@ -1078,10 +1272,12 @@ i64); define @intrinsic_vmseq_vx_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i16.i16( %0, i16 %1, @@ -1098,10 +1294,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i16.i16( %0, %1, @@ -1118,10 +1319,12 @@ i64); define @intrinsic_vmseq_vx_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i16.i16( %0, i16 %1, @@ -1138,10 +1341,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i16.i16( %0, %1, @@ -1158,10 +1366,12 @@ i64); define @intrinsic_vmseq_vx_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i16.i16( %0, i16 %1, @@ -1178,10 +1388,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i16.i16( %0, %1, @@ -1198,10 +1413,12 @@ i64); define @intrinsic_vmseq_vx_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv16i16.i16( %0, i16 %1, @@ -1218,10 +1435,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv16i16.i16( %0, %1, @@ -1238,10 +1460,12 @@ i64); define @intrinsic_vmseq_vx_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i32.i32( %0, i32 %1, @@ -1258,10 +1482,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i32.i32( %0, %1, @@ -1278,10 +1507,12 @@ i64); define @intrinsic_vmseq_vx_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i32.i32( %0, i32 %1, @@ -1298,10 +1529,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i32.i32( %0, %1, @@ -1318,10 +1554,12 @@ i64); define @intrinsic_vmseq_vx_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i32.i32( %0, i32 %1, @@ -1338,10 +1576,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i32.i32( %0, %1, @@ -1358,10 +1601,12 @@ i64); define @intrinsic_vmseq_vx_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv8i32.i32( %0, i32 %1, @@ -1378,10 +1623,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i32.i32( %0, %1, @@ -1398,10 +1648,12 @@ i64); define @intrinsic_vmseq_vx_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv1i64.i64( %0, i64 %1, @@ -1418,10 +1670,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i64.i64( %0, %1, @@ -1438,10 +1695,12 @@ i64); define @intrinsic_vmseq_vx_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv2i64.i64( %0, i64 %1, @@ -1458,10 +1717,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i64.i64( %0, %1, @@ -1478,10 +1742,12 @@ i64); define @intrinsic_vmseq_vx_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmseq.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmseq.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1764,15 @@ i64); define @intrinsic_vmseq_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i64.i64( %0, %1, @@ -1513,10 +1784,12 @@ } define @intrinsic_vmseq_vi_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv1i8.i8( %0, i8 9, @@ -1526,10 +1799,15 @@ } define @intrinsic_vmseq_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i8.i8( %0, %1, @@ -1541,10 +1819,12 @@ } define @intrinsic_vmseq_vi_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv2i8.i8( %0, i8 9, @@ -1554,10 +1834,15 @@ } define @intrinsic_vmseq_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i8.i8( %0, %1, @@ -1569,10 +1854,12 @@ } define @intrinsic_vmseq_vi_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv4i8.i8( %0, i8 9, @@ -1582,10 +1869,15 @@ } define @intrinsic_vmseq_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i8.i8( %0, %1, @@ -1597,10 +1889,12 @@ } define @intrinsic_vmseq_vi_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv8i8.i8( %0, i8 9, @@ -1610,10 +1904,15 @@ } define @intrinsic_vmseq_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i8.i8( %0, %1, @@ -1625,10 +1924,12 @@ } define @intrinsic_vmseq_vi_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv16i8.i8( %0, i8 9, @@ -1638,10 +1939,15 @@ } define @intrinsic_vmseq_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv16i8.i8( %0, %1, @@ -1653,10 +1959,12 @@ } define @intrinsic_vmseq_vi_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv32i8.i8( %0, i8 9, @@ -1666,10 +1974,15 @@ } define @intrinsic_vmseq_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv32i8.i8( %0, %1, @@ -1681,10 +1994,12 @@ } define @intrinsic_vmseq_vi_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv1i16.i16( %0, i16 9, @@ -1694,10 +2009,15 @@ } define @intrinsic_vmseq_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i16.i16( %0, %1, @@ -1709,10 +2029,12 @@ } define @intrinsic_vmseq_vi_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv2i16.i16( %0, i16 9, @@ -1722,10 +2044,15 @@ } define @intrinsic_vmseq_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i16.i16( %0, %1, @@ -1737,10 +2064,12 @@ } define @intrinsic_vmseq_vi_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv4i16.i16( %0, i16 9, @@ -1750,10 +2079,15 @@ } define @intrinsic_vmseq_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i16.i16( %0, %1, @@ -1765,10 +2099,12 @@ } define @intrinsic_vmseq_vi_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv8i16.i16( %0, i16 9, @@ -1778,10 +2114,15 @@ } define @intrinsic_vmseq_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i16.i16( %0, %1, @@ -1793,10 +2134,12 @@ } define @intrinsic_vmseq_vi_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv16i16.i16( %0, i16 9, @@ -1806,10 +2149,15 @@ } define @intrinsic_vmseq_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv16i16.i16( %0, %1, @@ -1821,10 +2169,12 @@ } define @intrinsic_vmseq_vi_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv1i32.i32( %0, i32 9, @@ -1834,10 +2184,15 @@ } define @intrinsic_vmseq_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i32.i32( %0, %1, @@ -1849,10 +2204,12 @@ } define @intrinsic_vmseq_vi_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv2i32.i32( %0, i32 9, @@ -1862,10 +2219,15 @@ } define @intrinsic_vmseq_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i32.i32( %0, %1, @@ -1877,10 +2239,12 @@ } define @intrinsic_vmseq_vi_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv4i32.i32( %0, i32 9, @@ -1890,10 +2254,15 @@ } define @intrinsic_vmseq_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i32.i32( %0, %1, @@ -1905,10 +2274,12 @@ } define @intrinsic_vmseq_vi_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv8i32.i32( %0, i32 9, @@ -1918,10 +2289,15 @@ } define @intrinsic_vmseq_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv8i32.i32( %0, %1, @@ -1933,10 +2309,12 @@ } define @intrinsic_vmseq_vi_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv1i64.i64( %0, i64 9, @@ -1946,10 +2324,15 @@ } define @intrinsic_vmseq_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv1i64.i64( %0, %1, @@ -1961,10 +2344,12 @@ } define @intrinsic_vmseq_vi_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv2i64.i64( %0, i64 9, @@ -1974,10 +2359,15 @@ } define @intrinsic_vmseq_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv2i64.i64( %0, %1, @@ -1989,10 +2379,12 @@ } define @intrinsic_vmseq_vi_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmseq.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmseq.nxv4i64.i64( %0, i64 9, @@ -2002,10 +2394,15 @@ } define @intrinsic_vmseq_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmseq.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmseq.mask.nxv4i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmset-rv32.ll @@ -1,13 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmset.nxv1i1( i32); define @intrinsic_vmset_m_pseudo_nxv1i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv1i1( i32 %0) @@ -18,10 +21,12 @@ i32); define @intrinsic_vmset_m_pseudo_nxv2i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv2i1( i32 %0) @@ -32,10 +37,12 @@ i32); define @intrinsic_vmset_m_pseudo_nxv4i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv4i1( i32 %0) @@ -46,10 +53,12 @@ i32); define @intrinsic_vmset_m_pseudo_nxv8i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv8i1( i32 %0) @@ -60,10 +69,12 @@ i32); define @intrinsic_vmset_m_pseudo_nxv16i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv16i1( i32 %0) @@ -74,10 +85,12 @@ i32); define @intrinsic_vmset_m_pseudo_nxv32i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv32i1( i32 %0) @@ -88,10 +101,12 @@ i32); define @intrinsic_vmset_m_pseudo_nxv64i1(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv64i1( i32 %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmset-rv64.ll @@ -1,13 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+experimental-zfh -verify-machineinstrs \ ; RUN: < %s | FileCheck %s declare @llvm.riscv.vmset.nxv1i1( i64); define @intrinsic_vmset_m_pseudo_nxv1i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv1i1( i64 %0) @@ -18,10 +21,12 @@ i64); define @intrinsic_vmset_m_pseudo_nxv2i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv2i1( i64 %0) @@ -32,10 +37,12 @@ i64); define @intrinsic_vmset_m_pseudo_nxv4i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv4i1( i64 %0) @@ -46,10 +53,12 @@ i64); define @intrinsic_vmset_m_pseudo_nxv8i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv8i1( i64 %0) @@ -60,10 +69,12 @@ i64); define @intrinsic_vmset_m_pseudo_nxv16i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv16i1( i64 %0) @@ -74,10 +85,12 @@ i64); define @intrinsic_vmset_m_pseudo_nxv32i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv32i1( i64 %0) @@ -88,10 +101,12 @@ i64); define @intrinsic_vmset_m_pseudo_nxv64i1(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmset.m v0 +; CHECK-NEXT: ret entry: -; CHECK-LABEL: intrinsic_vmset_m_pseudo_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8 -; CHECK: vmset.m {{v[0-9]+}} %a = call @llvm.riscv.vmset.nxv64i1( i64 %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsgt.nxv1i8.i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmsgt_vx_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv1i8.i8( %0, i8 %1, @@ -26,10 +29,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i8.i8( %0, %1, @@ -46,10 +54,12 @@ i32); define @intrinsic_vmsgt_vx_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv2i8.i8( %0, i8 %1, @@ -66,10 +76,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i8.i8( %0, %1, @@ -86,10 +101,12 @@ i32); define @intrinsic_vmsgt_vx_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv4i8.i8( %0, i8 %1, @@ -106,10 +123,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i8.i8( %0, %1, @@ -126,10 +148,12 @@ i32); define @intrinsic_vmsgt_vx_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv8i8.i8( %0, i8 %1, @@ -146,10 +170,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i8.i8( %0, %1, @@ -166,10 +195,12 @@ i32); define @intrinsic_vmsgt_vx_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv16i8.i8( %0, i8 %1, @@ -186,10 +217,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv16i8.i8( %0, %1, @@ -206,10 +242,12 @@ i32); define @intrinsic_vmsgt_vx_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv32i8.i8( %0, i8 %1, @@ -226,10 +264,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv32i8.i8( %0, %1, @@ -246,10 +289,12 @@ i32); define @intrinsic_vmsgt_vx_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv1i16.i16( %0, i16 %1, @@ -266,10 +311,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i16.i16( %0, %1, @@ -286,10 +336,12 @@ i32); define @intrinsic_vmsgt_vx_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv2i16.i16( %0, i16 %1, @@ -306,10 +358,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i16.i16( %0, %1, @@ -326,10 +383,12 @@ i32); define @intrinsic_vmsgt_vx_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv4i16.i16( %0, i16 %1, @@ -346,10 +405,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i16.i16( %0, %1, @@ -366,10 +430,12 @@ i32); define @intrinsic_vmsgt_vx_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv8i16.i16( %0, i16 %1, @@ -386,10 +452,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i16.i16( %0, %1, @@ -406,10 +477,12 @@ i32); define @intrinsic_vmsgt_vx_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv16i16.i16( %0, i16 %1, @@ -426,10 +499,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv16i16.i16( %0, %1, @@ -446,10 +524,12 @@ i32); define @intrinsic_vmsgt_vx_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv1i32.i32( %0, i32 %1, @@ -466,10 +546,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i32.i32( %0, %1, @@ -486,10 +571,12 @@ i32); define @intrinsic_vmsgt_vx_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv2i32.i32( %0, i32 %1, @@ -506,10 +593,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i32.i32( %0, %1, @@ -526,10 +618,12 @@ i32); define @intrinsic_vmsgt_vx_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv4i32.i32( %0, i32 %1, @@ -546,10 +640,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i32.i32( %0, %1, @@ -566,10 +665,12 @@ i32); define @intrinsic_vmsgt_vx_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv8i32.i32( %0, i32 %1, @@ -586,10 +687,15 @@ i32); define @intrinsic_vmsgt_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i32.i32( %0, %1, @@ -601,10 +707,12 @@ } define @intrinsic_vmsgt_vi_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv1i8.i8( %0, i8 9, @@ -614,10 +722,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i8.i8( %0, %1, @@ -629,10 +742,12 @@ } define @intrinsic_vmsgt_vi_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv2i8.i8( %0, i8 9, @@ -642,10 +757,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i8.i8( %0, %1, @@ -657,10 +777,12 @@ } define @intrinsic_vmsgt_vi_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv4i8.i8( %0, i8 9, @@ -670,10 +792,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i8.i8( %0, %1, @@ -685,10 +812,12 @@ } define @intrinsic_vmsgt_vi_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv8i8.i8( %0, i8 9, @@ -698,10 +827,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i8.i8( %0, %1, @@ -713,10 +847,12 @@ } define @intrinsic_vmsgt_vi_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv16i8.i8( %0, i8 9, @@ -726,10 +862,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv16i8.i8( %0, %1, @@ -741,10 +882,12 @@ } define @intrinsic_vmsgt_vi_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv32i8.i8( %0, i8 9, @@ -754,10 +897,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv32i8.i8( %0, %1, @@ -769,10 +917,12 @@ } define @intrinsic_vmsgt_vi_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv1i16.i16( %0, i16 9, @@ -782,10 +932,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i16.i16( %0, %1, @@ -797,10 +952,12 @@ } define @intrinsic_vmsgt_vi_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv2i16.i16( %0, i16 9, @@ -810,10 +967,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i16.i16( %0, %1, @@ -825,10 +987,12 @@ } define @intrinsic_vmsgt_vi_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv4i16.i16( %0, i16 9, @@ -838,10 +1002,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i16.i16( %0, %1, @@ -853,10 +1022,12 @@ } define @intrinsic_vmsgt_vi_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv8i16.i16( %0, i16 9, @@ -866,10 +1037,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i16.i16( %0, %1, @@ -881,10 +1057,12 @@ } define @intrinsic_vmsgt_vi_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv16i16.i16( %0, i16 9, @@ -894,10 +1072,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv16i16.i16( %0, %1, @@ -909,10 +1092,12 @@ } define @intrinsic_vmsgt_vi_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv1i32.i32( %0, i32 9, @@ -922,10 +1107,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i32.i32( %0, %1, @@ -937,10 +1127,12 @@ } define @intrinsic_vmsgt_vi_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv2i32.i32( %0, i32 9, @@ -950,10 +1142,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i32.i32( %0, %1, @@ -965,10 +1162,12 @@ } define @intrinsic_vmsgt_vi_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv4i32.i32( %0, i32 9, @@ -978,10 +1177,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i32.i32( %0, %1, @@ -993,10 +1197,12 @@ } define @intrinsic_vmsgt_vi_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv8i32.i32( %0, i32 9, @@ -1006,10 +1212,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsgt.nxv1i8.i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmsgt_vx_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv1i8.i8( %0, i8 %1, @@ -26,10 +29,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i8.i8( %0, %1, @@ -46,10 +54,12 @@ i64); define @intrinsic_vmsgt_vx_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv2i8.i8( %0, i8 %1, @@ -66,10 +76,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i8.i8( %0, %1, @@ -86,10 +101,12 @@ i64); define @intrinsic_vmsgt_vx_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv4i8.i8( %0, i8 %1, @@ -106,10 +123,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i8.i8( %0, %1, @@ -126,10 +148,12 @@ i64); define @intrinsic_vmsgt_vx_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv8i8.i8( %0, i8 %1, @@ -146,10 +170,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i8.i8( %0, %1, @@ -166,10 +195,12 @@ i64); define @intrinsic_vmsgt_vx_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv16i8.i8( %0, i8 %1, @@ -186,10 +217,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv16i8.i8( %0, %1, @@ -206,10 +242,12 @@ i64); define @intrinsic_vmsgt_vx_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv32i8.i8( %0, i8 %1, @@ -226,10 +264,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv32i8.i8( %0, %1, @@ -246,10 +289,12 @@ i64); define @intrinsic_vmsgt_vx_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv1i16.i16( %0, i16 %1, @@ -266,10 +311,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i16.i16( %0, %1, @@ -286,10 +336,12 @@ i64); define @intrinsic_vmsgt_vx_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv2i16.i16( %0, i16 %1, @@ -306,10 +358,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i16.i16( %0, %1, @@ -326,10 +383,12 @@ i64); define @intrinsic_vmsgt_vx_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv4i16.i16( %0, i16 %1, @@ -346,10 +405,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i16.i16( %0, %1, @@ -366,10 +430,12 @@ i64); define @intrinsic_vmsgt_vx_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv8i16.i16( %0, i16 %1, @@ -386,10 +452,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i16.i16( %0, %1, @@ -406,10 +477,12 @@ i64); define @intrinsic_vmsgt_vx_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv16i16.i16( %0, i16 %1, @@ -426,10 +499,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv16i16.i16( %0, %1, @@ -446,10 +524,12 @@ i64); define @intrinsic_vmsgt_vx_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv1i32.i32( %0, i32 %1, @@ -466,10 +546,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i32.i32( %0, %1, @@ -486,10 +571,12 @@ i64); define @intrinsic_vmsgt_vx_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv2i32.i32( %0, i32 %1, @@ -506,10 +593,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i32.i32( %0, %1, @@ -526,10 +618,12 @@ i64); define @intrinsic_vmsgt_vx_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv4i32.i32( %0, i32 %1, @@ -546,10 +640,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i32.i32( %0, %1, @@ -566,10 +665,12 @@ i64); define @intrinsic_vmsgt_vx_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv8i32.i32( %0, i32 %1, @@ -586,10 +687,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i32.i32( %0, %1, @@ -606,10 +712,12 @@ i64); define @intrinsic_vmsgt_vx_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv1i64.i64( %0, i64 %1, @@ -626,10 +734,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i64.i64( %0, %1, @@ -646,10 +759,12 @@ i64); define @intrinsic_vmsgt_vx_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv2i64.i64( %0, i64 %1, @@ -666,10 +781,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i64.i64( %0, %1, @@ -686,10 +806,12 @@ i64); define @intrinsic_vmsgt_vx_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmsgt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgt.nxv4i64.i64( %0, i64 %1, @@ -706,10 +828,15 @@ i64); define @intrinsic_vmsgt_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i64.i64( %0, %1, @@ -721,10 +848,12 @@ } define @intrinsic_vmsgt_vi_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv1i8.i8( %0, i8 9, @@ -734,10 +863,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i8.i8( %0, %1, @@ -749,10 +883,12 @@ } define @intrinsic_vmsgt_vi_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv2i8.i8( %0, i8 9, @@ -762,10 +898,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i8.i8( %0, %1, @@ -777,10 +918,12 @@ } define @intrinsic_vmsgt_vi_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv4i8.i8( %0, i8 9, @@ -790,10 +933,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i8.i8( %0, %1, @@ -805,10 +953,12 @@ } define @intrinsic_vmsgt_vi_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv8i8.i8( %0, i8 9, @@ -818,10 +968,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i8.i8( %0, %1, @@ -833,10 +988,12 @@ } define @intrinsic_vmsgt_vi_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv16i8.i8( %0, i8 9, @@ -846,10 +1003,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv16i8.i8( %0, %1, @@ -861,10 +1023,12 @@ } define @intrinsic_vmsgt_vi_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv32i8.i8( %0, i8 9, @@ -874,10 +1038,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv32i8.i8( %0, %1, @@ -889,10 +1058,12 @@ } define @intrinsic_vmsgt_vi_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv1i16.i16( %0, i16 9, @@ -902,10 +1073,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i16.i16( %0, %1, @@ -917,10 +1093,12 @@ } define @intrinsic_vmsgt_vi_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv2i16.i16( %0, i16 9, @@ -930,10 +1108,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i16.i16( %0, %1, @@ -945,10 +1128,12 @@ } define @intrinsic_vmsgt_vi_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv4i16.i16( %0, i16 9, @@ -958,10 +1143,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i16.i16( %0, %1, @@ -973,10 +1163,12 @@ } define @intrinsic_vmsgt_vi_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv8i16.i16( %0, i16 9, @@ -986,10 +1178,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i16.i16( %0, %1, @@ -1001,10 +1198,12 @@ } define @intrinsic_vmsgt_vi_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv16i16.i16( %0, i16 9, @@ -1014,10 +1213,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv16i16.i16( %0, %1, @@ -1029,10 +1233,12 @@ } define @intrinsic_vmsgt_vi_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv1i32.i32( %0, i32 9, @@ -1042,10 +1248,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i32.i32( %0, %1, @@ -1057,10 +1268,12 @@ } define @intrinsic_vmsgt_vi_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv2i32.i32( %0, i32 9, @@ -1070,10 +1283,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i32.i32( %0, %1, @@ -1085,10 +1303,12 @@ } define @intrinsic_vmsgt_vi_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv4i32.i32( %0, i32 9, @@ -1098,10 +1318,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i32.i32( %0, %1, @@ -1113,10 +1338,12 @@ } define @intrinsic_vmsgt_vi_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv8i32.i32( %0, i32 9, @@ -1126,10 +1353,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv8i32.i32( %0, %1, @@ -1141,10 +1373,12 @@ } define @intrinsic_vmsgt_vi_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv1i64.i64( %0, i64 9, @@ -1154,10 +1388,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv1i64.i64( %0, %1, @@ -1169,10 +1408,12 @@ } define @intrinsic_vmsgt_vi_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv2i64.i64( %0, i64 9, @@ -1182,10 +1423,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv2i64.i64( %0, %1, @@ -1197,10 +1443,12 @@ } define @intrinsic_vmsgt_vi_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsgt.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgt.nxv4i64.i64( %0, i64 9, @@ -1210,10 +1458,15 @@ } define @intrinsic_vmsgt_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgt.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgt.mask.nxv4i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsgtu.nxv1i8.i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv1i8.i8( %0, i8 %1, @@ -26,10 +29,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %0, %1, @@ -46,10 +54,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv2i8.i8( %0, i8 %1, @@ -66,10 +76,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %0, %1, @@ -86,10 +101,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv4i8.i8( %0, i8 %1, @@ -106,10 +123,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %0, %1, @@ -126,10 +148,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv8i8.i8( %0, i8 %1, @@ -146,10 +170,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %0, %1, @@ -166,10 +195,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv16i8.i8( %0, i8 %1, @@ -186,10 +217,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %0, %1, @@ -206,10 +242,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv32i8.i8( %0, i8 %1, @@ -226,10 +264,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %0, %1, @@ -246,10 +289,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv1i16.i16( %0, i16 %1, @@ -266,10 +311,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %0, %1, @@ -286,10 +336,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv2i16.i16( %0, i16 %1, @@ -306,10 +358,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %0, %1, @@ -326,10 +383,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv4i16.i16( %0, i16 %1, @@ -346,10 +405,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %0, %1, @@ -366,10 +430,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv8i16.i16( %0, i16 %1, @@ -386,10 +452,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %0, %1, @@ -406,10 +477,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv16i16.i16( %0, i16 %1, @@ -426,10 +499,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %0, %1, @@ -446,10 +524,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv1i32.i32( %0, i32 %1, @@ -466,10 +546,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %0, %1, @@ -486,10 +571,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv2i32.i32( %0, i32 %1, @@ -506,10 +593,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %0, %1, @@ -526,10 +618,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv4i32.i32( %0, i32 %1, @@ -546,10 +640,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %0, %1, @@ -566,10 +665,12 @@ i32); define @intrinsic_vmsgtu_vx_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv8i32.i32( %0, i32 %1, @@ -586,10 +687,15 @@ i32); define @intrinsic_vmsgtu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %0, %1, @@ -601,10 +707,12 @@ } define @intrinsic_vmsgtu_vi_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv1i8.i8( %0, i8 9, @@ -614,10 +722,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %0, %1, @@ -629,10 +742,12 @@ } define @intrinsic_vmsgtu_vi_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv2i8.i8( %0, i8 9, @@ -642,10 +757,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %0, %1, @@ -657,10 +777,12 @@ } define @intrinsic_vmsgtu_vi_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv4i8.i8( %0, i8 9, @@ -670,10 +792,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %0, %1, @@ -685,10 +812,12 @@ } define @intrinsic_vmsgtu_vi_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv8i8.i8( %0, i8 9, @@ -698,10 +827,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %0, %1, @@ -713,10 +847,12 @@ } define @intrinsic_vmsgtu_vi_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv16i8.i8( %0, i8 9, @@ -726,10 +862,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %0, %1, @@ -741,10 +882,12 @@ } define @intrinsic_vmsgtu_vi_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv32i8.i8( %0, i8 9, @@ -754,10 +897,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %0, %1, @@ -769,10 +917,12 @@ } define @intrinsic_vmsgtu_vi_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv1i16.i16( %0, i16 9, @@ -782,10 +932,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %0, %1, @@ -797,10 +952,12 @@ } define @intrinsic_vmsgtu_vi_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv2i16.i16( %0, i16 9, @@ -810,10 +967,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %0, %1, @@ -825,10 +987,12 @@ } define @intrinsic_vmsgtu_vi_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv4i16.i16( %0, i16 9, @@ -838,10 +1002,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %0, %1, @@ -853,10 +1022,12 @@ } define @intrinsic_vmsgtu_vi_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv8i16.i16( %0, i16 9, @@ -866,10 +1037,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %0, %1, @@ -881,10 +1057,12 @@ } define @intrinsic_vmsgtu_vi_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv16i16.i16( %0, i16 9, @@ -894,10 +1072,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %0, %1, @@ -909,10 +1092,12 @@ } define @intrinsic_vmsgtu_vi_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv1i32.i32( %0, i32 9, @@ -922,10 +1107,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %0, %1, @@ -937,10 +1127,12 @@ } define @intrinsic_vmsgtu_vi_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv2i32.i32( %0, i32 9, @@ -950,10 +1142,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %0, %1, @@ -965,10 +1162,12 @@ } define @intrinsic_vmsgtu_vi_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv4i32.i32( %0, i32 9, @@ -978,10 +1177,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %0, %1, @@ -993,10 +1197,12 @@ } define @intrinsic_vmsgtu_vi_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv8i32.i32( %0, i32 9, @@ -1006,10 +1212,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsgtu.nxv1i8.i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv1i8.i8( %0, i8 %1, @@ -26,10 +29,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %0, %1, @@ -46,10 +54,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv2i8.i8( %0, i8 %1, @@ -66,10 +76,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %0, %1, @@ -86,10 +101,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv4i8.i8( %0, i8 %1, @@ -106,10 +123,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %0, %1, @@ -126,10 +148,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv8i8.i8( %0, i8 %1, @@ -146,10 +170,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %0, %1, @@ -166,10 +195,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv16i8.i8( %0, i8 %1, @@ -186,10 +217,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %0, %1, @@ -206,10 +242,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv32i8.i8( %0, i8 %1, @@ -226,10 +264,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %0, %1, @@ -246,10 +289,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv1i16.i16( %0, i16 %1, @@ -266,10 +311,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %0, %1, @@ -286,10 +336,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv2i16.i16( %0, i16 %1, @@ -306,10 +358,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %0, %1, @@ -326,10 +383,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv4i16.i16( %0, i16 %1, @@ -346,10 +405,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %0, %1, @@ -366,10 +430,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv8i16.i16( %0, i16 %1, @@ -386,10 +452,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %0, %1, @@ -406,10 +477,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv16i16.i16( %0, i16 %1, @@ -426,10 +499,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %0, %1, @@ -446,10 +524,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv1i32.i32( %0, i32 %1, @@ -466,10 +546,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %0, %1, @@ -486,10 +571,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv2i32.i32( %0, i32 %1, @@ -506,10 +593,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %0, %1, @@ -526,10 +618,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv4i32.i32( %0, i32 %1, @@ -546,10 +640,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %0, %1, @@ -566,10 +665,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv8i32.i32( %0, i32 %1, @@ -586,10 +687,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %0, %1, @@ -606,10 +712,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv1i64.i64( %0, i64 %1, @@ -626,10 +734,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %0, %1, @@ -646,10 +759,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv2i64.i64( %0, i64 %1, @@ -666,10 +781,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %0, %1, @@ -686,10 +806,12 @@ i64); define @intrinsic_vmsgtu_vx_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmsgtu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsgtu.nxv4i64.i64( %0, i64 %1, @@ -706,10 +828,15 @@ i64); define @intrinsic_vmsgtu_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %0, %1, @@ -721,10 +848,12 @@ } define @intrinsic_vmsgtu_vi_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv1i8.i8( %0, i8 9, @@ -734,10 +863,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %0, %1, @@ -749,10 +883,12 @@ } define @intrinsic_vmsgtu_vi_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv2i8.i8( %0, i8 9, @@ -762,10 +898,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %0, %1, @@ -777,10 +918,12 @@ } define @intrinsic_vmsgtu_vi_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv4i8.i8( %0, i8 9, @@ -790,10 +933,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %0, %1, @@ -805,10 +953,12 @@ } define @intrinsic_vmsgtu_vi_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv8i8.i8( %0, i8 9, @@ -818,10 +968,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %0, %1, @@ -833,10 +988,12 @@ } define @intrinsic_vmsgtu_vi_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv16i8.i8( %0, i8 9, @@ -846,10 +1003,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %0, %1, @@ -861,10 +1023,12 @@ } define @intrinsic_vmsgtu_vi_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv32i8.i8( %0, i8 9, @@ -874,10 +1038,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %0, %1, @@ -889,10 +1058,12 @@ } define @intrinsic_vmsgtu_vi_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv1i16.i16( %0, i16 9, @@ -902,10 +1073,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %0, %1, @@ -917,10 +1093,12 @@ } define @intrinsic_vmsgtu_vi_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv2i16.i16( %0, i16 9, @@ -930,10 +1108,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %0, %1, @@ -945,10 +1128,12 @@ } define @intrinsic_vmsgtu_vi_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv4i16.i16( %0, i16 9, @@ -958,10 +1143,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %0, %1, @@ -973,10 +1163,12 @@ } define @intrinsic_vmsgtu_vi_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv8i16.i16( %0, i16 9, @@ -986,10 +1178,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %0, %1, @@ -1001,10 +1198,12 @@ } define @intrinsic_vmsgtu_vi_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv16i16.i16( %0, i16 9, @@ -1014,10 +1213,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %0, %1, @@ -1029,10 +1233,12 @@ } define @intrinsic_vmsgtu_vi_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv1i32.i32( %0, i32 9, @@ -1042,10 +1248,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %0, %1, @@ -1057,10 +1268,12 @@ } define @intrinsic_vmsgtu_vi_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv2i32.i32( %0, i32 9, @@ -1070,10 +1283,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %0, %1, @@ -1085,10 +1303,12 @@ } define @intrinsic_vmsgtu_vi_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv4i32.i32( %0, i32 9, @@ -1098,10 +1318,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %0, %1, @@ -1113,10 +1338,12 @@ } define @intrinsic_vmsgtu_vi_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv8i32.i32( %0, i32 9, @@ -1126,10 +1353,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %0, %1, @@ -1141,10 +1373,12 @@ } define @intrinsic_vmsgtu_vi_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv1i64.i64( %0, i64 9, @@ -1154,10 +1388,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %0, %1, @@ -1169,10 +1408,12 @@ } define @intrinsic_vmsgtu_vi_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv2i64.i64( %0, i64 9, @@ -1182,10 +1423,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %0, %1, @@ -1197,10 +1443,12 @@ } define @intrinsic_vmsgtu_vi_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsgtu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsgtu.nxv4i64.i64( %0, i64 9, @@ -1210,10 +1458,15 @@ } define @intrinsic_vmsgtu_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsgtu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll @@ -30,8 +30,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -72,8 +72,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -114,8 +114,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -156,8 +156,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -198,8 +198,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -240,8 +240,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -282,8 +282,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll @@ -30,8 +30,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -72,8 +72,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -114,8 +114,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -156,8 +156,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -198,8 +198,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -240,8 +240,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -282,8 +282,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsif.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsif.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsle.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmsle_vv_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmsle_vv_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmsle_vv_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmsle_vv_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmsle_vv_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmsle_vv_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmsle_vv_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmsle_vv_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmsle_vv_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i32); define @intrinsic_vmsle_vv_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i32); define @intrinsic_vmsle_vv_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i32); define @intrinsic_vmsle_vv_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i32); define @intrinsic_vmsle_vv_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i32); define @intrinsic_vmsle_vv_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i32); define @intrinsic_vmsle_vv_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i32); define @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i32); define @intrinsic_vmsle_vx_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i8.i8( %0, i8 %1, @@ -686,10 +809,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i8.i8( %0, %1, @@ -706,10 +834,12 @@ i32); define @intrinsic_vmsle_vx_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i8.i8( %0, i8 %1, @@ -726,10 +856,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i8.i8( %0, %1, @@ -746,10 +881,12 @@ i32); define @intrinsic_vmsle_vx_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i8.i8( %0, i8 %1, @@ -766,10 +903,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i8.i8( %0, %1, @@ -786,10 +928,12 @@ i32); define @intrinsic_vmsle_vx_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i8.i8( %0, i8 %1, @@ -806,10 +950,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i8.i8( %0, %1, @@ -826,10 +975,12 @@ i32); define @intrinsic_vmsle_vx_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv16i8.i8( %0, i8 %1, @@ -846,10 +997,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv16i8.i8( %0, %1, @@ -866,10 +1022,12 @@ i32); define @intrinsic_vmsle_vx_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv32i8.i8( %0, i8 %1, @@ -886,10 +1044,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv32i8.i8( %0, %1, @@ -906,10 +1069,12 @@ i32); define @intrinsic_vmsle_vx_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i16.i16( %0, i16 %1, @@ -926,10 +1091,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i16.i16( %0, %1, @@ -946,10 +1116,12 @@ i32); define @intrinsic_vmsle_vx_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i16.i16( %0, i16 %1, @@ -966,10 +1138,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i16.i16( %0, %1, @@ -986,10 +1163,12 @@ i32); define @intrinsic_vmsle_vx_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i16.i16( %0, i16 %1, @@ -1006,10 +1185,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i16.i16( %0, %1, @@ -1026,10 +1210,12 @@ i32); define @intrinsic_vmsle_vx_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i16.i16( %0, i16 %1, @@ -1046,10 +1232,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i16.i16( %0, %1, @@ -1066,10 +1257,12 @@ i32); define @intrinsic_vmsle_vx_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv16i16.i16( %0, i16 %1, @@ -1086,10 +1279,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv16i16.i16( %0, %1, @@ -1106,10 +1304,12 @@ i32); define @intrinsic_vmsle_vx_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i32.i32( %0, i32 %1, @@ -1126,10 +1326,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i32.i32( %0, %1, @@ -1146,10 +1351,12 @@ i32); define @intrinsic_vmsle_vx_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i32.i32( %0, i32 %1, @@ -1166,10 +1373,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i32.i32( %0, %1, @@ -1186,10 +1398,12 @@ i32); define @intrinsic_vmsle_vx_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i32.i32( %0, i32 %1, @@ -1206,10 +1420,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i32.i32( %0, %1, @@ -1226,10 +1445,12 @@ i32); define @intrinsic_vmsle_vx_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1467,15 @@ i32); define @intrinsic_vmsle_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i32.i32( %0, %1, @@ -1261,10 +1487,12 @@ } define @intrinsic_vmsle_vi_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv1i8.i8( %0, i8 9, @@ -1274,10 +1502,15 @@ } define @intrinsic_vmsle_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i8.i8( %0, %1, @@ -1289,10 +1522,12 @@ } define @intrinsic_vmsle_vi_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv2i8.i8( %0, i8 9, @@ -1302,10 +1537,15 @@ } define @intrinsic_vmsle_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i8.i8( %0, %1, @@ -1317,10 +1557,12 @@ } define @intrinsic_vmsle_vi_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv4i8.i8( %0, i8 9, @@ -1330,10 +1572,15 @@ } define @intrinsic_vmsle_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i8.i8( %0, %1, @@ -1345,10 +1592,12 @@ } define @intrinsic_vmsle_vi_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv8i8.i8( %0, i8 9, @@ -1358,10 +1607,15 @@ } define @intrinsic_vmsle_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i8.i8( %0, %1, @@ -1373,10 +1627,12 @@ } define @intrinsic_vmsle_vi_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv16i8.i8( %0, i8 9, @@ -1386,10 +1642,15 @@ } define @intrinsic_vmsle_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv16i8.i8( %0, %1, @@ -1401,10 +1662,12 @@ } define @intrinsic_vmsle_vi_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv32i8.i8( %0, i8 9, @@ -1414,10 +1677,15 @@ } define @intrinsic_vmsle_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv32i8.i8( %0, %1, @@ -1429,10 +1697,12 @@ } define @intrinsic_vmsle_vi_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv1i16.i16( %0, i16 9, @@ -1442,10 +1712,15 @@ } define @intrinsic_vmsle_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i16.i16( %0, %1, @@ -1457,10 +1732,12 @@ } define @intrinsic_vmsle_vi_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv2i16.i16( %0, i16 9, @@ -1470,10 +1747,15 @@ } define @intrinsic_vmsle_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i16.i16( %0, %1, @@ -1485,10 +1767,12 @@ } define @intrinsic_vmsle_vi_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv4i16.i16( %0, i16 9, @@ -1498,10 +1782,15 @@ } define @intrinsic_vmsle_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i16.i16( %0, %1, @@ -1513,10 +1802,12 @@ } define @intrinsic_vmsle_vi_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv8i16.i16( %0, i16 9, @@ -1526,10 +1817,15 @@ } define @intrinsic_vmsle_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i16.i16( %0, %1, @@ -1541,10 +1837,12 @@ } define @intrinsic_vmsle_vi_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv16i16.i16( %0, i16 9, @@ -1554,10 +1852,15 @@ } define @intrinsic_vmsle_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv16i16.i16( %0, %1, @@ -1569,10 +1872,12 @@ } define @intrinsic_vmsle_vi_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv1i32.i32( %0, i32 9, @@ -1582,10 +1887,15 @@ } define @intrinsic_vmsle_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i32.i32( %0, %1, @@ -1597,10 +1907,12 @@ } define @intrinsic_vmsle_vi_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv2i32.i32( %0, i32 9, @@ -1610,10 +1922,15 @@ } define @intrinsic_vmsle_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i32.i32( %0, %1, @@ -1625,10 +1942,12 @@ } define @intrinsic_vmsle_vi_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv4i32.i32( %0, i32 9, @@ -1638,10 +1957,15 @@ } define @intrinsic_vmsle_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i32.i32( %0, %1, @@ -1653,10 +1977,12 @@ } define @intrinsic_vmsle_vi_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv8i32.i32( %0, i32 9, @@ -1666,10 +1992,15 @@ } define @intrinsic_vmsle_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsle.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmsle_vv_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmsle_vv_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmsle_vv_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmsle_vv_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmsle_vv_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmsle_vv_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmsle_vv_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmsle_vv_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmsle_vv_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmsle_vv_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmsle_vv_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmsle_vv_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i64); define @intrinsic_vmsle_vv_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i64); define @intrinsic_vmsle_vv_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i64); define @intrinsic_vmsle_vv_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i64); define @intrinsic_vmsle_vv_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i64( %0, %1, @@ -686,10 +809,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmsle.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv1i64( %1, %2, @@ -710,10 +839,12 @@ i64); define @intrinsic_vmsle_vv_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i64( %0, %1, @@ -730,10 +861,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmsle.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv2i64( %1, %2, @@ -754,10 +891,12 @@ i64); define @intrinsic_vmsle_vv_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i64( %0, %1, @@ -774,10 +913,16 @@ i64); define @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmsle.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsle.nxv4i64( %1, %2, @@ -798,10 +943,12 @@ i64); define @intrinsic_vmsle_vx_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i8.i8( %0, i8 %1, @@ -818,10 +965,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i8.i8( %0, %1, @@ -838,10 +990,12 @@ i64); define @intrinsic_vmsle_vx_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i8.i8( %0, i8 %1, @@ -858,10 +1012,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i8.i8( %0, %1, @@ -878,10 +1037,12 @@ i64); define @intrinsic_vmsle_vx_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i8.i8( %0, i8 %1, @@ -898,10 +1059,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i8.i8( %0, %1, @@ -918,10 +1084,12 @@ i64); define @intrinsic_vmsle_vx_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i8.i8( %0, i8 %1, @@ -938,10 +1106,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i8.i8( %0, %1, @@ -958,10 +1131,12 @@ i64); define @intrinsic_vmsle_vx_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv16i8.i8( %0, i8 %1, @@ -978,10 +1153,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv16i8.i8( %0, %1, @@ -998,10 +1178,12 @@ i64); define @intrinsic_vmsle_vx_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv32i8.i8( %0, i8 %1, @@ -1018,10 +1200,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv32i8.i8( %0, %1, @@ -1038,10 +1225,12 @@ i64); define @intrinsic_vmsle_vx_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i16.i16( %0, i16 %1, @@ -1058,10 +1247,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i16.i16( %0, %1, @@ -1078,10 +1272,12 @@ i64); define @intrinsic_vmsle_vx_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i16.i16( %0, i16 %1, @@ -1098,10 +1294,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i16.i16( %0, %1, @@ -1118,10 +1319,12 @@ i64); define @intrinsic_vmsle_vx_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i16.i16( %0, i16 %1, @@ -1138,10 +1341,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i16.i16( %0, %1, @@ -1158,10 +1366,12 @@ i64); define @intrinsic_vmsle_vx_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i16.i16( %0, i16 %1, @@ -1178,10 +1388,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i16.i16( %0, %1, @@ -1198,10 +1413,12 @@ i64); define @intrinsic_vmsle_vx_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv16i16.i16( %0, i16 %1, @@ -1218,10 +1435,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv16i16.i16( %0, %1, @@ -1238,10 +1460,12 @@ i64); define @intrinsic_vmsle_vx_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i32.i32( %0, i32 %1, @@ -1258,10 +1482,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i32.i32( %0, %1, @@ -1278,10 +1507,12 @@ i64); define @intrinsic_vmsle_vx_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i32.i32( %0, i32 %1, @@ -1298,10 +1529,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i32.i32( %0, %1, @@ -1318,10 +1554,12 @@ i64); define @intrinsic_vmsle_vx_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i32.i32( %0, i32 %1, @@ -1338,10 +1576,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i32.i32( %0, %1, @@ -1358,10 +1601,12 @@ i64); define @intrinsic_vmsle_vx_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv8i32.i32( %0, i32 %1, @@ -1378,10 +1623,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i32.i32( %0, %1, @@ -1398,10 +1648,12 @@ i64); define @intrinsic_vmsle_vx_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv1i64.i64( %0, i64 %1, @@ -1418,10 +1670,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i64.i64( %0, %1, @@ -1438,10 +1695,12 @@ i64); define @intrinsic_vmsle_vx_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv2i64.i64( %0, i64 %1, @@ -1458,10 +1717,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i64.i64( %0, %1, @@ -1478,10 +1742,12 @@ i64); define @intrinsic_vmsle_vx_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmsle.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsle.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1764,15 @@ i64); define @intrinsic_vmsle_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i64.i64( %0, %1, @@ -1513,10 +1784,12 @@ } define @intrinsic_vmsle_vi_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv1i8.i8( %0, i8 9, @@ -1526,10 +1799,15 @@ } define @intrinsic_vmsle_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i8.i8( %0, %1, @@ -1541,10 +1819,12 @@ } define @intrinsic_vmsle_vi_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv2i8.i8( %0, i8 9, @@ -1554,10 +1834,15 @@ } define @intrinsic_vmsle_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i8.i8( %0, %1, @@ -1569,10 +1854,12 @@ } define @intrinsic_vmsle_vi_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv4i8.i8( %0, i8 9, @@ -1582,10 +1869,15 @@ } define @intrinsic_vmsle_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i8.i8( %0, %1, @@ -1597,10 +1889,12 @@ } define @intrinsic_vmsle_vi_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv8i8.i8( %0, i8 9, @@ -1610,10 +1904,15 @@ } define @intrinsic_vmsle_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i8.i8( %0, %1, @@ -1625,10 +1924,12 @@ } define @intrinsic_vmsle_vi_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv16i8.i8( %0, i8 9, @@ -1638,10 +1939,15 @@ } define @intrinsic_vmsle_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv16i8.i8( %0, %1, @@ -1653,10 +1959,12 @@ } define @intrinsic_vmsle_vi_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv32i8.i8( %0, i8 9, @@ -1666,10 +1974,15 @@ } define @intrinsic_vmsle_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv32i8.i8( %0, %1, @@ -1681,10 +1994,12 @@ } define @intrinsic_vmsle_vi_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv1i16.i16( %0, i16 9, @@ -1694,10 +2009,15 @@ } define @intrinsic_vmsle_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i16.i16( %0, %1, @@ -1709,10 +2029,12 @@ } define @intrinsic_vmsle_vi_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv2i16.i16( %0, i16 9, @@ -1722,10 +2044,15 @@ } define @intrinsic_vmsle_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i16.i16( %0, %1, @@ -1737,10 +2064,12 @@ } define @intrinsic_vmsle_vi_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv4i16.i16( %0, i16 9, @@ -1750,10 +2079,15 @@ } define @intrinsic_vmsle_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i16.i16( %0, %1, @@ -1765,10 +2099,12 @@ } define @intrinsic_vmsle_vi_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv8i16.i16( %0, i16 9, @@ -1778,10 +2114,15 @@ } define @intrinsic_vmsle_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i16.i16( %0, %1, @@ -1793,10 +2134,12 @@ } define @intrinsic_vmsle_vi_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv16i16.i16( %0, i16 9, @@ -1806,10 +2149,15 @@ } define @intrinsic_vmsle_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv16i16.i16( %0, %1, @@ -1821,10 +2169,12 @@ } define @intrinsic_vmsle_vi_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv1i32.i32( %0, i32 9, @@ -1834,10 +2184,15 @@ } define @intrinsic_vmsle_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i32.i32( %0, %1, @@ -1849,10 +2204,12 @@ } define @intrinsic_vmsle_vi_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv2i32.i32( %0, i32 9, @@ -1862,10 +2219,15 @@ } define @intrinsic_vmsle_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i32.i32( %0, %1, @@ -1877,10 +2239,12 @@ } define @intrinsic_vmsle_vi_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv4i32.i32( %0, i32 9, @@ -1890,10 +2254,15 @@ } define @intrinsic_vmsle_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i32.i32( %0, %1, @@ -1905,10 +2274,12 @@ } define @intrinsic_vmsle_vi_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv8i32.i32( %0, i32 9, @@ -1918,10 +2289,15 @@ } define @intrinsic_vmsle_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv8i32.i32( %0, %1, @@ -1933,10 +2309,12 @@ } define @intrinsic_vmsle_vi_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv1i64.i64( %0, i64 9, @@ -1946,10 +2324,15 @@ } define @intrinsic_vmsle_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv1i64.i64( %0, %1, @@ -1961,10 +2344,12 @@ } define @intrinsic_vmsle_vi_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv2i64.i64( %0, i64 9, @@ -1974,10 +2359,15 @@ } define @intrinsic_vmsle_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv2i64.i64( %0, %1, @@ -1989,10 +2379,12 @@ } define @intrinsic_vmsle_vi_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsle.nxv4i64.i64( %0, i64 9, @@ -2002,10 +2394,15 @@ } define @intrinsic_vmsle_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsle.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsle.mask.nxv4i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsleu.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmsleu_vv_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmsleu_vv_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmsleu_vv_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmsleu_vv_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmsleu_vv_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmsleu_vv_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmsleu_vv_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmsleu_vv_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmsleu_vv_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i32); define @intrinsic_vmsleu_vv_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i32); define @intrinsic_vmsleu_vv_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i32); define @intrinsic_vmsleu_vv_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i32); define @intrinsic_vmsleu_vv_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i32); define @intrinsic_vmsleu_vv_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i32); define @intrinsic_vmsleu_vv_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i32); define @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i32); define @intrinsic_vmsleu_vx_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i8.i8( %0, i8 %1, @@ -686,10 +809,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i8.i8( %0, %1, @@ -706,10 +834,12 @@ i32); define @intrinsic_vmsleu_vx_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i8.i8( %0, i8 %1, @@ -726,10 +856,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i8.i8( %0, %1, @@ -746,10 +881,12 @@ i32); define @intrinsic_vmsleu_vx_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i8.i8( %0, i8 %1, @@ -766,10 +903,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i8.i8( %0, %1, @@ -786,10 +928,12 @@ i32); define @intrinsic_vmsleu_vx_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i8.i8( %0, i8 %1, @@ -806,10 +950,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i8.i8( %0, %1, @@ -826,10 +975,12 @@ i32); define @intrinsic_vmsleu_vx_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv16i8.i8( %0, i8 %1, @@ -846,10 +997,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv16i8.i8( %0, %1, @@ -866,10 +1022,12 @@ i32); define @intrinsic_vmsleu_vx_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv32i8.i8( %0, i8 %1, @@ -886,10 +1044,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv32i8.i8( %0, %1, @@ -906,10 +1069,12 @@ i32); define @intrinsic_vmsleu_vx_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i16.i16( %0, i16 %1, @@ -926,10 +1091,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i16.i16( %0, %1, @@ -946,10 +1116,12 @@ i32); define @intrinsic_vmsleu_vx_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i16.i16( %0, i16 %1, @@ -966,10 +1138,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i16.i16( %0, %1, @@ -986,10 +1163,12 @@ i32); define @intrinsic_vmsleu_vx_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i16.i16( %0, i16 %1, @@ -1006,10 +1185,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i16.i16( %0, %1, @@ -1026,10 +1210,12 @@ i32); define @intrinsic_vmsleu_vx_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i16.i16( %0, i16 %1, @@ -1046,10 +1232,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i16.i16( %0, %1, @@ -1066,10 +1257,12 @@ i32); define @intrinsic_vmsleu_vx_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv16i16.i16( %0, i16 %1, @@ -1086,10 +1279,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv16i16.i16( %0, %1, @@ -1106,10 +1304,12 @@ i32); define @intrinsic_vmsleu_vx_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i32.i32( %0, i32 %1, @@ -1126,10 +1326,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i32.i32( %0, %1, @@ -1146,10 +1351,12 @@ i32); define @intrinsic_vmsleu_vx_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i32.i32( %0, i32 %1, @@ -1166,10 +1373,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i32.i32( %0, %1, @@ -1186,10 +1398,12 @@ i32); define @intrinsic_vmsleu_vx_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i32.i32( %0, i32 %1, @@ -1206,10 +1420,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i32.i32( %0, %1, @@ -1226,10 +1445,12 @@ i32); define @intrinsic_vmsleu_vx_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1467,15 @@ i32); define @intrinsic_vmsleu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i32.i32( %0, %1, @@ -1261,10 +1487,12 @@ } define @intrinsic_vmsleu_vi_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv1i8.i8( %0, i8 9, @@ -1274,10 +1502,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i8.i8( %0, %1, @@ -1289,10 +1522,12 @@ } define @intrinsic_vmsleu_vi_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv2i8.i8( %0, i8 9, @@ -1302,10 +1537,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i8.i8( %0, %1, @@ -1317,10 +1557,12 @@ } define @intrinsic_vmsleu_vi_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv4i8.i8( %0, i8 9, @@ -1330,10 +1572,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i8.i8( %0, %1, @@ -1345,10 +1592,12 @@ } define @intrinsic_vmsleu_vi_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv8i8.i8( %0, i8 9, @@ -1358,10 +1607,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i8.i8( %0, %1, @@ -1373,10 +1627,12 @@ } define @intrinsic_vmsleu_vi_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv16i8.i8( %0, i8 9, @@ -1386,10 +1642,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv16i8.i8( %0, %1, @@ -1401,10 +1662,12 @@ } define @intrinsic_vmsleu_vi_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv32i8.i8( %0, i8 9, @@ -1414,10 +1677,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv32i8.i8( %0, %1, @@ -1429,10 +1697,12 @@ } define @intrinsic_vmsleu_vi_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv1i16.i16( %0, i16 9, @@ -1442,10 +1712,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i16.i16( %0, %1, @@ -1457,10 +1732,12 @@ } define @intrinsic_vmsleu_vi_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv2i16.i16( %0, i16 9, @@ -1470,10 +1747,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i16.i16( %0, %1, @@ -1485,10 +1767,12 @@ } define @intrinsic_vmsleu_vi_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv4i16.i16( %0, i16 9, @@ -1498,10 +1782,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i16.i16( %0, %1, @@ -1513,10 +1802,12 @@ } define @intrinsic_vmsleu_vi_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv8i16.i16( %0, i16 9, @@ -1526,10 +1817,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i16.i16( %0, %1, @@ -1541,10 +1837,12 @@ } define @intrinsic_vmsleu_vi_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv16i16.i16( %0, i16 9, @@ -1554,10 +1852,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv16i16.i16( %0, %1, @@ -1569,10 +1872,12 @@ } define @intrinsic_vmsleu_vi_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv1i32.i32( %0, i32 9, @@ -1582,10 +1887,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i32.i32( %0, %1, @@ -1597,10 +1907,12 @@ } define @intrinsic_vmsleu_vi_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv2i32.i32( %0, i32 9, @@ -1610,10 +1922,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i32.i32( %0, %1, @@ -1625,10 +1942,12 @@ } define @intrinsic_vmsleu_vi_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv4i32.i32( %0, i32 9, @@ -1638,10 +1957,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i32.i32( %0, %1, @@ -1653,10 +1977,12 @@ } define @intrinsic_vmsleu_vi_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv8i32.i32( %0, i32 9, @@ -1666,10 +1992,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsleu.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmsleu_vv_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmsleu_vv_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmsleu_vv_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmsleu_vv_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmsleu_vv_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmsleu_vv_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmsleu_vv_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmsleu_vv_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmsleu_vv_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmsleu_vv_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmsleu_vv_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmsleu_vv_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i64); define @intrinsic_vmsleu_vv_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i64); define @intrinsic_vmsleu_vv_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i64); define @intrinsic_vmsleu_vv_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i64); define @intrinsic_vmsleu_vv_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i64( %0, %1, @@ -686,10 +809,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv1i64( %1, %2, @@ -710,10 +839,12 @@ i64); define @intrinsic_vmsleu_vv_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i64( %0, %1, @@ -730,10 +861,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv2i64( %1, %2, @@ -754,10 +891,12 @@ i64); define @intrinsic_vmsleu_vv_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i64( %0, %1, @@ -774,10 +913,16 @@ i64); define @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmsleu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsleu.nxv4i64( %1, %2, @@ -798,10 +943,12 @@ i64); define @intrinsic_vmsleu_vx_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i8.i8( %0, i8 %1, @@ -818,10 +965,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i8.i8( %0, %1, @@ -838,10 +990,12 @@ i64); define @intrinsic_vmsleu_vx_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i8.i8( %0, i8 %1, @@ -858,10 +1012,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i8.i8( %0, %1, @@ -878,10 +1037,12 @@ i64); define @intrinsic_vmsleu_vx_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i8.i8( %0, i8 %1, @@ -898,10 +1059,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i8.i8( %0, %1, @@ -918,10 +1084,12 @@ i64); define @intrinsic_vmsleu_vx_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i8.i8( %0, i8 %1, @@ -938,10 +1106,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i8.i8( %0, %1, @@ -958,10 +1131,12 @@ i64); define @intrinsic_vmsleu_vx_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv16i8.i8( %0, i8 %1, @@ -978,10 +1153,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv16i8.i8( %0, %1, @@ -998,10 +1178,12 @@ i64); define @intrinsic_vmsleu_vx_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv32i8.i8( %0, i8 %1, @@ -1018,10 +1200,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv32i8.i8( %0, %1, @@ -1038,10 +1225,12 @@ i64); define @intrinsic_vmsleu_vx_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i16.i16( %0, i16 %1, @@ -1058,10 +1247,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i16.i16( %0, %1, @@ -1078,10 +1272,12 @@ i64); define @intrinsic_vmsleu_vx_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i16.i16( %0, i16 %1, @@ -1098,10 +1294,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i16.i16( %0, %1, @@ -1118,10 +1319,12 @@ i64); define @intrinsic_vmsleu_vx_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i16.i16( %0, i16 %1, @@ -1138,10 +1341,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i16.i16( %0, %1, @@ -1158,10 +1366,12 @@ i64); define @intrinsic_vmsleu_vx_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i16.i16( %0, i16 %1, @@ -1178,10 +1388,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i16.i16( %0, %1, @@ -1198,10 +1413,12 @@ i64); define @intrinsic_vmsleu_vx_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv16i16.i16( %0, i16 %1, @@ -1218,10 +1435,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv16i16.i16( %0, %1, @@ -1238,10 +1460,12 @@ i64); define @intrinsic_vmsleu_vx_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i32.i32( %0, i32 %1, @@ -1258,10 +1482,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i32.i32( %0, %1, @@ -1278,10 +1507,12 @@ i64); define @intrinsic_vmsleu_vx_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i32.i32( %0, i32 %1, @@ -1298,10 +1529,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i32.i32( %0, %1, @@ -1318,10 +1554,12 @@ i64); define @intrinsic_vmsleu_vx_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i32.i32( %0, i32 %1, @@ -1338,10 +1576,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i32.i32( %0, %1, @@ -1358,10 +1601,12 @@ i64); define @intrinsic_vmsleu_vx_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv8i32.i32( %0, i32 %1, @@ -1378,10 +1623,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i32.i32( %0, %1, @@ -1398,10 +1648,12 @@ i64); define @intrinsic_vmsleu_vx_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv1i64.i64( %0, i64 %1, @@ -1418,10 +1670,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i64.i64( %0, %1, @@ -1438,10 +1695,12 @@ i64); define @intrinsic_vmsleu_vx_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv2i64.i64( %0, i64 %1, @@ -1458,10 +1717,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i64.i64( %0, %1, @@ -1478,10 +1742,12 @@ i64); define @intrinsic_vmsleu_vx_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmsleu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsleu.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1764,15 @@ i64); define @intrinsic_vmsleu_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i64.i64( %0, %1, @@ -1513,10 +1784,12 @@ } define @intrinsic_vmsleu_vi_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv1i8.i8( %0, i8 9, @@ -1526,10 +1799,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i8.i8( %0, %1, @@ -1541,10 +1819,12 @@ } define @intrinsic_vmsleu_vi_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv2i8.i8( %0, i8 9, @@ -1554,10 +1834,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i8.i8( %0, %1, @@ -1569,10 +1854,12 @@ } define @intrinsic_vmsleu_vi_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv4i8.i8( %0, i8 9, @@ -1582,10 +1869,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i8.i8( %0, %1, @@ -1597,10 +1889,12 @@ } define @intrinsic_vmsleu_vi_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv8i8.i8( %0, i8 9, @@ -1610,10 +1904,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i8.i8( %0, %1, @@ -1625,10 +1924,12 @@ } define @intrinsic_vmsleu_vi_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv16i8.i8( %0, i8 9, @@ -1638,10 +1939,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv16i8.i8( %0, %1, @@ -1653,10 +1959,12 @@ } define @intrinsic_vmsleu_vi_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv32i8.i8( %0, i8 9, @@ -1666,10 +1974,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv32i8.i8( %0, %1, @@ -1681,10 +1994,12 @@ } define @intrinsic_vmsleu_vi_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv1i16.i16( %0, i16 9, @@ -1694,10 +2009,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i16.i16( %0, %1, @@ -1709,10 +2029,12 @@ } define @intrinsic_vmsleu_vi_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv2i16.i16( %0, i16 9, @@ -1722,10 +2044,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i16.i16( %0, %1, @@ -1737,10 +2064,12 @@ } define @intrinsic_vmsleu_vi_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv4i16.i16( %0, i16 9, @@ -1750,10 +2079,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i16.i16( %0, %1, @@ -1765,10 +2099,12 @@ } define @intrinsic_vmsleu_vi_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv8i16.i16( %0, i16 9, @@ -1778,10 +2114,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i16.i16( %0, %1, @@ -1793,10 +2134,12 @@ } define @intrinsic_vmsleu_vi_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv16i16.i16( %0, i16 9, @@ -1806,10 +2149,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv16i16.i16( %0, %1, @@ -1821,10 +2169,12 @@ } define @intrinsic_vmsleu_vi_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv1i32.i32( %0, i32 9, @@ -1834,10 +2184,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i32.i32( %0, %1, @@ -1849,10 +2204,12 @@ } define @intrinsic_vmsleu_vi_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv2i32.i32( %0, i32 9, @@ -1862,10 +2219,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i32.i32( %0, %1, @@ -1877,10 +2239,12 @@ } define @intrinsic_vmsleu_vi_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv4i32.i32( %0, i32 9, @@ -1890,10 +2254,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i32.i32( %0, %1, @@ -1905,10 +2274,12 @@ } define @intrinsic_vmsleu_vi_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv8i32.i32( %0, i32 9, @@ -1918,10 +2289,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv8i32.i32( %0, %1, @@ -1933,10 +2309,12 @@ } define @intrinsic_vmsleu_vi_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv1i64.i64( %0, i64 9, @@ -1946,10 +2324,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv1i64.i64( %0, %1, @@ -1961,10 +2344,12 @@ } define @intrinsic_vmsleu_vi_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv2i64.i64( %0, i64 9, @@ -1974,10 +2359,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv2i64.i64( %0, %1, @@ -1989,10 +2379,12 @@ } define @intrinsic_vmsleu_vi_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsleu.nxv4i64.i64( %0, i64 9, @@ -2002,10 +2394,15 @@ } define @intrinsic_vmsleu_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsleu.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsleu.mask.nxv4i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmslt.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmslt_vv_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmslt_vv_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmslt_vv_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmslt_vv_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmslt_vv_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmslt_vv_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmslt_vv_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmslt_vv_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmslt_vv_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i32); define @intrinsic_vmslt_vv_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i32); define @intrinsic_vmslt_vv_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i32); define @intrinsic_vmslt_vv_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i32); define @intrinsic_vmslt_vv_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i32); define @intrinsic_vmslt_vv_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i32); define @intrinsic_vmslt_vv_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i32); define @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i32); define @intrinsic_vmslt_vx_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i8.i8( %0, i8 %1, @@ -686,10 +809,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i8.i8( %0, %1, @@ -706,10 +834,12 @@ i32); define @intrinsic_vmslt_vx_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i8.i8( %0, i8 %1, @@ -726,10 +856,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i8.i8( %0, %1, @@ -746,10 +881,12 @@ i32); define @intrinsic_vmslt_vx_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i8.i8( %0, i8 %1, @@ -766,10 +903,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i8.i8( %0, %1, @@ -786,10 +928,12 @@ i32); define @intrinsic_vmslt_vx_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i8.i8( %0, i8 %1, @@ -806,10 +950,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i8.i8( %0, %1, @@ -826,10 +975,12 @@ i32); define @intrinsic_vmslt_vx_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv16i8.i8( %0, i8 %1, @@ -846,10 +997,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv16i8.i8( %0, %1, @@ -866,10 +1022,12 @@ i32); define @intrinsic_vmslt_vx_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv32i8.i8( %0, i8 %1, @@ -886,10 +1044,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv32i8.i8( %0, %1, @@ -906,10 +1069,12 @@ i32); define @intrinsic_vmslt_vx_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i16.i16( %0, i16 %1, @@ -926,10 +1091,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i16.i16( %0, %1, @@ -946,10 +1116,12 @@ i32); define @intrinsic_vmslt_vx_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i16.i16( %0, i16 %1, @@ -966,10 +1138,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i16.i16( %0, %1, @@ -986,10 +1163,12 @@ i32); define @intrinsic_vmslt_vx_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i16.i16( %0, i16 %1, @@ -1006,10 +1185,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i16.i16( %0, %1, @@ -1026,10 +1210,12 @@ i32); define @intrinsic_vmslt_vx_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i16.i16( %0, i16 %1, @@ -1046,10 +1232,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i16.i16( %0, %1, @@ -1066,10 +1257,12 @@ i32); define @intrinsic_vmslt_vx_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv16i16.i16( %0, i16 %1, @@ -1086,10 +1279,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv16i16.i16( %0, %1, @@ -1106,10 +1304,12 @@ i32); define @intrinsic_vmslt_vx_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i32.i32( %0, i32 %1, @@ -1126,10 +1326,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i32.i32( %0, %1, @@ -1146,10 +1351,12 @@ i32); define @intrinsic_vmslt_vx_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i32.i32( %0, i32 %1, @@ -1166,10 +1373,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i32.i32( %0, %1, @@ -1186,10 +1398,12 @@ i32); define @intrinsic_vmslt_vx_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i32.i32( %0, i32 %1, @@ -1206,10 +1420,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i32.i32( %0, %1, @@ -1226,10 +1445,12 @@ i32); define @intrinsic_vmslt_vx_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1467,15 @@ i32); define @intrinsic_vmslt_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i32.i32( %0, %1, @@ -1261,10 +1487,12 @@ } define @intrinsic_vmslt_vi_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -16 %a = call @llvm.riscv.vmslt.nxv1i8.i8( %0, i8 -15, @@ -1274,10 +1502,13 @@ } define @intrinsic_vmslt_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -15, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i8.i8( %0, %1, @@ -1289,10 +1520,12 @@ } define @intrinsic_vmslt_vi_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -14 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -14 %a = call @llvm.riscv.vmslt.nxv2i8.i8( %0, i8 -13, @@ -1302,10 +1535,13 @@ } define @intrinsic_vmslt_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -13, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i8.i8( %0, %1, @@ -1317,10 +1553,12 @@ } define @intrinsic_vmslt_vi_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -12 %a = call @llvm.riscv.vmslt.nxv4i8.i8( %0, i8 -11, @@ -1330,10 +1568,13 @@ } define @intrinsic_vmslt_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -11, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i8.i8( %0, %1, @@ -1345,10 +1586,12 @@ } define @intrinsic_vmslt_vi_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -10 %a = call @llvm.riscv.vmslt.nxv8i8.i8( %0, i8 -9, @@ -1358,10 +1601,13 @@ } define @intrinsic_vmslt_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i8.i8( %0, %1, @@ -1373,10 +1619,12 @@ } define @intrinsic_vmslt_vi_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -8 %a = call @llvm.riscv.vmslt.nxv16i8.i8( %0, i8 -7, @@ -1386,10 +1634,13 @@ } define @intrinsic_vmslt_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsle.vi v10, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -7, v0.t %a = call @llvm.riscv.vmslt.mask.nxv16i8.i8( %0, %1, @@ -1401,10 +1652,12 @@ } define @intrinsic_vmslt_vi_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -6 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -6 %a = call @llvm.riscv.vmslt.nxv32i8.i8( %0, i8 -5, @@ -1414,10 +1667,13 @@ } define @intrinsic_vmslt_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsle.vi v12, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -5, v0.t %a = call @llvm.riscv.vmslt.mask.nxv32i8.i8( %0, %1, @@ -1429,10 +1685,12 @@ } define @intrinsic_vmslt_vi_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -4 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -4 %a = call @llvm.riscv.vmslt.nxv1i16.i16( %0, i16 -3, @@ -1442,10 +1700,13 @@ } define @intrinsic_vmslt_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -3, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i16.i16( %0, %1, @@ -1457,10 +1718,12 @@ } define @intrinsic_vmslt_vi_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -2 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -2 %a = call @llvm.riscv.vmslt.nxv2i16.i16( %0, i16 -1, @@ -1470,10 +1733,13 @@ } define @intrinsic_vmslt_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -1, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -1, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i16.i16( %0, %1, @@ -1485,10 +1751,12 @@ } define @intrinsic_vmslt_vi_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -1 %a = call @llvm.riscv.vmslt.nxv4i16.i16( %0, i16 0, @@ -1498,10 +1766,13 @@ } define @intrinsic_vmslt_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 0, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i16.i16( %0, %1, @@ -1513,10 +1784,12 @@ } define @intrinsic_vmslt_vi_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 1 %a = call @llvm.riscv.vmslt.nxv8i16.i16( %0, i16 2, @@ -1526,10 +1799,13 @@ } define @intrinsic_vmslt_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsle.vi v10, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 2, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i16.i16( %0, %1, @@ -1541,10 +1817,12 @@ } define @intrinsic_vmslt_vi_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 3 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 3 %a = call @llvm.riscv.vmslt.nxv16i16.i16( %0, i16 4, @@ -1554,10 +1832,13 @@ } define @intrinsic_vmslt_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsle.vi v12, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 4, v0.t %a = call @llvm.riscv.vmslt.mask.nxv16i16.i16( %0, %1, @@ -1569,10 +1850,12 @@ } define @intrinsic_vmslt_vi_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 5 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 5 %a = call @llvm.riscv.vmslt.nxv1i32.i32( %0, i32 6, @@ -1582,10 +1865,13 @@ } define @intrinsic_vmslt_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 6, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i32.i32( %0, %1, @@ -1597,10 +1883,12 @@ } define @intrinsic_vmslt_vi_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 7 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 7 %a = call @llvm.riscv.vmslt.nxv2i32.i32( %0, i32 8, @@ -1610,10 +1898,13 @@ } define @intrinsic_vmslt_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 8, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i32.i32( %0, %1, @@ -1625,10 +1916,12 @@ } define @intrinsic_vmslt_vi_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmslt.nxv4i32.i32( %0, i32 10, @@ -1638,10 +1931,13 @@ } define @intrinsic_vmslt_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsle.vi v10, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 10, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i32.i32( %0, %1, @@ -1653,10 +1949,12 @@ } define @intrinsic_vmslt_vi_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 11 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 11 %a = call @llvm.riscv.vmslt.nxv8i32.i32( %0, i32 12, @@ -1666,10 +1964,13 @@ } define @intrinsic_vmslt_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsle.vi v12, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 12, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmslt.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmslt_vv_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmslt_vv_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmslt_vv_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmslt_vv_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmslt_vv_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmslt_vv_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmslt_vv_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmslt_vv_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmslt_vv_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmslt_vv_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmslt_vv_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmslt_vv_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i64); define @intrinsic_vmslt_vv_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i64); define @intrinsic_vmslt_vv_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i64); define @intrinsic_vmslt_vv_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i64); define @intrinsic_vmslt_vv_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i64( %0, %1, @@ -686,10 +809,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmslt.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv1i64( %1, %2, @@ -710,10 +839,12 @@ i64); define @intrinsic_vmslt_vv_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i64( %0, %1, @@ -730,10 +861,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmslt.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv2i64( %1, %2, @@ -754,10 +891,12 @@ i64); define @intrinsic_vmslt_vv_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i64( %0, %1, @@ -774,10 +913,16 @@ i64); define @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmslt.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmslt.nxv4i64( %1, %2, @@ -798,10 +943,12 @@ i64); define @intrinsic_vmslt_vx_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i8.i8( %0, i8 %1, @@ -818,10 +965,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i8.i8( %0, %1, @@ -838,10 +990,12 @@ i64); define @intrinsic_vmslt_vx_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i8.i8( %0, i8 %1, @@ -858,10 +1012,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i8.i8( %0, %1, @@ -878,10 +1037,12 @@ i64); define @intrinsic_vmslt_vx_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i8.i8( %0, i8 %1, @@ -898,10 +1059,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i8.i8( %0, %1, @@ -918,10 +1084,12 @@ i64); define @intrinsic_vmslt_vx_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i8.i8( %0, i8 %1, @@ -938,10 +1106,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i8.i8( %0, %1, @@ -958,10 +1131,12 @@ i64); define @intrinsic_vmslt_vx_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv16i8.i8( %0, i8 %1, @@ -978,10 +1153,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv16i8.i8( %0, %1, @@ -998,10 +1178,12 @@ i64); define @intrinsic_vmslt_vx_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv32i8.i8( %0, i8 %1, @@ -1018,10 +1200,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv32i8.i8( %0, %1, @@ -1038,10 +1225,12 @@ i64); define @intrinsic_vmslt_vx_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i16.i16( %0, i16 %1, @@ -1058,10 +1247,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i16.i16( %0, %1, @@ -1078,10 +1272,12 @@ i64); define @intrinsic_vmslt_vx_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i16.i16( %0, i16 %1, @@ -1098,10 +1294,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i16.i16( %0, %1, @@ -1118,10 +1319,12 @@ i64); define @intrinsic_vmslt_vx_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i16.i16( %0, i16 %1, @@ -1138,10 +1341,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i16.i16( %0, %1, @@ -1158,10 +1366,12 @@ i64); define @intrinsic_vmslt_vx_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i16.i16( %0, i16 %1, @@ -1178,10 +1388,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i16.i16( %0, %1, @@ -1198,10 +1413,12 @@ i64); define @intrinsic_vmslt_vx_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv16i16.i16( %0, i16 %1, @@ -1218,10 +1435,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv16i16.i16( %0, %1, @@ -1238,10 +1460,12 @@ i64); define @intrinsic_vmslt_vx_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i32.i32( %0, i32 %1, @@ -1258,10 +1482,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i32.i32( %0, %1, @@ -1278,10 +1507,12 @@ i64); define @intrinsic_vmslt_vx_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i32.i32( %0, i32 %1, @@ -1298,10 +1529,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i32.i32( %0, %1, @@ -1318,10 +1554,12 @@ i64); define @intrinsic_vmslt_vx_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i32.i32( %0, i32 %1, @@ -1338,10 +1576,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i32.i32( %0, %1, @@ -1358,10 +1601,12 @@ i64); define @intrinsic_vmslt_vx_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv8i32.i32( %0, i32 %1, @@ -1378,10 +1623,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i32.i32( %0, %1, @@ -1398,10 +1648,12 @@ i64); define @intrinsic_vmslt_vx_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv1i64.i64( %0, i64 %1, @@ -1418,10 +1670,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i64.i64( %0, %1, @@ -1438,10 +1695,12 @@ i64); define @intrinsic_vmslt_vx_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv2i64.i64( %0, i64 %1, @@ -1458,10 +1717,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i64.i64( %0, %1, @@ -1478,10 +1742,12 @@ i64); define @intrinsic_vmslt_vx_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmslt.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmslt.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1764,15 @@ i64); define @intrinsic_vmslt_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmslt.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i64.i64( %0, %1, @@ -1513,10 +1784,12 @@ } define @intrinsic_vmslt_vi_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -16 %a = call @llvm.riscv.vmslt.nxv1i8.i8( %0, i8 -15, @@ -1526,10 +1799,13 @@ } define @intrinsic_vmslt_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -15, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i8.i8( %0, %1, @@ -1541,10 +1817,12 @@ } define @intrinsic_vmslt_vi_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -14 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -14 %a = call @llvm.riscv.vmslt.nxv2i8.i8( %0, i8 -13, @@ -1554,10 +1832,13 @@ } define @intrinsic_vmslt_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -13, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i8.i8( %0, %1, @@ -1569,10 +1850,12 @@ } define @intrinsic_vmslt_vi_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -12 %a = call @llvm.riscv.vmslt.nxv4i8.i8( %0, i8 -11, @@ -1582,10 +1865,13 @@ } define @intrinsic_vmslt_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -11, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i8.i8( %0, %1, @@ -1597,10 +1883,12 @@ } define @intrinsic_vmslt_vi_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -10 %a = call @llvm.riscv.vmslt.nxv8i8.i8( %0, i8 -9, @@ -1610,10 +1898,13 @@ } define @intrinsic_vmslt_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i8.i8( %0, %1, @@ -1625,10 +1916,12 @@ } define @intrinsic_vmslt_vi_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -8 %a = call @llvm.riscv.vmslt.nxv16i8.i8( %0, i8 -7, @@ -1638,10 +1931,13 @@ } define @intrinsic_vmslt_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsle.vi v10, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -7, v0.t %a = call @llvm.riscv.vmslt.mask.nxv16i8.i8( %0, %1, @@ -1653,10 +1949,12 @@ } define @intrinsic_vmslt_vi_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -6 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -6 %a = call @llvm.riscv.vmslt.nxv32i8.i8( %0, i8 -5, @@ -1666,10 +1964,13 @@ } define @intrinsic_vmslt_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsle.vi v12, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -5, v0.t %a = call @llvm.riscv.vmslt.mask.nxv32i8.i8( %0, %1, @@ -1681,10 +1982,12 @@ } define @intrinsic_vmslt_vi_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -4 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -4 %a = call @llvm.riscv.vmslt.nxv1i16.i16( %0, i16 -3, @@ -1694,10 +1997,13 @@ } define @intrinsic_vmslt_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -3, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i16.i16( %0, %1, @@ -1709,10 +2015,12 @@ } define @intrinsic_vmslt_vi_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -2 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -2 %a = call @llvm.riscv.vmslt.nxv2i16.i16( %0, i16 -1, @@ -1722,10 +2030,13 @@ } define @intrinsic_vmslt_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, -1, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -1, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i16.i16( %0, %1, @@ -1737,10 +2048,12 @@ } define @intrinsic_vmslt_vi_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -1 %a = call @llvm.riscv.vmslt.nxv4i16.i16( %0, i16 0, @@ -1750,10 +2063,13 @@ } define @intrinsic_vmslt_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 0, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i16.i16( %0, %1, @@ -1765,10 +2081,12 @@ } define @intrinsic_vmslt_vi_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 1 %a = call @llvm.riscv.vmslt.nxv8i16.i16( %0, i16 2, @@ -1778,10 +2096,13 @@ } define @intrinsic_vmslt_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsle.vi v10, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 2, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i16.i16( %0, %1, @@ -1793,10 +2114,12 @@ } define @intrinsic_vmslt_vi_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 3 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 3 %a = call @llvm.riscv.vmslt.nxv16i16.i16( %0, i16 4, @@ -1806,10 +2129,13 @@ } define @intrinsic_vmslt_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsle.vi v12, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 4, v0.t %a = call @llvm.riscv.vmslt.mask.nxv16i16.i16( %0, %1, @@ -1821,10 +2147,12 @@ } define @intrinsic_vmslt_vi_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 5 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 5 %a = call @llvm.riscv.vmslt.nxv1i32.i32( %0, i32 6, @@ -1834,10 +2162,13 @@ } define @intrinsic_vmslt_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 6, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i32.i32( %0, %1, @@ -1849,10 +2180,12 @@ } define @intrinsic_vmslt_vi_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 7 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 7 %a = call @llvm.riscv.vmslt.nxv2i32.i32( %0, i32 8, @@ -1862,10 +2195,13 @@ } define @intrinsic_vmslt_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 8, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i32.i32( %0, %1, @@ -1877,10 +2213,12 @@ } define @intrinsic_vmslt_vi_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmslt.nxv4i32.i32( %0, i32 10, @@ -1890,10 +2228,13 @@ } define @intrinsic_vmslt_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsle.vi v10, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 10, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i32.i32( %0, %1, @@ -1905,10 +2246,12 @@ } define @intrinsic_vmslt_vi_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 11 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 11 %a = call @llvm.riscv.vmslt.nxv8i32.i32( %0, i32 12, @@ -1918,10 +2261,13 @@ } define @intrinsic_vmslt_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsle.vi v12, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 12, v0.t %a = call @llvm.riscv.vmslt.mask.nxv8i32.i32( %0, %1, @@ -1933,10 +2279,12 @@ } define @intrinsic_vmslt_vi_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 13 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 13 %a = call @llvm.riscv.vmslt.nxv1i64.i64( %0, i64 14, @@ -1946,10 +2294,13 @@ } define @intrinsic_vmslt_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmsle.vi v9, v8, 14, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 14, v0.t %a = call @llvm.riscv.vmslt.mask.nxv1i64.i64( %0, %1, @@ -1961,10 +2312,12 @@ } define @intrinsic_vmslt_vi_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, 15 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 15 %a = call @llvm.riscv.vmslt.nxv2i64.i64( %0, i64 16, @@ -1974,10 +2327,13 @@ } define @intrinsic_vmslt_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmsle.vi v10, v8, -16, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -16, v0.t %a = call @llvm.riscv.vmslt.mask.nxv2i64.i64( %0, %1, @@ -1989,10 +2345,12 @@ } define @intrinsic_vmslt_vi_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsle.vi v0, v8, -15 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -15 %a = call @llvm.riscv.vmslt.nxv4i64.i64( %0, i64 -14, @@ -2002,10 +2360,13 @@ } define @intrinsic_vmslt_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmsle.vi v12, v8, -14, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, -14, v0.t %a = call @llvm.riscv.vmslt.mask.nxv4i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsltu.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmsltu_vv_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmsltu_vv_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmsltu_vv_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmsltu_vv_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmsltu_vv_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmsltu_vv_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmsltu_vv_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmsltu_vv_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmsltu_vv_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i32); define @intrinsic_vmsltu_vv_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i32); define @intrinsic_vmsltu_vv_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i32); define @intrinsic_vmsltu_vv_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i32); define @intrinsic_vmsltu_vv_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i32); define @intrinsic_vmsltu_vv_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i32); define @intrinsic_vmsltu_vv_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i32); define @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i32); define @intrinsic_vmsltu_vx_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i8.i8( %0, i8 %1, @@ -686,10 +809,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i8.i8( %0, %1, @@ -706,10 +834,12 @@ i32); define @intrinsic_vmsltu_vx_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i8.i8( %0, i8 %1, @@ -726,10 +856,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i8.i8( %0, %1, @@ -746,10 +881,12 @@ i32); define @intrinsic_vmsltu_vx_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i8.i8( %0, i8 %1, @@ -766,10 +903,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i8.i8( %0, %1, @@ -786,10 +928,12 @@ i32); define @intrinsic_vmsltu_vx_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i8.i8( %0, i8 %1, @@ -806,10 +950,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i8.i8( %0, %1, @@ -826,10 +975,12 @@ i32); define @intrinsic_vmsltu_vx_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv16i8.i8( %0, i8 %1, @@ -846,10 +997,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv16i8.i8( %0, %1, @@ -866,10 +1022,12 @@ i32); define @intrinsic_vmsltu_vx_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv32i8.i8( %0, i8 %1, @@ -886,10 +1044,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv32i8.i8( %0, %1, @@ -906,10 +1069,12 @@ i32); define @intrinsic_vmsltu_vx_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i16.i16( %0, i16 %1, @@ -926,10 +1091,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i16.i16( %0, %1, @@ -946,10 +1116,12 @@ i32); define @intrinsic_vmsltu_vx_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i16.i16( %0, i16 %1, @@ -966,10 +1138,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i16.i16( %0, %1, @@ -986,10 +1163,12 @@ i32); define @intrinsic_vmsltu_vx_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i16.i16( %0, i16 %1, @@ -1006,10 +1185,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i16.i16( %0, %1, @@ -1026,10 +1210,12 @@ i32); define @intrinsic_vmsltu_vx_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i16.i16( %0, i16 %1, @@ -1046,10 +1232,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i16.i16( %0, %1, @@ -1066,10 +1257,12 @@ i32); define @intrinsic_vmsltu_vx_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv16i16.i16( %0, i16 %1, @@ -1086,10 +1279,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv16i16.i16( %0, %1, @@ -1106,10 +1304,12 @@ i32); define @intrinsic_vmsltu_vx_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i32.i32( %0, i32 %1, @@ -1126,10 +1326,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i32.i32( %0, %1, @@ -1146,10 +1351,12 @@ i32); define @intrinsic_vmsltu_vx_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i32.i32( %0, i32 %1, @@ -1166,10 +1373,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i32.i32( %0, %1, @@ -1186,10 +1398,12 @@ i32); define @intrinsic_vmsltu_vx_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i32.i32( %0, i32 %1, @@ -1206,10 +1420,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i32.i32( %0, %1, @@ -1226,10 +1445,12 @@ i32); define @intrinsic_vmsltu_vx_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1467,15 @@ i32); define @intrinsic_vmsltu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i32.i32( %0, %1, @@ -1261,10 +1487,12 @@ } define @intrinsic_vmsltu_vi_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -16 %a = call @llvm.riscv.vmsltu.nxv1i8.i8( %0, i8 -15, @@ -1274,10 +1502,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -15, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i8.i8( %0, %1, @@ -1289,10 +1520,12 @@ } define @intrinsic_vmsltu_vi_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -14 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -14 %a = call @llvm.riscv.vmsltu.nxv2i8.i8( %0, i8 -13, @@ -1302,10 +1535,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -13, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i8.i8( %0, %1, @@ -1317,10 +1553,12 @@ } define @intrinsic_vmsltu_vi_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -12 %a = call @llvm.riscv.vmsltu.nxv4i8.i8( %0, i8 -11, @@ -1330,10 +1568,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -11, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i8.i8( %0, %1, @@ -1345,10 +1586,12 @@ } define @intrinsic_vmsltu_vi_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -10 %a = call @llvm.riscv.vmsltu.nxv8i8.i8( %0, i8 -9, @@ -1358,10 +1601,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i8.i8( %0, %1, @@ -1373,10 +1619,12 @@ } define @intrinsic_vmsltu_vi_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -8 %a = call @llvm.riscv.vmsltu.nxv16i8.i8( %0, i8 -7, @@ -1386,10 +1634,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsleu.vi v10, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -7, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv16i8.i8( %0, %1, @@ -1401,10 +1652,12 @@ } define @intrinsic_vmsltu_vi_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -6 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -6 %a = call @llvm.riscv.vmsltu.nxv32i8.i8( %0, i8 -5, @@ -1414,10 +1667,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsleu.vi v12, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -5, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv32i8.i8( %0, %1, @@ -1429,10 +1685,12 @@ } define @intrinsic_vmsltu_vi_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -4 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -4 %a = call @llvm.riscv.vmsltu.nxv1i16.i16( %0, i16 -3, @@ -1442,10 +1700,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -3, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i16.i16( %0, %1, @@ -1457,10 +1718,12 @@ } define @intrinsic_vmsltu_vi_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -2 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -2 %a = call @llvm.riscv.vmsltu.nxv2i16.i16( %0, i16 -1, @@ -1470,10 +1733,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsne.vv v9, v8, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, [[REG:v[0-9]+]], [[REG]], v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i16.i16( %0, %1, @@ -1485,10 +1751,12 @@ } define @intrinsic_vmsltu_vi_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, [[REG:v[0-9]+]], [[REG]] %a = call @llvm.riscv.vmsltu.nxv4i16.i16( %0, i16 0, @@ -1498,10 +1766,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 0, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i16.i16( %0, %1, @@ -1513,10 +1784,12 @@ } define @intrinsic_vmsltu_vi_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 1 %a = call @llvm.riscv.vmsltu.nxv8i16.i16( %0, i16 2, @@ -1526,10 +1799,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsleu.vi v10, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 2, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i16.i16( %0, %1, @@ -1541,10 +1817,12 @@ } define @intrinsic_vmsltu_vi_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 3 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 3 %a = call @llvm.riscv.vmsltu.nxv16i16.i16( %0, i16 4, @@ -1554,10 +1832,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsleu.vi v12, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 4, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv16i16.i16( %0, %1, @@ -1569,10 +1850,12 @@ } define @intrinsic_vmsltu_vi_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 5 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 5 %a = call @llvm.riscv.vmsltu.nxv1i32.i32( %0, i32 6, @@ -1582,10 +1865,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 6, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i32.i32( %0, %1, @@ -1597,10 +1883,12 @@ } define @intrinsic_vmsltu_vi_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 7 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 7 %a = call @llvm.riscv.vmsltu.nxv2i32.i32( %0, i32 8, @@ -1610,10 +1898,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 8, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i32.i32( %0, %1, @@ -1625,10 +1916,12 @@ } define @intrinsic_vmsltu_vi_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsltu.nxv4i32.i32( %0, i32 10, @@ -1638,10 +1931,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsleu.vi v10, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 10, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i32.i32( %0, %1, @@ -1653,10 +1949,12 @@ } define @intrinsic_vmsltu_vi_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 11 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 11 %a = call @llvm.riscv.vmsltu.nxv8i32.i32( %0, i32 12, @@ -1666,10 +1964,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsleu.vi v12, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 12, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsltu.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmsltu_vv_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmsltu_vv_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmsltu_vv_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmsltu_vv_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmsltu_vv_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmsltu_vv_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmsltu_vv_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmsltu_vv_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmsltu_vv_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmsltu_vv_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmsltu_vv_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmsltu_vv_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i64); define @intrinsic_vmsltu_vv_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i64); define @intrinsic_vmsltu_vv_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i64); define @intrinsic_vmsltu_vv_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i64); define @intrinsic_vmsltu_vv_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i64( %0, %1, @@ -686,10 +809,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv1i64( %1, %2, @@ -710,10 +839,12 @@ i64); define @intrinsic_vmsltu_vv_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i64( %0, %1, @@ -730,10 +861,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv2i64( %1, %2, @@ -754,10 +891,12 @@ i64); define @intrinsic_vmsltu_vv_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i64( %0, %1, @@ -774,10 +913,16 @@ i64); define @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmsltu.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsltu.nxv4i64( %1, %2, @@ -798,10 +943,12 @@ i64); define @intrinsic_vmsltu_vx_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i8.i8( %0, i8 %1, @@ -818,10 +965,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i8.i8( %0, %1, @@ -838,10 +990,12 @@ i64); define @intrinsic_vmsltu_vx_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i8.i8( %0, i8 %1, @@ -858,10 +1012,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i8.i8( %0, %1, @@ -878,10 +1037,12 @@ i64); define @intrinsic_vmsltu_vx_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i8.i8( %0, i8 %1, @@ -898,10 +1059,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i8.i8( %0, %1, @@ -918,10 +1084,12 @@ i64); define @intrinsic_vmsltu_vx_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i8.i8( %0, i8 %1, @@ -938,10 +1106,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i8.i8( %0, %1, @@ -958,10 +1131,12 @@ i64); define @intrinsic_vmsltu_vx_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv16i8.i8( %0, i8 %1, @@ -978,10 +1153,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv16i8.i8( %0, %1, @@ -998,10 +1178,12 @@ i64); define @intrinsic_vmsltu_vx_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv32i8.i8( %0, i8 %1, @@ -1018,10 +1200,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv32i8.i8( %0, %1, @@ -1038,10 +1225,12 @@ i64); define @intrinsic_vmsltu_vx_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i16.i16( %0, i16 %1, @@ -1058,10 +1247,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i16.i16( %0, %1, @@ -1078,10 +1272,12 @@ i64); define @intrinsic_vmsltu_vx_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i16.i16( %0, i16 %1, @@ -1098,10 +1294,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i16.i16( %0, %1, @@ -1118,10 +1319,12 @@ i64); define @intrinsic_vmsltu_vx_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i16.i16( %0, i16 %1, @@ -1138,10 +1341,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i16.i16( %0, %1, @@ -1158,10 +1366,12 @@ i64); define @intrinsic_vmsltu_vx_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i16.i16( %0, i16 %1, @@ -1178,10 +1388,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i16.i16( %0, %1, @@ -1198,10 +1413,12 @@ i64); define @intrinsic_vmsltu_vx_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv16i16.i16( %0, i16 %1, @@ -1218,10 +1435,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv16i16.i16( %0, %1, @@ -1238,10 +1460,12 @@ i64); define @intrinsic_vmsltu_vx_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i32.i32( %0, i32 %1, @@ -1258,10 +1482,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i32.i32( %0, %1, @@ -1278,10 +1507,12 @@ i64); define @intrinsic_vmsltu_vx_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i32.i32( %0, i32 %1, @@ -1298,10 +1529,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i32.i32( %0, %1, @@ -1318,10 +1554,12 @@ i64); define @intrinsic_vmsltu_vx_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i32.i32( %0, i32 %1, @@ -1338,10 +1576,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i32.i32( %0, %1, @@ -1358,10 +1601,12 @@ i64); define @intrinsic_vmsltu_vx_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv8i32.i32( %0, i32 %1, @@ -1378,10 +1623,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i32.i32( %0, %1, @@ -1398,10 +1648,12 @@ i64); define @intrinsic_vmsltu_vx_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv1i64.i64( %0, i64 %1, @@ -1418,10 +1670,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i64.i64( %0, %1, @@ -1438,10 +1695,12 @@ i64); define @intrinsic_vmsltu_vx_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv2i64.i64( %0, i64 %1, @@ -1458,10 +1717,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i64.i64( %0, %1, @@ -1478,10 +1742,12 @@ i64); define @intrinsic_vmsltu_vx_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmsltu.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsltu.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1764,15 @@ i64); define @intrinsic_vmsltu_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsltu.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i64.i64( %0, %1, @@ -1513,10 +1784,12 @@ } define @intrinsic_vmsltu_vi_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -16 %a = call @llvm.riscv.vmsltu.nxv1i8.i8( %0, i8 -15, @@ -1526,10 +1799,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -15, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -15, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i8.i8( %0, %1, @@ -1541,10 +1817,12 @@ } define @intrinsic_vmsltu_vi_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -14 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -14 %a = call @llvm.riscv.vmsltu.nxv2i8.i8( %0, i8 -13, @@ -1554,10 +1832,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -13, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -13, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i8.i8( %0, %1, @@ -1569,10 +1850,12 @@ } define @intrinsic_vmsltu_vi_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -12 %a = call @llvm.riscv.vmsltu.nxv4i8.i8( %0, i8 -11, @@ -1582,10 +1865,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -11, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -11, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i8.i8( %0, %1, @@ -1597,10 +1883,12 @@ } define @intrinsic_vmsltu_vi_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -10 %a = call @llvm.riscv.vmsltu.nxv8i8.i8( %0, i8 -9, @@ -1610,10 +1898,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -9, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i8.i8( %0, %1, @@ -1625,10 +1916,12 @@ } define @intrinsic_vmsltu_vi_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -8 %a = call @llvm.riscv.vmsltu.nxv16i8.i8( %0, i8 -7, @@ -1638,10 +1931,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsleu.vi v10, v8, -7, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -7, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv16i8.i8( %0, %1, @@ -1653,10 +1949,12 @@ } define @intrinsic_vmsltu_vi_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -6 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -6 %a = call @llvm.riscv.vmsltu.nxv32i8.i8( %0, i8 -5, @@ -1666,10 +1964,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsleu.vi v12, v8, -5, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -5, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv32i8.i8( %0, %1, @@ -1681,10 +1982,12 @@ } define @intrinsic_vmsltu_vi_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -4 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -4 %a = call @llvm.riscv.vmsltu.nxv1i16.i16( %0, i16 -3, @@ -1694,10 +1997,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, -3, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -3, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i16.i16( %0, %1, @@ -1709,10 +2015,12 @@ } define @intrinsic_vmsltu_vi_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -2 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -2 %a = call @llvm.riscv.vmsltu.nxv2i16.i16( %0, i16 -1, @@ -1722,10 +2030,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsne.vv v9, v8, v8, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, [[REG:v[0-9]+]], [[REG]], v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i16.i16( %0, %1, @@ -1737,10 +2048,12 @@ } define @intrinsic_vmsltu_vi_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, [[REG:v[0-9]+]], [[REG]] %a = call @llvm.riscv.vmsltu.nxv4i16.i16( %0, i16 0, @@ -1750,10 +2063,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, 0, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 0, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i16.i16( %0, %1, @@ -1765,10 +2081,12 @@ } define @intrinsic_vmsltu_vi_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 1 %a = call @llvm.riscv.vmsltu.nxv8i16.i16( %0, i16 2, @@ -1778,10 +2096,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsleu.vi v10, v8, 2, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 2, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i16.i16( %0, %1, @@ -1793,10 +2114,12 @@ } define @intrinsic_vmsltu_vi_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 3 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 3 %a = call @llvm.riscv.vmsltu.nxv16i16.i16( %0, i16 4, @@ -1806,10 +2129,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsleu.vi v12, v8, 4, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 4, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv16i16.i16( %0, %1, @@ -1821,10 +2147,12 @@ } define @intrinsic_vmsltu_vi_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 5 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 5 %a = call @llvm.riscv.vmsltu.nxv1i32.i32( %0, i32 6, @@ -1834,10 +2162,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, 6, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 6, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i32.i32( %0, %1, @@ -1849,10 +2180,12 @@ } define @intrinsic_vmsltu_vi_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 7 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 7 %a = call @llvm.riscv.vmsltu.nxv2i32.i32( %0, i32 8, @@ -1862,10 +2195,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, 8, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 8, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i32.i32( %0, %1, @@ -1877,10 +2213,12 @@ } define @intrinsic_vmsltu_vi_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsltu.nxv4i32.i32( %0, i32 10, @@ -1890,10 +2228,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsleu.vi v10, v8, 10, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 10, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i32.i32( %0, %1, @@ -1905,10 +2246,12 @@ } define @intrinsic_vmsltu_vi_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 11 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 11 %a = call @llvm.riscv.vmsltu.nxv8i32.i32( %0, i32 12, @@ -1918,10 +2261,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsleu.vi v12, v8, 12, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 12, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv8i32.i32( %0, %1, @@ -1933,10 +2279,12 @@ } define @intrinsic_vmsltu_vi_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 13 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 13 %a = call @llvm.riscv.vmsltu.nxv1i64.i64( %0, i64 14, @@ -1946,10 +2294,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmsleu.vi v9, v8, 14, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 14, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv1i64.i64( %0, %1, @@ -1961,10 +2312,12 @@ } define @intrinsic_vmsltu_vi_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, 15 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 15 %a = call @llvm.riscv.vmsltu.nxv2i64.i64( %0, i64 16, @@ -1974,10 +2327,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmsleu.vi v10, v8, -16, v0.t +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -16, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv2i64.i64( %0, %1, @@ -1989,10 +2345,12 @@ } define @intrinsic_vmsltu_vi_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsleu.vi v0, v8, -15 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -15 %a = call @llvm.riscv.vmsltu.nxv4i64.i64( %0, i64 -14, @@ -2002,10 +2360,13 @@ } define @intrinsic_vmsltu_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmsleu.vi v12, v8, -14, v0.t +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsltu_mask_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, -14, v0.t %a = call @llvm.riscv.vmsltu.mask.nxv4i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsne.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmsne_vv_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i32); define @intrinsic_vmsne_vv_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i32); define @intrinsic_vmsne_vv_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i32); define @intrinsic_vmsne_vv_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i32); define @intrinsic_vmsne_vv_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i32); define @intrinsic_vmsne_vv_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i32); define @intrinsic_vmsne_vv_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i32); define @intrinsic_vmsne_vv_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i32); define @intrinsic_vmsne_vv_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i32); define @intrinsic_vmsne_vv_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i32); define @intrinsic_vmsne_vv_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i32); define @intrinsic_vmsne_vv_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i32); define @intrinsic_vmsne_vv_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i32); define @intrinsic_vmsne_vv_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i32); define @intrinsic_vmsne_vv_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i32); define @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i32); define @intrinsic_vmsne_vx_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i8.i8( %0, i8 %1, @@ -686,10 +809,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i8.i8( %0, %1, @@ -706,10 +834,12 @@ i32); define @intrinsic_vmsne_vx_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i8.i8( %0, i8 %1, @@ -726,10 +856,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i8.i8( %0, %1, @@ -746,10 +881,12 @@ i32); define @intrinsic_vmsne_vx_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i8.i8( %0, i8 %1, @@ -766,10 +903,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i8.i8( %0, %1, @@ -786,10 +928,12 @@ i32); define @intrinsic_vmsne_vx_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i8.i8( %0, i8 %1, @@ -806,10 +950,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i8.i8( %0, %1, @@ -826,10 +975,12 @@ i32); define @intrinsic_vmsne_vx_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv16i8.i8( %0, i8 %1, @@ -846,10 +997,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv16i8.i8( %0, %1, @@ -866,10 +1022,12 @@ i32); define @intrinsic_vmsne_vx_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv32i8.i8( %0, i8 %1, @@ -886,10 +1044,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv32i8.i8( %0, %1, @@ -906,10 +1069,12 @@ i32); define @intrinsic_vmsne_vx_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i16.i16( %0, i16 %1, @@ -926,10 +1091,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i16.i16( %0, %1, @@ -946,10 +1116,12 @@ i32); define @intrinsic_vmsne_vx_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i16.i16( %0, i16 %1, @@ -966,10 +1138,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i16.i16( %0, %1, @@ -986,10 +1163,12 @@ i32); define @intrinsic_vmsne_vx_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i16.i16( %0, i16 %1, @@ -1006,10 +1185,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i16.i16( %0, %1, @@ -1026,10 +1210,12 @@ i32); define @intrinsic_vmsne_vx_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i16.i16( %0, i16 %1, @@ -1046,10 +1232,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i16.i16( %0, %1, @@ -1066,10 +1257,12 @@ i32); define @intrinsic_vmsne_vx_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv16i16.i16( %0, i16 %1, @@ -1086,10 +1279,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv16i16.i16( %0, %1, @@ -1106,10 +1304,12 @@ i32); define @intrinsic_vmsne_vx_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i32.i32( %0, i32 %1, @@ -1126,10 +1326,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i32.i32( %0, %1, @@ -1146,10 +1351,12 @@ i32); define @intrinsic_vmsne_vx_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i32.i32( %0, i32 %1, @@ -1166,10 +1373,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i32.i32( %0, %1, @@ -1186,10 +1398,12 @@ i32); define @intrinsic_vmsne_vx_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i32.i32( %0, i32 %1, @@ -1206,10 +1420,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i32.i32( %0, %1, @@ -1226,10 +1445,12 @@ i32); define @intrinsic_vmsne_vx_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1467,15 @@ i32); define @intrinsic_vmsne_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i32.i32( %0, %1, @@ -1261,10 +1487,12 @@ } define @intrinsic_vmsne_vi_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv1i8.i8( %0, i8 9, @@ -1274,10 +1502,15 @@ } define @intrinsic_vmsne_mask_vi_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i8.i8( %0, %1, @@ -1289,10 +1522,12 @@ } define @intrinsic_vmsne_vi_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv2i8.i8( %0, i8 9, @@ -1302,10 +1537,15 @@ } define @intrinsic_vmsne_mask_vi_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i8.i8( %0, %1, @@ -1317,10 +1557,12 @@ } define @intrinsic_vmsne_vi_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv4i8.i8( %0, i8 9, @@ -1330,10 +1572,15 @@ } define @intrinsic_vmsne_mask_vi_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i8.i8( %0, %1, @@ -1345,10 +1592,12 @@ } define @intrinsic_vmsne_vi_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv8i8.i8( %0, i8 9, @@ -1358,10 +1607,15 @@ } define @intrinsic_vmsne_mask_vi_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i8.i8( %0, %1, @@ -1373,10 +1627,12 @@ } define @intrinsic_vmsne_vi_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv16i8.i8( %0, i8 9, @@ -1386,10 +1642,15 @@ } define @intrinsic_vmsne_mask_vi_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv16i8.i8( %0, %1, @@ -1401,10 +1662,12 @@ } define @intrinsic_vmsne_vi_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv32i8.i8( %0, i8 9, @@ -1414,10 +1677,15 @@ } define @intrinsic_vmsne_mask_vi_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv32i8.i8( %0, %1, @@ -1429,10 +1697,12 @@ } define @intrinsic_vmsne_vi_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv1i16.i16( %0, i16 9, @@ -1442,10 +1712,15 @@ } define @intrinsic_vmsne_mask_vi_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i16.i16( %0, %1, @@ -1457,10 +1732,12 @@ } define @intrinsic_vmsne_vi_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv2i16.i16( %0, i16 9, @@ -1470,10 +1747,15 @@ } define @intrinsic_vmsne_mask_vi_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i16.i16( %0, %1, @@ -1485,10 +1767,12 @@ } define @intrinsic_vmsne_vi_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv4i16.i16( %0, i16 9, @@ -1498,10 +1782,15 @@ } define @intrinsic_vmsne_mask_vi_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i16.i16( %0, %1, @@ -1513,10 +1802,12 @@ } define @intrinsic_vmsne_vi_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv8i16.i16( %0, i16 9, @@ -1526,10 +1817,15 @@ } define @intrinsic_vmsne_mask_vi_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i16.i16( %0, %1, @@ -1541,10 +1837,12 @@ } define @intrinsic_vmsne_vi_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv16i16.i16( %0, i16 9, @@ -1554,10 +1852,15 @@ } define @intrinsic_vmsne_mask_vi_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv16i16.i16( %0, %1, @@ -1569,10 +1872,12 @@ } define @intrinsic_vmsne_vi_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv1i32.i32( %0, i32 9, @@ -1582,10 +1887,15 @@ } define @intrinsic_vmsne_mask_vi_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i32.i32( %0, %1, @@ -1597,10 +1907,12 @@ } define @intrinsic_vmsne_vi_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv2i32.i32( %0, i32 9, @@ -1610,10 +1922,15 @@ } define @intrinsic_vmsne_mask_vi_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i32.i32( %0, %1, @@ -1625,10 +1942,12 @@ } define @intrinsic_vmsne_vi_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv4i32.i32( %0, i32 9, @@ -1638,10 +1957,15 @@ } define @intrinsic_vmsne_mask_vi_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i32.i32( %0, %1, @@ -1653,10 +1977,12 @@ } define @intrinsic_vmsne_vi_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv8i32.i32( %0, i32 9, @@ -1666,10 +1992,15 @@ } define @intrinsic_vmsne_mask_vi_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmsne.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmsne_vv_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i8( %0, %1, @@ -26,10 +29,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv1i8( %1, %2, @@ -50,10 +59,12 @@ i64); define @intrinsic_vmsne_vv_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i8( %0, %1, @@ -70,10 +81,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv2i8( %1, %2, @@ -94,10 +111,12 @@ i64); define @intrinsic_vmsne_vv_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i8( %0, %1, @@ -114,10 +133,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv4i8( %1, %2, @@ -138,10 +163,12 @@ i64); define @intrinsic_vmsne_vv_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i8( %0, %1, @@ -158,10 +185,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv8i8( %1, %2, @@ -182,10 +215,12 @@ i64); define @intrinsic_vmsne_vv_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv16i8( %0, %1, @@ -202,10 +237,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv16i8( %1, %2, @@ -226,10 +267,12 @@ i64); define @intrinsic_vmsne_vv_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv32i8( %0, %1, @@ -246,10 +289,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv32i8( %1, %2, @@ -270,10 +319,12 @@ i64); define @intrinsic_vmsne_vv_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i16( %0, %1, @@ -290,10 +341,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv1i16( %1, %2, @@ -314,10 +371,12 @@ i64); define @intrinsic_vmsne_vv_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i16( %0, %1, @@ -334,10 +393,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv2i16( %1, %2, @@ -358,10 +423,12 @@ i64); define @intrinsic_vmsne_vv_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i16( %0, %1, @@ -378,10 +445,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv4i16( %1, %2, @@ -402,10 +475,12 @@ i64); define @intrinsic_vmsne_vv_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i16( %0, %1, @@ -422,10 +497,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv8i16( %1, %2, @@ -446,10 +527,12 @@ i64); define @intrinsic_vmsne_vv_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv16i16( %0, %1, @@ -466,10 +549,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv16i16( %1, %2, @@ -490,10 +579,12 @@ i64); define @intrinsic_vmsne_vv_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i32( %0, %1, @@ -510,10 +601,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv1i32( %1, %2, @@ -534,10 +631,12 @@ i64); define @intrinsic_vmsne_vv_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i32( %0, %1, @@ -554,10 +653,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv2i32( %1, %2, @@ -578,10 +683,12 @@ i64); define @intrinsic_vmsne_vv_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i32( %0, %1, @@ -598,10 +705,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv4i32( %1, %2, @@ -622,10 +735,12 @@ i64); define @intrinsic_vmsne_vv_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i32( %0, %1, @@ -642,10 +757,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv8i32( %1, %2, @@ -666,10 +787,12 @@ i64); define @intrinsic_vmsne_vv_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i64( %0, %1, @@ -686,10 +809,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmsne.vv v25, v9, v10, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv1i64( %1, %2, @@ -710,10 +839,12 @@ i64); define @intrinsic_vmsne_vv_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i64( %0, %1, @@ -730,10 +861,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmsne.vv v25, v10, v12, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv2i64( %1, %2, @@ -754,10 +891,12 @@ i64); define @intrinsic_vmsne_vv_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i64( %0, %1, @@ -774,10 +913,16 @@ i64); define @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmsne.vv v25, v12, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %mask = call @llvm.riscv.vmsne.nxv4i64( %1, %2, @@ -798,10 +943,12 @@ i64); define @intrinsic_vmsne_vx_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i8.i8( %0, i8 %1, @@ -818,10 +965,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i8.i8( %0, %1, @@ -838,10 +990,12 @@ i64); define @intrinsic_vmsne_vx_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i8.i8( %0, i8 %1, @@ -858,10 +1012,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i8.i8( %0, %1, @@ -878,10 +1037,12 @@ i64); define @intrinsic_vmsne_vx_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i8.i8( %0, i8 %1, @@ -898,10 +1059,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i8.i8( %0, %1, @@ -918,10 +1084,12 @@ i64); define @intrinsic_vmsne_vx_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i8.i8( %0, i8 %1, @@ -938,10 +1106,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i8.i8( %0, %1, @@ -958,10 +1131,12 @@ i64); define @intrinsic_vmsne_vx_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv16i8.i8( %0, i8 %1, @@ -978,10 +1153,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv16i8.i8( %0, %1, @@ -998,10 +1178,12 @@ i64); define @intrinsic_vmsne_vx_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv32i8.i8( %0, i8 %1, @@ -1018,10 +1200,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv32i8.i8( %0, %1, @@ -1038,10 +1225,12 @@ i64); define @intrinsic_vmsne_vx_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i16.i16( %0, i16 %1, @@ -1058,10 +1247,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i16.i16( %0, %1, @@ -1078,10 +1272,12 @@ i64); define @intrinsic_vmsne_vx_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i16.i16( %0, i16 %1, @@ -1098,10 +1294,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i16.i16( %0, %1, @@ -1118,10 +1319,12 @@ i64); define @intrinsic_vmsne_vx_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i16.i16( %0, i16 %1, @@ -1138,10 +1341,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i16.i16( %0, %1, @@ -1158,10 +1366,12 @@ i64); define @intrinsic_vmsne_vx_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i16.i16( %0, i16 %1, @@ -1178,10 +1388,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i16.i16( %0, %1, @@ -1198,10 +1413,12 @@ i64); define @intrinsic_vmsne_vx_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv16i16.i16( %0, i16 %1, @@ -1218,10 +1435,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv16i16.i16( %0, %1, @@ -1238,10 +1460,12 @@ i64); define @intrinsic_vmsne_vx_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i32.i32( %0, i32 %1, @@ -1258,10 +1482,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i32.i32( %0, %1, @@ -1278,10 +1507,12 @@ i64); define @intrinsic_vmsne_vx_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i32.i32( %0, i32 %1, @@ -1298,10 +1529,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i32.i32( %0, %1, @@ -1318,10 +1554,12 @@ i64); define @intrinsic_vmsne_vx_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i32.i32( %0, i32 %1, @@ -1338,10 +1576,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i32.i32( %0, %1, @@ -1358,10 +1601,12 @@ i64); define @intrinsic_vmsne_vx_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv8i32.i32( %0, i32 %1, @@ -1378,10 +1623,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i32.i32( %0, %1, @@ -1398,10 +1648,12 @@ i64); define @intrinsic_vmsne_vx_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv1i64.i64( %0, i64 %1, @@ -1418,10 +1670,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i64.i64( %0, %1, @@ -1438,10 +1695,12 @@ i64); define @intrinsic_vmsne_vx_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv2i64.i64( %0, i64 %1, @@ -1458,10 +1717,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i64.i64( %0, %1, @@ -1478,10 +1742,12 @@ i64); define @intrinsic_vmsne_vx_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmsne.vx v0, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmsne.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1764,15 @@ i64); define @intrinsic_vmsne_mask_vx_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vx v25, v8, a0, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i64.i64( %0, %1, @@ -1513,10 +1784,12 @@ } define @intrinsic_vmsne_vi_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv1i8.i8( %0, i8 9, @@ -1526,10 +1799,15 @@ } define @intrinsic_vmsne_mask_vi_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i8.i8( %0, %1, @@ -1541,10 +1819,12 @@ } define @intrinsic_vmsne_vi_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv2i8.i8( %0, i8 9, @@ -1554,10 +1834,15 @@ } define @intrinsic_vmsne_mask_vi_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i8.i8( %0, %1, @@ -1569,10 +1854,12 @@ } define @intrinsic_vmsne_vi_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv4i8.i8( %0, i8 9, @@ -1582,10 +1869,15 @@ } define @intrinsic_vmsne_mask_vi_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i8.i8( %0, %1, @@ -1597,10 +1889,12 @@ } define @intrinsic_vmsne_vi_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv8i8.i8( %0, i8 9, @@ -1610,10 +1904,15 @@ } define @intrinsic_vmsne_mask_vi_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i8.i8( %0, %1, @@ -1625,10 +1924,12 @@ } define @intrinsic_vmsne_vi_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv16i8.i8( %0, i8 9, @@ -1638,10 +1939,15 @@ } define @intrinsic_vmsne_mask_vi_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv16i8.i8( %0, %1, @@ -1653,10 +1959,12 @@ } define @intrinsic_vmsne_vi_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv32i8.i8( %0, i8 9, @@ -1666,10 +1974,15 @@ } define @intrinsic_vmsne_mask_vi_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv32i8.i8( %0, %1, @@ -1681,10 +1994,12 @@ } define @intrinsic_vmsne_vi_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv1i16.i16( %0, i16 9, @@ -1694,10 +2009,15 @@ } define @intrinsic_vmsne_mask_vi_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i16.i16( %0, %1, @@ -1709,10 +2029,12 @@ } define @intrinsic_vmsne_vi_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv2i16.i16( %0, i16 9, @@ -1722,10 +2044,15 @@ } define @intrinsic_vmsne_mask_vi_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i16.i16( %0, %1, @@ -1737,10 +2064,12 @@ } define @intrinsic_vmsne_vi_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv4i16.i16( %0, i16 9, @@ -1750,10 +2079,15 @@ } define @intrinsic_vmsne_mask_vi_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i16.i16( %0, %1, @@ -1765,10 +2099,12 @@ } define @intrinsic_vmsne_vi_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv8i16.i16( %0, i16 9, @@ -1778,10 +2114,15 @@ } define @intrinsic_vmsne_mask_vi_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i16.i16( %0, %1, @@ -1793,10 +2134,12 @@ } define @intrinsic_vmsne_vi_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv16i16.i16( %0, i16 9, @@ -1806,10 +2149,15 @@ } define @intrinsic_vmsne_mask_vi_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv16i16.i16( %0, %1, @@ -1821,10 +2169,12 @@ } define @intrinsic_vmsne_vi_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv1i32.i32( %0, i32 9, @@ -1834,10 +2184,15 @@ } define @intrinsic_vmsne_mask_vi_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i32.i32( %0, %1, @@ -1849,10 +2204,12 @@ } define @intrinsic_vmsne_vi_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv2i32.i32( %0, i32 9, @@ -1862,10 +2219,15 @@ } define @intrinsic_vmsne_mask_vi_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i32.i32( %0, %1, @@ -1877,10 +2239,12 @@ } define @intrinsic_vmsne_vi_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv4i32.i32( %0, i32 9, @@ -1890,10 +2254,15 @@ } define @intrinsic_vmsne_mask_vi_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i32.i32( %0, %1, @@ -1905,10 +2274,12 @@ } define @intrinsic_vmsne_vi_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv8i32.i32( %0, i32 9, @@ -1918,10 +2289,15 @@ } define @intrinsic_vmsne_mask_vi_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv8i32.i32( %0, %1, @@ -1933,10 +2309,12 @@ } define @intrinsic_vmsne_vi_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv1i64.i64( %0, i64 9, @@ -1946,10 +2324,15 @@ } define @intrinsic_vmsne_mask_vi_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv1i64.i64( %0, %1, @@ -1961,10 +2344,12 @@ } define @intrinsic_vmsne_vi_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv2i64.i64( %0, i64 9, @@ -1974,10 +2359,15 @@ } define @intrinsic_vmsne_mask_vi_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmv1r.v v0, v10 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv2i64.i64( %0, %1, @@ -1989,10 +2379,12 @@ } define @intrinsic_vmsne_vi_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmsne.vi v0, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmsne.nxv4i64.i64( %0, i64 9, @@ -2002,10 +2394,15 @@ } define @intrinsic_vmsne_mask_vi_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmv1r.v v0, v12 +; CHECK-NEXT: vmsne.vi v25, v8, 9, v0.t +; CHECK-NEXT: vmv1r.v v0, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vmsne.mask.nxv4i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll @@ -30,8 +30,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -72,8 +72,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -114,8 +114,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -156,8 +156,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -198,8 +198,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -240,8 +240,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -282,8 +282,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll @@ -30,8 +30,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -72,8 +72,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -114,8 +114,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -156,8 +156,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -198,8 +198,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -240,8 +240,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: @@ -282,8 +282,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vmv1r.v v25, v0 ; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu -; CHECK-NEXT: vmv1r.v v0, v17 -; CHECK-NEXT: vmsof.m v25, v16, v0.t +; CHECK-NEXT: vmv1r.v v0, v9 +; CHECK-NEXT: vmsof.m v25, v8, v0.t ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmul.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vmul_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vmul_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vmul_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vmul_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vmul_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vmul_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vmul_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vmul_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vmul_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vmul_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vmul_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vmul_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vmul_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vmul_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vmul_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vmul_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vmul_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vmul_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmul.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vmul_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vmul_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vmul_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vmul_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vmul_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vmul_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vmul_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vmul_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vmul_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vmul_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vmul_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vmul_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vmul_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vmul_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vmul_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vmul_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vmul_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vmul_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vmul_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vmul_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vmul_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vmul_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmul.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmul_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmul.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmul_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vmul_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vmul_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vmul_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vmul_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vmul_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vmul_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vmul_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vmul_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v18 +; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vmul_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vmul_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v20 +; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vmul_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vmul_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmul_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vmul_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vmul_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vmul_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vmul_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vmul_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmul_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vmul_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vmul_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v18 +; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vmul_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vmul_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v20 +; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vmul_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vmul_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmul_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vmul_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vmul_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vmul_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vmul_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vmul_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vmul_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v18 +; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vmul_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vmul_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v20 +; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmul_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vmul_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmul_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vmul_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vmul_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -655,7 +652,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vmul.vv v16, v16, v25 +; CHECK-NEXT: vmul.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -668,7 +665,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -680,7 +677,7 @@ ; CHECK-LABEL: vmul_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v18 +; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -697,7 +694,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vmul.vv v16, v16, v26 +; CHECK-NEXT: vmul.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -710,7 +707,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -722,7 +719,7 @@ ; CHECK-LABEL: vmul_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v20 +; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -735,11 +732,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vmul.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vmul.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -752,7 +749,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -763,9 +760,8 @@ define @vmul_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmul_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -775,14 +771,14 @@ ; CHECK-LABEL: vmul_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmul.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -795,7 +791,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmul_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vmul_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vmul_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vmul_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vmul_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vmul_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vmul_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vmul_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vmul_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v18 +; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vmul_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vmul_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v20 +; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vmul_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vmul_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vmul_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vmul_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vmul_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vmul_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vmul_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vmul_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vmul_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vmul_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vmul_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v18 +; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vmul_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vmul_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v20 +; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vmul_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vmul_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vmul_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vmul_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vmul_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vmul_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vmul_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vmul_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vmul_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v18 +; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vmul_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vmul_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v20 +; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vmul_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vmul_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vmul_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vmul_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vmul_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v17 +; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -648,7 +645,7 @@ ; CHECK-LABEL: vmul_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -661,7 +658,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -673,7 +670,7 @@ ; CHECK-LABEL: vmul_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v18 +; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -683,7 +680,7 @@ ; CHECK-LABEL: vmul_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -696,7 +693,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -708,7 +705,7 @@ ; CHECK-LABEL: vmul_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmul.vv v16, v16, v20 +; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -718,7 +715,7 @@ ; CHECK-LABEL: vmul_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -731,7 +728,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -742,9 +739,8 @@ define @vmul_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vmul_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmul.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = mul %va, %vb ret %vc @@ -754,7 +750,7 @@ ; CHECK-LABEL: vmul_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -767,7 +763,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmul.vx v16, v16, a0 +; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmulh.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmulh.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmulh.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmulh.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmulh.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmulh.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vmulh.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmulh.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmulh.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmulh.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmulh.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmulh.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulh.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vmulh.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulh_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmulh.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulh.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmulhsu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vmulhsu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmulhsu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vmulhsu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmulhsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmulhsu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhsu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vmulhsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhsu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmulhsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhsu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmulhu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vmulhu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vmulhu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vmulhu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vmulhu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmulhu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vmulhu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmulhu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmulhu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vmulhu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vmulhu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmulhu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vmulhu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vmulhu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll @@ -7,7 +7,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv1i8( %0, i8 %1, i32 %2) @@ -20,7 +20,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv2i8( %0, i8 %1, i32 %2) @@ -33,7 +33,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv4i8( %0, i8 %1, i32 %2) @@ -46,7 +46,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv8i8( %0, i8 %1, i32 %2) @@ -59,7 +59,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv16i8( %0, i8 %1, i32 %2) @@ -72,7 +72,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv32i8( %0, i8 %1, i32 %2) @@ -85,7 +85,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv64i8( %0, i8 %1, i32 %2) @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv1i16( %0, i16 %1, i32 %2) @@ -111,7 +111,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv2i16( %0, i16 %1, i32 %2) @@ -124,7 +124,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv4i16( %0, i16 %1, i32 %2) @@ -137,7 +137,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv8i16( %0, i16 %1, i32 %2) @@ -150,7 +150,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv16i16( %0, i16 %1, i32 %2) @@ -163,7 +163,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv32i16( %0, i16 %1, i32 %2) @@ -176,7 +176,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv1i32( %0, i32 %1, i32 %2) @@ -189,7 +189,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv2i32( %0, i32 %1, i32 %2) @@ -202,7 +202,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv4i32( %0, i32 %1, i32 %2) @@ -215,7 +215,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv8i32( %0, i32 %1, i32 %2) @@ -228,7 +228,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv16i32( %0, i32 %1, i32 %2) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll @@ -7,7 +7,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv1i8( %0, i8 %1, i64 %2) @@ -20,7 +20,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv2i8( %0, i8 %1, i64 %2) @@ -33,7 +33,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv4i8( %0, i8 %1, i64 %2) @@ -46,7 +46,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv8i8( %0, i8 %1, i64 %2) @@ -59,7 +59,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv16i8( %0, i8 %1, i64 %2) @@ -72,7 +72,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv32i8( %0, i8 %1, i64 %2) @@ -85,7 +85,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv64i8( %0, i8 %1, i64 %2) @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv1i16( %0, i16 %1, i64 %2) @@ -111,7 +111,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv2i16( %0, i16 %1, i64 %2) @@ -124,7 +124,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv4i16( %0, i16 %1, i64 %2) @@ -137,7 +137,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv8i16( %0, i16 %1, i64 %2) @@ -150,7 +150,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv16i16( %0, i16 %1, i64 %2) @@ -163,7 +163,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv32i16( %0, i16 %1, i64 %2) @@ -176,7 +176,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv1i32( %0, i32 %1, i64 %2) @@ -189,7 +189,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv2i32( %0, i32 %1, i64 %2) @@ -202,7 +202,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv4i32( %0, i32 %1, i64 %2) @@ -215,7 +215,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv8i32( %0, i32 %1, i64 %2) @@ -228,7 +228,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv16i32( %0, i32 %1, i64 %2) @@ -241,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv1i64( %0, i64 %1, i64 %2) @@ -254,7 +254,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv2i64( %0, i64 %1, i64 %2) @@ -267,7 +267,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv4i64( %0, i64 %1, i64 %2) @@ -280,7 +280,7 @@ ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vmv.s.x v16, a0 +; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vmv.s.x.nxv8i64( %0, i64 %1, i64 %2) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmv.v.v.nxv1i8( @@ -5,10 +6,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1i8( %0, i32 %1) @@ -21,10 +24,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv2i8_nxv2i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2i8( %0, i32 %1) @@ -37,10 +42,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv4i8_nxv4i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4i8( %0, i32 %1) @@ -53,10 +60,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv8i8_nxv8i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a0, e8,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8i8( %0, i32 %1) @@ -69,10 +78,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv16i8_nxv16i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a0, e8,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16i8( %0, i32 %1) @@ -85,10 +96,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv32i8_nxv32i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a0, e8,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv32i8( %0, i32 %1) @@ -101,10 +114,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv64i8_nxv64i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a0, e8,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv64i8( %0, i32 %1) @@ -117,10 +132,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv1i16_nxv1i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1i16( %0, i32 %1) @@ -133,10 +150,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv2i16_nxv2i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2i16( %0, i32 %1) @@ -149,10 +168,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv4i16_nxv4i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a0, e16,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4i16( %0, i32 %1) @@ -165,10 +186,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv8i16_nxv8i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a0, e16,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8i16( %0, i32 %1) @@ -181,10 +204,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv16i16_nxv16i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a0, e16,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16i16( %0, i32 %1) @@ -197,10 +222,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv32i16_nxv32i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a0, e16,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv32i16( %0, i32 %1) @@ -213,10 +240,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv1i32_nxv1i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1i32( %0, i32 %1) @@ -229,10 +258,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv2i32_nxv2i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a0, e32,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2i32( %0, i32 %1) @@ -245,10 +276,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv4i32_nxv4i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a0, e32,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4i32( %0, i32 %1) @@ -261,10 +294,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv8i32_nxv8i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a0, e32,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8i32( %0, i32 %1) @@ -277,10 +312,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv16i32_nxv16i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a0, e32,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16i32( %0, i32 %1) @@ -293,10 +330,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv1i64_nxv1i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, a0, e64,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1i64( %0, i32 %1) @@ -309,10 +348,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv2i64_nxv2i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, a0, e64,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2i64( %0, i32 %1) @@ -325,10 +366,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv4i64_nxv4i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, a0, e64,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4i64( %0, i32 %1) @@ -341,10 +384,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv8i64_nxv8i64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, a0, e64,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8i64( %0, i32 %1) @@ -357,10 +402,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv1f16_nxv1f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1f16( %0, i32 %1) @@ -373,10 +420,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv2f16_nxv2f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2f16( %0, i32 %1) @@ -389,10 +438,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv4f16_nxv4f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a0, e16,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4f16( %0, i32 %1) @@ -405,10 +456,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv8f16_nxv8f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a0, e16,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8f16( %0, i32 %1) @@ -421,10 +474,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv16f16_nxv16f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a0, e16,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16f16( %0, i32 %1) @@ -437,10 +492,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv32f16_nxv32f16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a0, e16,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv32f16( %0, i32 %1) @@ -453,10 +510,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1f32( %0, i32 %1) @@ -469,10 +528,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv2f32_nxv2f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a0, e32,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2f32( %0, i32 %1) @@ -485,10 +546,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv4f32_nxv4f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a0, e32,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4f32( %0, i32 %1) @@ -501,10 +564,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv8f32_nxv8f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a0, e32,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8f32( %0, i32 %1) @@ -517,10 +582,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv16f32_nxv16f32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a0, e32,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16f32( %0, i32 %1) @@ -533,10 +600,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv1f64_nxv1f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, a0, e64,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1f64( %0, i32 %1) @@ -549,10 +618,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv2f64_nxv2f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, a0, e64,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2f64( %0, i32 %1) @@ -565,10 +636,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv4f64_nxv4f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, a0, e64,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4f64( %0, i32 %1) @@ -581,10 +654,12 @@ i32); define @intrinsic_vmv.v.v_v_nxv8f64_nxv8f64( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, a0, e64,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8f64( %0, i32 %1) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmv.v.v.nxv1i8( @@ -5,10 +6,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1i8( %0, i64 %1) @@ -21,10 +24,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv2i8_nxv2i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2i8( %0, i64 %1) @@ -37,10 +42,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv4i8_nxv4i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4i8( %0, i64 %1) @@ -53,10 +60,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv8i8_nxv8i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a0, e8,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8i8( %0, i64 %1) @@ -69,10 +78,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv16i8_nxv16i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a0, e8,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16i8( %0, i64 %1) @@ -85,10 +96,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv32i8_nxv32i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a0, e8,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv32i8( %0, i64 %1) @@ -101,10 +114,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv64i8_nxv64i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a0, e8,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv64i8( %0, i64 %1) @@ -117,10 +132,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv1i16_nxv1i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1i16( %0, i64 %1) @@ -133,10 +150,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv2i16_nxv2i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2i16( %0, i64 %1) @@ -149,10 +168,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv4i16_nxv4i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a0, e16,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4i16( %0, i64 %1) @@ -165,10 +186,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv8i16_nxv8i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a0, e16,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8i16( %0, i64 %1) @@ -181,10 +204,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv16i16_nxv16i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a0, e16,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16i16( %0, i64 %1) @@ -197,10 +222,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv32i16_nxv32i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a0, e16,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv32i16( %0, i64 %1) @@ -213,10 +240,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv1i32_nxv1i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1i32( %0, i64 %1) @@ -229,10 +258,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv2i32_nxv2i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a0, e32,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2i32( %0, i64 %1) @@ -245,10 +276,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv4i32_nxv4i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a0, e32,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4i32( %0, i64 %1) @@ -261,10 +294,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv8i32_nxv8i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a0, e32,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8i32( %0, i64 %1) @@ -277,10 +312,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv16i32_nxv16i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a0, e32,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16i32( %0, i64 %1) @@ -293,10 +330,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv1i64_nxv1i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, a0, e64,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1i64( %0, i64 %1) @@ -309,10 +348,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv2i64_nxv2i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, a0, e64,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2i64( %0, i64 %1) @@ -325,10 +366,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv4i64_nxv4i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, a0, e64,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4i64( %0, i64 %1) @@ -341,10 +384,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv8i64_nxv8i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, a0, e64,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8i64( %0, i64 %1) @@ -357,10 +402,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv1f16_nxv1f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1f16( %0, i64 %1) @@ -373,10 +420,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv2f16_nxv2f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2f16( %0, i64 %1) @@ -389,10 +438,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv4f16_nxv4f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a0, e16,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4f16( %0, i64 %1) @@ -405,10 +456,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv8f16_nxv8f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a0, e16,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8f16( %0, i64 %1) @@ -421,10 +474,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv16f16_nxv16f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a0, e16,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16f16( %0, i64 %1) @@ -437,10 +492,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv32f16_nxv32f16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a0, e16,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv32f16( %0, i64 %1) @@ -453,10 +510,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1f32( %0, i64 %1) @@ -469,10 +528,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv2f32_nxv2f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a0, e32,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2f32( %0, i64 %1) @@ -485,10 +546,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv4f32_nxv4f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a0, e32,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4f32( %0, i64 %1) @@ -501,10 +564,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv8f32_nxv8f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a0, e32,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8f32( %0, i64 %1) @@ -517,10 +582,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv16f32_nxv16f32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a0, e32,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv16f32( %0, i64 %1) @@ -533,10 +600,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv1f64_nxv1f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, a0, e64,m1 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv1f64( %0, i64 %1) @@ -549,10 +618,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv2f64_nxv2f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, a0, e64,m2 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv2f64( %0, i64 %1) @@ -565,10 +636,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv4f64_nxv4f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, a0, e64,m4 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv4f64( %0, i64 %1) @@ -581,10 +654,12 @@ i64); define @intrinsic_vmv.v.v_v_nxv8f64_nxv8f64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.v v8, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, a0, e64,m8 -; CHECK: vmv.v.v {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmv.v.v.nxv8f64( %0, i64 %1) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmv.v.x.nxv1i8( @@ -5,10 +6,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv1i8(i8 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8 -; CHECK: vsetvli {{.*}}, a1, e8,mf8 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv1i8( i8 %0, i32 %1) @@ -21,10 +24,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv2i8(i8 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8 -; CHECK: vsetvli {{.*}}, a1, e8,mf4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv2i8( i8 %0, i32 %1) @@ -37,10 +42,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv4i8(i8 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8 -; CHECK: vsetvli {{.*}}, a1, e8,mf2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv4i8( i8 %0, i32 %1) @@ -53,10 +60,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv8i8(i8 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8 -; CHECK: vsetvli {{.*}}, a1, e8,m1 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv8i8( i8 %0, i32 %1) @@ -69,10 +78,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv16i8(i8 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8 -; CHECK: vsetvli {{.*}}, a1, e8,m2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv16i8( i8 %0, i32 %1) @@ -85,10 +96,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv32i8(i8 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8 -; CHECK: vsetvli {{.*}}, a1, e8,m4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv32i8( i8 %0, i32 %1) @@ -101,10 +114,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv64i8(i8 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8 -; CHECK: vsetvli {{.*}}, a1, e8,m8 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv64i8( i8 %0, i32 %1) @@ -117,10 +132,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv1i16(i16 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16 -; CHECK: vsetvli {{.*}}, a1, e16,mf4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv1i16( i16 %0, i32 %1) @@ -133,10 +150,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv2i16(i16 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16 -; CHECK: vsetvli {{.*}}, a1, e16,mf2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv2i16( i16 %0, i32 %1) @@ -149,10 +168,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv4i16(i16 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16 -; CHECK: vsetvli {{.*}}, a1, e16,m1 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv4i16( i16 %0, i32 %1) @@ -165,10 +186,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv8i16(i16 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16 -; CHECK: vsetvli {{.*}}, a1, e16,m2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv8i16( i16 %0, i32 %1) @@ -181,10 +204,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv16i16(i16 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16 -; CHECK: vsetvli {{.*}}, a1, e16,m4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv16i16( i16 %0, i32 %1) @@ -197,10 +222,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv32i16(i16 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16 -; CHECK: vsetvli {{.*}}, a1, e16,m8 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv32i16( i16 %0, i32 %1) @@ -213,10 +240,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv1i32(i32 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32 -; CHECK: vsetvli {{.*}}, a1, e32,mf2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv1i32( i32 %0, i32 %1) @@ -229,10 +258,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv2i32(i32 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32 -; CHECK: vsetvli {{.*}}, a1, e32,m1 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv2i32( i32 %0, i32 %1) @@ -245,10 +276,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv4i32(i32 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32 -; CHECK: vsetvli {{.*}}, a1, e32,m2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv4i32( i32 %0, i32 %1) @@ -261,10 +294,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv8i32(i32 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32 -; CHECK: vsetvli {{.*}}, a1, e32,m4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv8i32( i32 %0, i32 %1) @@ -277,10 +312,12 @@ i32); define @intrinsic_vmv.v.x_x_nxv16i32(i32 %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32 -; CHECK: vsetvli {{.*}}, a1, e32,m8 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv16i32( i32 %0, i32 %1) @@ -289,10 +326,12 @@ } define @intrinsic_vmv.v.x_i_nxv1i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf8 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv1i8( i8 9, i32 %0) @@ -301,10 +340,12 @@ } define @intrinsic_vmv.v.x_i_nxv2i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv2i8( i8 9, i32 %0) @@ -313,10 +354,12 @@ } define @intrinsic_vmv.v.x_i_nxv4i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv4i8( i8 9, i32 %0) @@ -325,10 +368,12 @@ } define @intrinsic_vmv.v.x_i_nxv8i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8 -; CHECK: vsetvli {{.*}}, a0, e8,m1 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv8i8( i8 9, i32 %0) @@ -337,10 +382,12 @@ } define @intrinsic_vmv.v.x_i_nxv16i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8 -; CHECK: vsetvli {{.*}}, a0, e8,m2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv16i8( i8 9, i32 %0) @@ -349,10 +396,12 @@ } define @intrinsic_vmv.v.x_i_nxv32i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8 -; CHECK: vsetvli {{.*}}, a0, e8,m4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv32i8( i8 9, i32 %0) @@ -361,10 +410,12 @@ } define @intrinsic_vmv.v.x_i_nxv64i8(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8 -; CHECK: vsetvli {{.*}}, a0, e8,m8 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv64i8( i8 9, i32 %0) @@ -373,10 +424,12 @@ } define @intrinsic_vmv.v.x_i_nxv1i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv1i16( i16 9, i32 %0) @@ -385,10 +438,12 @@ } define @intrinsic_vmv.v.x_i_nxv2i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv2i16( i16 9, i32 %0) @@ -397,10 +452,12 @@ } define @intrinsic_vmv.v.x_i_nxv4i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16 -; CHECK: vsetvli {{.*}}, a0, e16,m1 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv4i16( i16 9, i32 %0) @@ -409,10 +466,12 @@ } define @intrinsic_vmv.v.x_i_nxv8i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16 -; CHECK: vsetvli {{.*}}, a0, e16,m2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv8i16( i16 9, i32 %0) @@ -421,10 +480,12 @@ } define @intrinsic_vmv.v.x_i_nxv16i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16 -; CHECK: vsetvli {{.*}}, a0, e16,m4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv16i16( i16 9, i32 %0) @@ -433,10 +494,12 @@ } define @intrinsic_vmv.v.x_i_nxv32i16(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16 -; CHECK: vsetvli {{.*}}, a0, e16,m8 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv32i16( i16 9, i32 %0) @@ -445,10 +508,12 @@ } define @intrinsic_vmv.v.x_i_nxv1i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv1i32( i32 9, i32 %0) @@ -457,10 +522,12 @@ } define @intrinsic_vmv.v.x_i_nxv2i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32 -; CHECK: vsetvli {{.*}}, a0, e32,m1 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv2i32( i32 9, i32 %0) @@ -469,10 +536,12 @@ } define @intrinsic_vmv.v.x_i_nxv4i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32 -; CHECK: vsetvli {{.*}}, a0, e32,m2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv4i32( i32 9, i32 %0) @@ -481,10 +550,12 @@ } define @intrinsic_vmv.v.x_i_nxv8i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32 -; CHECK: vsetvli {{.*}}, a0, e32,m4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv8i32( i32 9, i32 %0) @@ -493,10 +564,12 @@ } define @intrinsic_vmv.v.x_i_nxv16i32(i32 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32 -; CHECK: vsetvli {{.*}}, a0, e32,m8 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv16i32( i32 9, i32 %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmv.v.x.nxv1i8( @@ -5,10 +6,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv1i8(i8 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8 -; CHECK: vsetvli {{.*}}, a1, e8,mf8 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv1i8( i8 %0, i64 %1) @@ -21,10 +24,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv2i8(i8 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8 -; CHECK: vsetvli {{.*}}, a1, e8,mf4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv2i8( i8 %0, i64 %1) @@ -37,10 +42,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv4i8(i8 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8 -; CHECK: vsetvli {{.*}}, a1, e8,mf2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv4i8( i8 %0, i64 %1) @@ -53,10 +60,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv8i8(i8 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8 -; CHECK: vsetvli {{.*}}, a1, e8,m1 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv8i8( i8 %0, i64 %1) @@ -69,10 +78,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv16i8(i8 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8 -; CHECK: vsetvli {{.*}}, a1, e8,m2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv16i8( i8 %0, i64 %1) @@ -85,10 +96,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv32i8(i8 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8 -; CHECK: vsetvli {{.*}}, a1, e8,m4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv32i8( i8 %0, i64 %1) @@ -101,10 +114,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv64i8(i8 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8 -; CHECK: vsetvli {{.*}}, a1, e8,m8 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv64i8( i8 %0, i64 %1) @@ -117,10 +132,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv1i16(i16 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16 -; CHECK: vsetvli {{.*}}, a1, e16,mf4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv1i16( i16 %0, i64 %1) @@ -133,10 +150,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv2i16(i16 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16 -; CHECK: vsetvli {{.*}}, a1, e16,mf2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv2i16( i16 %0, i64 %1) @@ -149,10 +168,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv4i16(i16 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16 -; CHECK: vsetvli {{.*}}, a1, e16,m1 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv4i16( i16 %0, i64 %1) @@ -165,10 +186,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv8i16(i16 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16 -; CHECK: vsetvli {{.*}}, a1, e16,m2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv8i16( i16 %0, i64 %1) @@ -181,10 +204,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv16i16(i16 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16 -; CHECK: vsetvli {{.*}}, a1, e16,m4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv16i16( i16 %0, i64 %1) @@ -197,10 +222,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv32i16(i16 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16 -; CHECK: vsetvli {{.*}}, a1, e16,m8 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv32i16( i16 %0, i64 %1) @@ -213,10 +240,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv1i32(i32 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32 -; CHECK: vsetvli {{.*}}, a1, e32,mf2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv1i32( i32 %0, i64 %1) @@ -229,10 +258,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv2i32(i32 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32 -; CHECK: vsetvli {{.*}}, a1, e32,m1 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv2i32( i32 %0, i64 %1) @@ -245,10 +276,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv4i32(i32 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32 -; CHECK: vsetvli {{.*}}, a1, e32,m2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv4i32( i32 %0, i64 %1) @@ -261,10 +294,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv8i32(i32 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32 -; CHECK: vsetvli {{.*}}, a1, e32,m4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv8i32( i32 %0, i64 %1) @@ -277,10 +312,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv16i32(i32 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32 -; CHECK: vsetvli {{.*}}, a1, e32,m8 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv16i32( i32 %0, i64 %1) @@ -293,10 +330,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv1i64(i64 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64 -; CHECK: vsetvli {{.*}}, a1, e64,m1 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv1i64( i64 %0, i64 %1) @@ -309,10 +348,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv2i64(i64 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64 -; CHECK: vsetvli {{.*}}, a1, e64,m2 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv2i64( i64 %0, i64 %1) @@ -325,10 +366,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv4i64(i64 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64 -; CHECK: vsetvli {{.*}}, a1, e64,m4 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv4i64( i64 %0, i64 %1) @@ -341,10 +384,12 @@ i64); define @intrinsic_vmv.v.x_x_nxv8i64(i64 %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.x v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64 -; CHECK: vsetvli {{.*}}, a1, e64,m8 -; CHECK: vmv.v.x {{v[0-9]+}}, a0 %a = call @llvm.riscv.vmv.v.x.nxv8i64( i64 %0, i64 %1) @@ -353,10 +398,12 @@ } define @intrinsic_vmv.v.x_i_nxv1i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf8 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv1i8( i8 9, i64 %0) @@ -365,10 +412,12 @@ } define @intrinsic_vmv.v.x_i_nxv2i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv2i8( i8 9, i64 %0) @@ -377,10 +426,12 @@ } define @intrinsic_vmv.v.x_i_nxv4i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8 -; CHECK: vsetvli {{.*}}, a0, e8,mf2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv4i8( i8 9, i64 %0) @@ -389,10 +440,12 @@ } define @intrinsic_vmv.v.x_i_nxv8i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8 -; CHECK: vsetvli {{.*}}, a0, e8,m1 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv8i8( i8 9, i64 %0) @@ -401,10 +454,12 @@ } define @intrinsic_vmv.v.x_i_nxv16i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8 -; CHECK: vsetvli {{.*}}, a0, e8,m2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv16i8( i8 9, i64 %0) @@ -413,10 +468,12 @@ } define @intrinsic_vmv.v.x_i_nxv32i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8 -; CHECK: vsetvli {{.*}}, a0, e8,m4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv32i8( i8 9, i64 %0) @@ -425,10 +482,12 @@ } define @intrinsic_vmv.v.x_i_nxv64i8(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8 -; CHECK: vsetvli {{.*}}, a0, e8,m8 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv64i8( i8 9, i64 %0) @@ -437,10 +496,12 @@ } define @intrinsic_vmv.v.x_i_nxv1i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv1i16( i16 9, i64 %0) @@ -449,10 +510,12 @@ } define @intrinsic_vmv.v.x_i_nxv2i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16 -; CHECK: vsetvli {{.*}}, a0, e16,mf2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv2i16( i16 9, i64 %0) @@ -461,10 +524,12 @@ } define @intrinsic_vmv.v.x_i_nxv4i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16 -; CHECK: vsetvli {{.*}}, a0, e16,m1 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv4i16( i16 9, i64 %0) @@ -473,10 +538,12 @@ } define @intrinsic_vmv.v.x_i_nxv8i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16 -; CHECK: vsetvli {{.*}}, a0, e16,m2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv8i16( i16 9, i64 %0) @@ -485,10 +552,12 @@ } define @intrinsic_vmv.v.x_i_nxv16i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16 -; CHECK: vsetvli {{.*}}, a0, e16,m4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv16i16( i16 9, i64 %0) @@ -497,10 +566,12 @@ } define @intrinsic_vmv.v.x_i_nxv32i16(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16 -; CHECK: vsetvli {{.*}}, a0, e16,m8 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv32i16( i16 9, i64 %0) @@ -509,10 +580,12 @@ } define @intrinsic_vmv.v.x_i_nxv1i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32 -; CHECK: vsetvli {{.*}}, a0, e32,mf2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv1i32( i32 9, i64 %0) @@ -521,10 +594,12 @@ } define @intrinsic_vmv.v.x_i_nxv2i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32 -; CHECK: vsetvli {{.*}}, a0, e32,m1 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv2i32( i32 9, i64 %0) @@ -533,10 +608,12 @@ } define @intrinsic_vmv.v.x_i_nxv4i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32 -; CHECK: vsetvli {{.*}}, a0, e32,m2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv4i32( i32 9, i64 %0) @@ -545,10 +622,12 @@ } define @intrinsic_vmv.v.x_i_nxv8i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32 -; CHECK: vsetvli {{.*}}, a0, e32,m4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv8i32( i32 9, i64 %0) @@ -557,10 +636,12 @@ } define @intrinsic_vmv.v.x_i_nxv16i32(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32 -; CHECK: vsetvli {{.*}}, a0, e32,m8 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv16i32( i32 9, i64 %0) @@ -569,10 +650,12 @@ } define @intrinsic_vmv.v.x_i_nxv1i64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64 -; CHECK: vsetvli {{.*}}, a0, e64,m1 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv1i64( i64 9, i64 %0) @@ -581,10 +664,12 @@ } define @intrinsic_vmv.v.x_i_nxv2i64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64 -; CHECK: vsetvli {{.*}}, a0, e64,m2 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv2i64( i64 9, i64 %0) @@ -593,10 +678,12 @@ } define @intrinsic_vmv.v.x_i_nxv4i64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64 -; CHECK: vsetvli {{.*}}, a0, e64,m4 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv4i64( i64 9, i64 %0) @@ -605,10 +692,12 @@ } define @intrinsic_vmv.v.x_i_nxv8i64(i64 %0) nounwind { +; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vmv.v.i v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64 -; CHECK: vsetvli {{.*}}, a0, e64,m8 -; CHECK: vmv.v.i {{v[0-9]+}}, 9 %a = call @llvm.riscv.vmv.v.x.nxv8i64( i64 9, i64 %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll @@ -7,7 +7,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv1i8( %0) @@ -20,7 +20,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv2i8( %0) @@ -33,7 +33,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv4i8( %0) @@ -46,7 +46,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,m1,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv8i8( %0) @@ -59,7 +59,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,m2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv16i8( %0) @@ -72,7 +72,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,m4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv32i8( %0) @@ -85,7 +85,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,m8,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv64i8( %0) @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv1i16( %0) @@ -111,7 +111,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv2i16( %0) @@ -124,7 +124,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv4i16( %0) @@ -137,7 +137,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv8i16( %0) @@ -150,7 +150,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv16i16( %0) @@ -163,7 +163,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv32i16( %0) @@ -176,7 +176,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv1i32( %0) @@ -189,7 +189,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv2i32( %0) @@ -202,7 +202,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv4i32( %0) @@ -215,7 +215,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv8i32( %0) @@ -228,7 +228,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m8,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv16i32( %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll @@ -7,7 +7,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv1i8( %0) @@ -20,7 +20,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv2i8( %0) @@ -33,7 +33,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv4i8( %0) @@ -46,7 +46,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,m1,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv8i8( %0) @@ -59,7 +59,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,m2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv16i8( %0) @@ -72,7 +72,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,m4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv32i8( %0) @@ -85,7 +85,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv64i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e8,m8,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i8 @llvm.riscv.vmv.x.s.nxv64i8( %0) @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv1i16( %0) @@ -111,7 +111,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv2i16( %0) @@ -124,7 +124,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv4i16( %0) @@ -137,7 +137,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv8i16( %0) @@ -150,7 +150,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv16i16( %0) @@ -163,7 +163,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e16,m8,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i16 @llvm.riscv.vmv.x.s.nxv32i16( %0) @@ -176,7 +176,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv1i32( %0) @@ -189,7 +189,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv2i32( %0) @@ -202,7 +202,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv4i32( %0) @@ -215,7 +215,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv8i32( %0) @@ -228,7 +228,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e32,m8,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i32 @llvm.riscv.vmv.x.s.nxv16i32( %0) @@ -241,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vmv.x.s.nxv1i64( %0) @@ -254,7 +254,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e64,m2,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vmv.x.s.nxv2i64( %0) @@ -267,7 +267,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e64,m4,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vmv.x.s.nxv4i64( %0) @@ -280,7 +280,7 @@ ; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli zero, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.x.s a0, v16 +; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret entry: %a = call i64 @llvm.riscv.vmv.x.s.nxv8i64( %0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmxnor.nxv1i1( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmxnor_mm_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmxnor_mm_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmxnor_mm_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmxnor_mm_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmxnor_mm_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmxnor_mm_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmxnor_mm_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmxnor.nxv1i1( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmxnor_mm_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmxnor_mm_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmxnor_mm_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmxnor_mm_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmxnor_mm_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmxnor_mm_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmxnor_mm_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmxnor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxnor.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmxor.nxv1i1( @@ -6,10 +7,12 @@ i32); define @intrinsic_vmxor_mm_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i32); define @intrinsic_vmxor_mm_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i32); define @intrinsic_vmxor_mm_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i32); define @intrinsic_vmxor_mm_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i32); define @intrinsic_vmxor_mm_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i32); define @intrinsic_vmxor_mm_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i32); define @intrinsic_vmxor_mm_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vmxor.nxv1i1( @@ -6,10 +7,12 @@ i64); define @intrinsic_vmxor_mm_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv1i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv1i1( %0, %1, @@ -24,10 +27,12 @@ i64); define @intrinsic_vmxor_mm_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv2i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv2i1( %0, %1, @@ -42,10 +47,12 @@ i64); define @intrinsic_vmxor_mm_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv4i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv4i1( %0, %1, @@ -60,10 +67,12 @@ i64); define @intrinsic_vmxor_mm_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv8i1( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vmxor_mm_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv16i1( %0, %1, @@ -96,10 +107,12 @@ i64); define @intrinsic_vmxor_mm_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv32i1( %0, %1, @@ -114,10 +127,12 @@ i64); define @intrinsic_vmxor_mm_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmxor.mm v0, v0, v8 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vmxor.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnclip.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnclip.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnclip.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnclip.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vnclip.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vnclip.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vnclip.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vnclip.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -881,10 +992,13 @@ } define @intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( %0, i8 9, @@ -894,10 +1008,12 @@ } define @intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -909,10 +1025,13 @@ } define @intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( %0, i8 9, @@ -922,10 +1041,12 @@ } define @intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -937,10 +1058,13 @@ } define @intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( %0, i8 9, @@ -950,10 +1074,12 @@ } define @intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -965,10 +1091,13 @@ } define @intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( %0, i8 9, @@ -978,10 +1107,12 @@ } define @intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -993,10 +1124,13 @@ } define @intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnclip.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( %0, i8 9, @@ -1006,10 +1140,12 @@ } define @intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -1021,10 +1157,13 @@ } define @intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnclip.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( %0, i8 9, @@ -1034,10 +1173,12 @@ } define @intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -1049,10 +1190,13 @@ } define @intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( %0, i16 9, @@ -1062,10 +1206,12 @@ } define @intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -1077,10 +1223,13 @@ } define @intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( %0, i16 9, @@ -1090,10 +1239,12 @@ } define @intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -1105,10 +1256,13 @@ } define @intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( %0, i16 9, @@ -1118,10 +1272,12 @@ } define @intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -1133,10 +1289,13 @@ } define @intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnclip.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( %0, i16 9, @@ -1146,10 +1305,12 @@ } define @intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1161,10 +1322,13 @@ } define @intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnclip.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( %0, i16 9, @@ -1174,10 +1338,12 @@ } define @intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnclip.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnclip.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnclip.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnclip.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i32.nxv1i64.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i32_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnclip.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i32_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnclip.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i32_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnclip.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vnclip_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i32_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnclip.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vnclip.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vnclip.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vnclip.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vnclip.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vnclip_wx_nxv1i32_nxv1i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv1i32.nxv1i64.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv1i32_nxv1i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vnclip_wx_nxv2i32_nxv2i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vnclip.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv2i32.nxv2i64.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv2i32_nxv2i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vnclip_wx_nxv4i32_nxv4i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vnclip.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv4i32.nxv4i64.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv4i32_nxv4i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vnclip_wx_nxv8i32_nxv8i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vnclip.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wx_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclip.nxv8i32.nxv8i64.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vnclip_mask_wx_nxv8i32_nxv8i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wx_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnclip.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.i32( %0, %1, @@ -1201,10 +1352,13 @@ } define @intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv1i8.nxv1i16.i8( %0, i8 9, @@ -1214,10 +1368,12 @@ } define @intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -1229,10 +1385,13 @@ } define @intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv2i8.nxv2i16.i8( %0, i8 9, @@ -1242,10 +1401,12 @@ } define @intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -1257,10 +1418,13 @@ } define @intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv4i8.nxv4i16.i8( %0, i8 9, @@ -1270,10 +1434,12 @@ } define @intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -1285,10 +1451,13 @@ } define @intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv8i8.nxv8i16.i8( %0, i8 9, @@ -1298,10 +1467,12 @@ } define @intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -1313,10 +1484,13 @@ } define @intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnclip.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv16i8.nxv16i16.i8( %0, i8 9, @@ -1326,10 +1500,12 @@ } define @intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -1341,10 +1517,13 @@ } define @intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnclip.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv32i8.nxv32i16.i8( %0, i8 9, @@ -1354,10 +1533,12 @@ } define @intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -1369,10 +1550,13 @@ } define @intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv1i16.nxv1i32.i16( %0, i16 9, @@ -1382,10 +1566,12 @@ } define @intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -1397,10 +1583,13 @@ } define @intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv2i16.nxv2i32.i16( %0, i16 9, @@ -1410,10 +1599,12 @@ } define @intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -1425,10 +1616,13 @@ } define @intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv4i16.nxv4i32.i16( %0, i16 9, @@ -1438,10 +1632,12 @@ } define @intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -1453,10 +1649,13 @@ } define @intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnclip.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv8i16.nxv8i32.i16( %0, i16 9, @@ -1466,10 +1665,12 @@ } define @intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1481,10 +1682,13 @@ } define @intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnclip.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv16i16.nxv16i32.i16( %0, i16 9, @@ -1494,10 +1698,12 @@ } define @intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -1509,10 +1715,13 @@ } define @intrinsic_vnclip_wi_nxv1i32_nxv1i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv1i32.nxv1i64.i32( %0, i32 9, @@ -1522,10 +1731,12 @@ } define @intrinsic_vnclip_mask_wi_nxv1i32_nxv1i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.i32( %0, %1, @@ -1537,10 +1748,13 @@ } define @intrinsic_vnclip_wi_nxv2i32_nxv2i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnclip.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv2i32.nxv2i64.i32( %0, i32 9, @@ -1550,10 +1764,12 @@ } define @intrinsic_vnclip_mask_wi_nxv2i32_nxv2i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.i32( %0, %1, @@ -1565,10 +1781,13 @@ } define @intrinsic_vnclip_wi_nxv4i32_nxv4i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnclip.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv4i32.nxv4i64.i32( %0, i32 9, @@ -1578,10 +1797,12 @@ } define @intrinsic_vnclip_mask_wi_nxv4i32_nxv4i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.i32( %0, %1, @@ -1593,10 +1814,13 @@ } define @intrinsic_vnclip_wi_nxv8i32_nxv8i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnclip.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_wi_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclip.nxv8i32.nxv8i64.i32( %0, i32 9, @@ -1606,10 +1830,12 @@ } define @intrinsic_vnclip_mask_wi_nxv8i32_nxv8i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclip_mask_wi_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnclip.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnclipu.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnclipu.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnclipu.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnclipu.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vnclipu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vnclipu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vnclipu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vnclipu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -881,10 +992,13 @@ } define @intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( %0, i8 9, @@ -894,10 +1008,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -909,10 +1025,13 @@ } define @intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( %0, i8 9, @@ -922,10 +1041,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -937,10 +1058,13 @@ } define @intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( %0, i8 9, @@ -950,10 +1074,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -965,10 +1091,13 @@ } define @intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( %0, i8 9, @@ -978,10 +1107,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -993,10 +1124,13 @@ } define @intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnclipu.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( %0, i8 9, @@ -1006,10 +1140,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -1021,10 +1157,13 @@ } define @intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnclipu.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( %0, i8 9, @@ -1034,10 +1173,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -1049,10 +1190,13 @@ } define @intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( %0, i16 9, @@ -1062,10 +1206,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -1077,10 +1223,13 @@ } define @intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( %0, i16 9, @@ -1090,10 +1239,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -1105,10 +1256,13 @@ } define @intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( %0, i16 9, @@ -1118,10 +1272,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -1133,10 +1289,13 @@ } define @intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnclipu.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( %0, i16 9, @@ -1146,10 +1305,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1161,10 +1322,13 @@ } define @intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnclipu.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( %0, i16 9, @@ -1174,10 +1338,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnclipu.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnclipu.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnclipu.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnclipu.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vnclipu_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i32_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i32.nxv1i64.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i32_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnclipu.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i32.nxv2i64.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i32_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnclipu.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i32.nxv4i64.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i32_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnclipu.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i32.nxv8i64.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vnclipu_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i32_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnclipu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vnclipu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vnclipu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vnclipu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vnclipu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vnclipu_wx_nxv1i32_nxv1i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv1i32.nxv1i64.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv1i32_nxv1i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vnclipu_wx_nxv2i32_nxv2i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vnclipu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv2i32.nxv2i64.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv2i32_nxv2i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vnclipu_wx_nxv4i32_nxv4i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vnclipu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv4i32.nxv4i64.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv4i32_nxv4i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vnclipu_wx_nxv8i32_nxv8i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vnclipu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wx_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnclipu.nxv8i32.nxv8i64.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vnclipu_mask_wx_nxv8i32_nxv8i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wx_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnclipu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64.i32( %0, %1, @@ -1201,10 +1352,13 @@ } define @intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv1i8.nxv1i16.i8( %0, i8 9, @@ -1214,10 +1368,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -1229,10 +1385,13 @@ } define @intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv2i8.nxv2i16.i8( %0, i8 9, @@ -1242,10 +1401,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -1257,10 +1418,13 @@ } define @intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv4i8.nxv4i16.i8( %0, i8 9, @@ -1270,10 +1434,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -1285,10 +1451,13 @@ } define @intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv8i8.nxv8i16.i8( %0, i8 9, @@ -1298,10 +1467,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -1313,10 +1484,13 @@ } define @intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnclipu.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv16i8.nxv16i16.i8( %0, i8 9, @@ -1326,10 +1500,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -1341,10 +1517,13 @@ } define @intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnclipu.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv32i8.nxv32i16.i8( %0, i8 9, @@ -1354,10 +1533,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -1369,10 +1550,13 @@ } define @intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv1i16.nxv1i32.i16( %0, i16 9, @@ -1382,10 +1566,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -1397,10 +1583,13 @@ } define @intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv2i16.nxv2i32.i16( %0, i16 9, @@ -1410,10 +1599,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -1425,10 +1616,13 @@ } define @intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv4i16.nxv4i32.i16( %0, i16 9, @@ -1438,10 +1632,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -1453,10 +1649,13 @@ } define @intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnclipu.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv8i16.nxv8i32.i16( %0, i16 9, @@ -1466,10 +1665,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1481,10 +1682,13 @@ } define @intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnclipu.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv16i16.nxv16i32.i16( %0, i16 9, @@ -1494,10 +1698,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -1509,10 +1715,13 @@ } define @intrinsic_vnclipu_wi_nxv1i32_nxv1i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv1i32.nxv1i64.i32( %0, i32 9, @@ -1522,10 +1731,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv1i32_nxv1i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64.i32( %0, %1, @@ -1537,10 +1748,13 @@ } define @intrinsic_vnclipu_wi_nxv2i32_nxv2i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnclipu.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv2i32.nxv2i64.i32( %0, i32 9, @@ -1550,10 +1764,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv2i32_nxv2i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64.i32( %0, %1, @@ -1565,10 +1781,13 @@ } define @intrinsic_vnclipu_wi_nxv4i32_nxv4i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnclipu.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv4i32.nxv4i64.i32( %0, i32 9, @@ -1578,10 +1797,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv4i32_nxv4i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64.i32( %0, %1, @@ -1593,10 +1814,13 @@ } define @intrinsic_vnclipu_wi_nxv8i32_nxv8i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnclipu.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_wi_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnclipu.nxv8i32.nxv8i64.i32( %0, i32 9, @@ -1606,10 +1830,12 @@ } define @intrinsic_vnclipu_mask_wi_nxv8i32_nxv8i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnclipu_mask_wi_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnclipu.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv16i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv32i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv16i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i32.nxv1i32( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i32.nxv2i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i32.nxv4i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i32.nxv8i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i8.i8( %0, i8 %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i8.i8( %0, i8 %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i8.i8( %0, i8 %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i8.i8( %0, i8 %1, @@ -721,10 +790,12 @@ i32); define @intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i8.i8( %0, i8 %1, @@ -742,10 +813,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i8.i8( %0, i8 %1, @@ -763,10 +836,12 @@ i32); define @intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i8.i8( %0, i8 %1, @@ -784,10 +859,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i8.i8( %0, i8 %1, @@ -805,10 +882,12 @@ i32); define @intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv16i8.i8( %0, i8 %1, @@ -826,10 +905,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv16i8.i8( %0, i8 %1, @@ -847,10 +928,12 @@ i32); define @intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv32i8.i8( %0, i8 %1, @@ -868,10 +951,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv32i8.i8( %0, i8 %1, @@ -889,10 +974,12 @@ i32); define @intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i16.i16( %0, i16 %1, @@ -910,10 +997,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i16.i16( %0, i16 %1, @@ -931,10 +1020,12 @@ i32); define @intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i16.i16( %0, i16 %1, @@ -952,10 +1043,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i16.i16( %0, i16 %1, @@ -973,10 +1066,12 @@ i32); define @intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i16.i16( %0, i16 %1, @@ -994,10 +1089,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i16.i16( %0, i16 %1, @@ -1015,10 +1112,12 @@ i32); define @intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i16.i16( %0, i16 %1, @@ -1036,10 +1135,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i16.i16( %0, i16 %1, @@ -1057,10 +1158,12 @@ i32); define @intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv16i16.i16( %0, i16 %1, @@ -1078,10 +1181,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv16i16.i16( %0, i16 %1, @@ -1099,10 +1204,12 @@ i32); define @intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i32.i32( %0, i32 %1, @@ -1120,10 +1227,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i32.i32( %0, i32 %1, @@ -1141,10 +1250,12 @@ i32); define @intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i32.i32( %0, i32 %1, @@ -1162,10 +1273,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i32.i32( %0, i32 %1, @@ -1183,10 +1296,12 @@ i32); define @intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i32.i32( %0, i32 %1, @@ -1204,10 +1319,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i32.i32( %0, i32 %1, @@ -1225,10 +1342,12 @@ i32); define @intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1365,12 @@ i32); define @intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i32.i32( %0, i32 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnmsac.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv16i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv32i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv16i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i32.nxv1i32( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i32.nxv2i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i32.nxv4i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i32.nxv8i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vnmsac_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i64.nxv1i64( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vnmsac_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i64.nxv2i64( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vnmsac_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i64.nxv4i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vnmsac.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i8.i8( %0, i8 %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i8.i8( %0, i8 %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i8.i8( %0, i8 %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i8.i8( %0, i8 %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i8.i8( %0, i8 %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i8.i8( %0, i8 %1, @@ -889,10 +974,12 @@ i64); define @intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i8.i8( %0, i8 %1, @@ -910,10 +997,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i8.i8( %0, i8 %1, @@ -931,10 +1020,12 @@ i64); define @intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv16i8.i8( %0, i8 %1, @@ -952,10 +1043,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv16i8.i8( %0, i8 %1, @@ -973,10 +1066,12 @@ i64); define @intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv32i8.i8( %0, i8 %1, @@ -994,10 +1089,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv32i8.i8( %0, i8 %1, @@ -1015,10 +1112,12 @@ i64); define @intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i16.i16( %0, i16 %1, @@ -1036,10 +1135,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i16.i16( %0, i16 %1, @@ -1057,10 +1158,12 @@ i64); define @intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i16.i16( %0, i16 %1, @@ -1078,10 +1181,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i16.i16( %0, i16 %1, @@ -1099,10 +1204,12 @@ i64); define @intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i16.i16( %0, i16 %1, @@ -1120,10 +1227,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i16.i16( %0, i16 %1, @@ -1141,10 +1250,12 @@ i64); define @intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i16.i16( %0, i16 %1, @@ -1162,10 +1273,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i16.i16( %0, i16 %1, @@ -1183,10 +1296,12 @@ i64); define @intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv16i16.i16( %0, i16 %1, @@ -1204,10 +1319,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv16i16.i16( %0, i16 %1, @@ -1225,10 +1342,12 @@ i64); define @intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i32.i32( %0, i32 %1, @@ -1246,10 +1365,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i32.i32( %0, i32 %1, @@ -1267,10 +1388,12 @@ i64); define @intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i32.i32( %0, i32 %1, @@ -1288,10 +1411,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i32.i32( %0, i32 %1, @@ -1309,10 +1434,12 @@ i64); define @intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i32.i32( %0, i32 %1, @@ -1330,10 +1457,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i32.i32( %0, i32 %1, @@ -1351,10 +1480,12 @@ i64); define @intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv8i32.i32( %0, i32 %1, @@ -1372,10 +1503,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv8i32.i32( %0, i32 %1, @@ -1393,10 +1526,12 @@ i64); define @intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv1i64.i64( %0, i64 %1, @@ -1414,10 +1549,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv1i64.i64( %0, i64 %1, @@ -1435,10 +1572,12 @@ i64); define @intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv2i64.i64( %0, i64 %1, @@ -1456,10 +1595,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv2i64.i64( %0, i64 %1, @@ -1477,10 +1618,12 @@ i64); define @intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsac.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1641,12 @@ i64); define @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vnmsac.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsac.mask.nxv4i64.i64( %0, i64 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv16i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv32i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv16i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i32.nxv1i32( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i32.nxv2i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i32.nxv4i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i32.nxv8i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i8.i8( %0, i8 %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i8.i8( %0, i8 %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i8.i8( %0, i8 %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i8.i8( %0, i8 %1, @@ -721,10 +790,12 @@ i32); define @intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i8.i8( %0, i8 %1, @@ -742,10 +813,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i8.i8( %0, i8 %1, @@ -763,10 +836,12 @@ i32); define @intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i8.i8( %0, i8 %1, @@ -784,10 +859,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i8.i8( %0, i8 %1, @@ -805,10 +882,12 @@ i32); define @intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv16i8.i8( %0, i8 %1, @@ -826,10 +905,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv16i8.i8( %0, i8 %1, @@ -847,10 +928,12 @@ i32); define @intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv32i8.i8( %0, i8 %1, @@ -868,10 +951,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv32i8.i8( %0, i8 %1, @@ -889,10 +974,12 @@ i32); define @intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i16.i16( %0, i16 %1, @@ -910,10 +997,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i16.i16( %0, i16 %1, @@ -931,10 +1020,12 @@ i32); define @intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i16.i16( %0, i16 %1, @@ -952,10 +1043,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i16.i16( %0, i16 %1, @@ -973,10 +1066,12 @@ i32); define @intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i16.i16( %0, i16 %1, @@ -994,10 +1089,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i16.i16( %0, i16 %1, @@ -1015,10 +1112,12 @@ i32); define @intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i16.i16( %0, i16 %1, @@ -1036,10 +1135,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i16.i16( %0, i16 %1, @@ -1057,10 +1158,12 @@ i32); define @intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv16i16.i16( %0, i16 %1, @@ -1078,10 +1181,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv16i16.i16( %0, i16 %1, @@ -1099,10 +1204,12 @@ i32); define @intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i32.i32( %0, i32 %1, @@ -1120,10 +1227,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i32.i32( %0, i32 %1, @@ -1141,10 +1250,12 @@ i32); define @intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i32.i32( %0, i32 %1, @@ -1162,10 +1273,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i32.i32( %0, i32 %1, @@ -1183,10 +1296,12 @@ i32); define @intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i32.i32( %0, i32 %1, @@ -1204,10 +1319,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i32.i32( %0, i32 %1, @@ -1225,10 +1342,12 @@ i32); define @intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i32.i32( %0, i32 %1, @@ -1246,10 +1365,12 @@ i32); define @intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i32.i32( %0, i32 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnmsub.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv16i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv32i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv16i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i32.nxv1i32( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i32.nxv2i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i32.nxv4i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i32.nxv8i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vnmsub_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i64.nxv1i64( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vnmsub_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i64.nxv2i64( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vnmsub_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i64.nxv4i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vnmsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i8.i8( %0, i8 %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i8.i8( %0, i8 %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i8.i8( %0, i8 %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i8.i8( %0, i8 %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i8.i8( %0, i8 %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i8.i8( %0, i8 %1, @@ -889,10 +974,12 @@ i64); define @intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i8.i8( %0, i8 %1, @@ -910,10 +997,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i8.i8( %0, i8 %1, @@ -931,10 +1020,12 @@ i64); define @intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv16i8.i8( %0, i8 %1, @@ -952,10 +1043,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv16i8.i8( %0, i8 %1, @@ -973,10 +1066,12 @@ i64); define @intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv32i8.i8( %0, i8 %1, @@ -994,10 +1089,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8( %0, i8 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv32i8.i8( %0, i8 %1, @@ -1015,10 +1112,12 @@ i64); define @intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i16.i16( %0, i16 %1, @@ -1036,10 +1135,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i16.i16( %0, i16 %1, @@ -1057,10 +1158,12 @@ i64); define @intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i16.i16( %0, i16 %1, @@ -1078,10 +1181,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i16.i16( %0, i16 %1, @@ -1099,10 +1204,12 @@ i64); define @intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i16.i16( %0, i16 %1, @@ -1120,10 +1227,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i16.i16( %0, i16 %1, @@ -1141,10 +1250,12 @@ i64); define @intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i16.i16( %0, i16 %1, @@ -1162,10 +1273,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i16.i16( %0, i16 %1, @@ -1183,10 +1296,12 @@ i64); define @intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv16i16.i16( %0, i16 %1, @@ -1204,10 +1319,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16( %0, i16 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv16i16.i16( %0, i16 %1, @@ -1225,10 +1342,12 @@ i64); define @intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i32.i32( %0, i32 %1, @@ -1246,10 +1365,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i32.i32( %0, i32 %1, @@ -1267,10 +1388,12 @@ i64); define @intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i32.i32( %0, i32 %1, @@ -1288,10 +1411,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i32.i32( %0, i32 %1, @@ -1309,10 +1434,12 @@ i64); define @intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i32.i32( %0, i32 %1, @@ -1330,10 +1457,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i32.i32( %0, i32 %1, @@ -1351,10 +1480,12 @@ i64); define @intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv8i32.i32( %0, i32 %1, @@ -1372,10 +1503,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32( %0, i32 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv8i32.i32( %0, i32 %1, @@ -1393,10 +1526,12 @@ i64); define @intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv1i64.i64( %0, i64 %1, @@ -1414,10 +1549,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv1i64.i64( %0, i64 %1, @@ -1435,10 +1572,12 @@ i64); define @intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv2i64.i64( %0, i64 %1, @@ -1456,10 +1595,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv2i64.i64( %0, i64 %1, @@ -1477,10 +1618,12 @@ i64); define @intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}} %a = call @llvm.riscv.vnmsub.nxv4i64.i64( %0, i64 %1, @@ -1498,10 +1641,12 @@ i64); define @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64( %0, i64 %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vnmsub.vx v8, a0, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnmsub.mask.nxv4i64.i64( %0, i64 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vnsra_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vnsra_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnsra.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnsra.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnsra.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vnsra_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vnsra_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnsra.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnsra.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnsra.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vnsra_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vnsra.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vnsra.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vnsra.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vnsra.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -881,10 +992,13 @@ } define @intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( %0, i8 9, @@ -894,10 +1008,12 @@ } define @intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -909,10 +1025,13 @@ } define @intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( %0, i8 9, @@ -922,10 +1041,12 @@ } define @intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -937,10 +1058,13 @@ } define @intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( %0, i8 9, @@ -950,10 +1074,12 @@ } define @intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -965,10 +1091,13 @@ } define @intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( %0, i8 9, @@ -978,10 +1107,12 @@ } define @intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -993,10 +1124,13 @@ } define @intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnsra.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( %0, i8 9, @@ -1006,10 +1140,12 @@ } define @intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -1021,10 +1157,13 @@ } define @intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnsra.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( %0, i8 9, @@ -1034,10 +1173,12 @@ } define @intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -1049,10 +1190,13 @@ } define @intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( %0, i16 9, @@ -1062,10 +1206,12 @@ } define @intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -1077,10 +1223,13 @@ } define @intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( %0, i16 9, @@ -1090,10 +1239,12 @@ } define @intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -1105,10 +1256,13 @@ } define @intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( %0, i16 9, @@ -1118,10 +1272,12 @@ } define @intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -1133,10 +1289,13 @@ } define @intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnsra.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( %0, i16 9, @@ -1146,10 +1305,12 @@ } define @intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1161,10 +1322,13 @@ } define @intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnsra.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( %0, i16 9, @@ -1174,10 +1338,12 @@ } define @intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vnsra_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vnsra_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnsra.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnsra.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnsra.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vnsra_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vnsra_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnsra.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnsra.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnsra.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv1i32_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i32.nxv1i64.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv1i32_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnsra.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv2i32_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i32.nxv2i64.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnsra.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv2i32_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnsra.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv4i32_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i32.nxv4i64.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnsra.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv4i32_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnsra.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wv_nxv8i32_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i32.nxv8i64.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vnsra_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnsra.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wv_nxv8i32_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnsra.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vnsra.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vnsra.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vnsra.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vnsra.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vnsra_wx_nxv1i32_nxv1i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv1i32_nxv1i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vnsra_wx_nxv2i32_nxv2i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vnsra.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv2i32_nxv2i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnsra.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vnsra_wx_nxv4i32_nxv4i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vnsra.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv4i32_nxv4i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnsra.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vnsra_wx_nxv8i32_nxv8i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vnsra.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wx_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vnsra_mask_wx_nxv8i32_nxv8i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnsra.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wx_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnsra.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32( %0, %1, @@ -1201,10 +1352,13 @@ } define @intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv1i8.nxv1i16.i8( %0, i8 9, @@ -1214,10 +1368,12 @@ } define @intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -1229,10 +1385,13 @@ } define @intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv2i8.nxv2i16.i8( %0, i8 9, @@ -1242,10 +1401,12 @@ } define @intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -1257,10 +1418,13 @@ } define @intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv4i8.nxv4i16.i8( %0, i8 9, @@ -1270,10 +1434,12 @@ } define @intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -1285,10 +1451,13 @@ } define @intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv8i8.nxv8i16.i8( %0, i8 9, @@ -1298,10 +1467,12 @@ } define @intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -1313,10 +1484,13 @@ } define @intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnsra.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv16i8.nxv16i16.i8( %0, i8 9, @@ -1326,10 +1500,12 @@ } define @intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -1341,10 +1517,13 @@ } define @intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnsra.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv32i8.nxv32i16.i8( %0, i8 9, @@ -1354,10 +1533,12 @@ } define @intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -1369,10 +1550,13 @@ } define @intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv1i16.nxv1i32.i16( %0, i16 9, @@ -1382,10 +1566,12 @@ } define @intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -1397,10 +1583,13 @@ } define @intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv2i16.nxv2i32.i16( %0, i16 9, @@ -1410,10 +1599,12 @@ } define @intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -1425,10 +1616,13 @@ } define @intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv4i16.nxv4i32.i16( %0, i16 9, @@ -1438,10 +1632,12 @@ } define @intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -1453,10 +1649,13 @@ } define @intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnsra.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv8i16.nxv8i32.i16( %0, i16 9, @@ -1466,10 +1665,12 @@ } define @intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1481,10 +1682,13 @@ } define @intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnsra.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv16i16.nxv16i32.i16( %0, i16 9, @@ -1494,10 +1698,12 @@ } define @intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -1509,10 +1715,13 @@ } define @intrinsic_vnsra_wi_nxv1i32_nxv1i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv1i32.nxv1i64.i32( %0, i32 9, @@ -1522,10 +1731,12 @@ } define @intrinsic_vnsra_mask_wi_nxv1i32_nxv1i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv1i32.nxv1i64.i32( %0, %1, @@ -1537,10 +1748,13 @@ } define @intrinsic_vnsra_wi_nxv2i32_nxv2i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnsra.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv2i32.nxv2i64.i32( %0, i32 9, @@ -1550,10 +1764,12 @@ } define @intrinsic_vnsra_mask_wi_nxv2i32_nxv2i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnsra.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv2i32.nxv2i64.i32( %0, %1, @@ -1565,10 +1781,13 @@ } define @intrinsic_vnsra_wi_nxv4i32_nxv4i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnsra.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv4i32.nxv4i64.i32( %0, i32 9, @@ -1578,10 +1797,12 @@ } define @intrinsic_vnsra_mask_wi_nxv4i32_nxv4i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnsra.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv4i32.nxv4i64.i32( %0, %1, @@ -1593,10 +1814,13 @@ } define @intrinsic_vnsra_wi_nxv8i32_nxv8i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnsra.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_wi_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsra.nxv8i32.nxv8i64.i32( %0, i32 9, @@ -1606,10 +1830,12 @@ } define @intrinsic_vnsra_mask_wi_nxv8i32_nxv8i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnsra.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsra_mask_wi_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnsra.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsra.mask.nxv8i32.nxv8i64.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnsrl.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnsrl.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnsrl.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnsrl.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vnsrl_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vnsrl.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vnsrl.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vnsrl.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vnsrl.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -881,10 +992,13 @@ } define @intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( %0, i8 9, @@ -894,10 +1008,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -909,10 +1025,13 @@ } define @intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( %0, i8 9, @@ -922,10 +1041,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -937,10 +1058,13 @@ } define @intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( %0, i8 9, @@ -950,10 +1074,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -965,10 +1091,13 @@ } define @intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( %0, i8 9, @@ -978,10 +1107,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -993,10 +1124,13 @@ } define @intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnsrl.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( %0, i8 9, @@ -1006,10 +1140,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -1021,10 +1157,13 @@ } define @intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnsrl.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( %0, i8 9, @@ -1034,10 +1173,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -1049,10 +1190,13 @@ } define @intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( %0, i16 9, @@ -1062,10 +1206,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -1077,10 +1223,13 @@ } define @intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( %0, i16 9, @@ -1090,10 +1239,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -1105,10 +1256,13 @@ } define @intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( %0, i16 9, @@ -1118,10 +1272,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -1133,10 +1289,13 @@ } define @intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnsrl.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( %0, i16 9, @@ -1146,10 +1305,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1161,10 +1322,13 @@ } define @intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnsrl.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( %0, i16 9, @@ -1174,10 +1338,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i8_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i8_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i8_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i8_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i8_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i8_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i8_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i8_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnsrl.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i8_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i8_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnsrl.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv32i8_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv32i8_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i16_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i16_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i16_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i16_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i16_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i16_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnsrl.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i16_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i16_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnsrl.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i16_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv16i16_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv1i32_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i32.nxv1i64.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i32_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv1i32_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnsrl.wv v25, v8, v10 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i32_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i32.nxv2i64.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i32_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv2i32_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnsrl.wv v26, v8, v12 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv4i32_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i32.nxv4i64.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i32_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v12, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv4i32_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnsrl.wv v28, v8, v16 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wv_nxv8i32_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i32.nxv8i64.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vnsrl_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i32_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnsrl.wv v8, v16, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wv_nxv8i32_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnsrl.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vnsrl.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vnsrl.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vnsrl.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vnsrl.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vnsrl_wx_nxv1i32_nxv1i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv1i32_nxv1i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vnsrl_wx_nxv2i32_nxv2i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vnsrl.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv2i32_nxv2i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vnsrl_wx_nxv4i32_nxv4i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vnsrl.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv4i32_nxv4i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vnsrl_wx_nxv8i32_nxv8i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vnsrl.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wx_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vnsrl_mask_wx_nxv8i32_nxv8i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vnsrl.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wx_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnsrl.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32( %0, %1, @@ -1201,10 +1352,13 @@ } define @intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv1i8.nxv1i16.i8( %0, i8 9, @@ -1214,10 +1368,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i8_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i8.nxv1i16.i8( %0, %1, @@ -1229,10 +1385,13 @@ } define @intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv2i8.nxv2i16.i8( %0, i8 9, @@ -1242,10 +1401,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i8_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i8.nxv2i16.i8( %0, %1, @@ -1257,10 +1418,13 @@ } define @intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv4i8.nxv4i16.i8( %0, i8 9, @@ -1270,10 +1434,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i8_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i8.nxv4i16.i8( %0, %1, @@ -1285,10 +1451,13 @@ } define @intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv8i8.nxv8i16.i8( %0, i8 9, @@ -1298,10 +1467,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i8_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i8.nxv8i16.i8( %0, %1, @@ -1313,10 +1484,13 @@ } define @intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vnsrl.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv16i8.nxv16i16.i8( %0, i8 9, @@ -1326,10 +1500,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i8_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i8.nxv16i16.i8( %0, %1, @@ -1341,10 +1517,13 @@ } define @intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vnsrl.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv32i8.nxv32i16.i8( %0, i8 9, @@ -1354,10 +1533,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv32i8_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv32i8.nxv32i16.i8( %0, %1, @@ -1369,10 +1550,13 @@ } define @intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv1i16.nxv1i32.i16( %0, i16 9, @@ -1382,10 +1566,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i16_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i16.nxv1i32.i16( %0, %1, @@ -1397,10 +1583,13 @@ } define @intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv2i16.nxv2i32.i16( %0, i16 9, @@ -1410,10 +1599,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i16_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i16.nxv2i32.i16( %0, %1, @@ -1425,10 +1616,13 @@ } define @intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv4i16.nxv4i32.i16( %0, i16 9, @@ -1438,10 +1632,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i16_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i16.nxv4i32.i16( %0, %1, @@ -1453,10 +1649,13 @@ } define @intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vnsrl.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv8i16.nxv8i32.i16( %0, i16 9, @@ -1466,10 +1665,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i16_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i16.nxv8i32.i16( %0, %1, @@ -1481,10 +1682,13 @@ } define @intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vnsrl.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv16i16.nxv16i32.i16( %0, i16 9, @@ -1494,10 +1698,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv16i16_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv16i16.nxv16i32.i16( %0, %1, @@ -1509,10 +1715,13 @@ } define @intrinsic_vnsrl_wi_nxv1i32_nxv1i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv1i32.nxv1i64.i32( %0, i32 9, @@ -1522,10 +1731,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv1i32_nxv1i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i32_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv1i32_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv1i32.nxv1i64.i32( %0, %1, @@ -1537,10 +1748,13 @@ } define @intrinsic_vnsrl_wi_nxv2i32_nxv2i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vnsrl.wi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv2i32.nxv2i64.i32( %0, i32 9, @@ -1550,10 +1764,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv2i32_nxv2i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i32_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv2i32_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv2i32.nxv2i64.i32( %0, %1, @@ -1565,10 +1781,13 @@ } define @intrinsic_vnsrl_wi_nxv4i32_nxv4i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vnsrl.wi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv4i32.nxv4i64.i32( %0, i32 9, @@ -1578,10 +1797,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv4i32_nxv4i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i32_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv4i32_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv4i32.nxv4i64.i32( %0, %1, @@ -1593,10 +1814,13 @@ } define @intrinsic_vnsrl_wi_nxv8i32_nxv8i64_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vnsrl.wi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_wi_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vnsrl.nxv8i32.nxv8i64.i32( %0, i32 9, @@ -1606,10 +1830,12 @@ } define @intrinsic_vnsrl_mask_wi_nxv8i32_nxv8i64_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i32_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vnsrl.wi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vnsrl_mask_wi_nxv8i32_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vnsrl.wi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vnsrl.mask.nxv8i32.nxv8i64.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vor.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vor_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vor_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vor_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vor_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vor_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vor_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vor_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vor_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vor_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vor_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vor_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vor_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vor_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vor_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vor_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vor_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vor_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vor_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vor_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vor_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vor_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vor_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vor_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vor_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vor_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vor_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vor_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vor_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vor_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vor_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vor_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vor_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vor_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vor_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vor_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vor_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vor.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vor_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vor_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vor_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vor_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vor_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vor_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vor_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vor.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vor_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vor_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vor_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vor_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vor_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vor_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vor_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vor_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vor_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vor_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vor_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vor_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vor_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vor_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vor_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vor_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vor_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vor_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vor_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vor_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vor_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vor_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vor_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vor.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vor.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vor_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vor_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vor_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vor_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vor_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vor_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vor_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vor_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vor_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vor_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vor_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vor_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vor_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vor_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vor_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vor_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vor_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vor_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vor_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vor_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vor_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vor_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vor_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vor_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vor_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vor_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vor.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vor_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vor.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vor_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vor_vx_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vor_vx_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -42,7 +42,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -54,7 +54,7 @@ ; CHECK-LABEL: vor_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -66,7 +66,7 @@ ; CHECK-LABEL: vor_vx_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -78,7 +78,7 @@ ; CHECK-LABEL: vor_vx_nxv2i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -91,7 +91,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -103,7 +103,7 @@ ; CHECK-LABEL: vor_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -115,7 +115,7 @@ ; CHECK-LABEL: vor_vx_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -127,7 +127,7 @@ ; CHECK-LABEL: vor_vx_nxv4i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -140,7 +140,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -152,7 +152,7 @@ ; CHECK-LABEL: vor_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -164,7 +164,7 @@ ; CHECK-LABEL: vor_vx_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -176,7 +176,7 @@ ; CHECK-LABEL: vor_vx_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -189,7 +189,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -201,7 +201,7 @@ ; CHECK-LABEL: vor_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -213,7 +213,7 @@ ; CHECK-LABEL: vor_vx_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -225,7 +225,7 @@ ; CHECK-LABEL: vor_vx_nxv16i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -238,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -250,7 +250,7 @@ ; CHECK-LABEL: vor_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -262,7 +262,7 @@ ; CHECK-LABEL: vor_vx_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +274,7 @@ ; CHECK-LABEL: vor_vx_nxv32i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -287,7 +287,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -299,7 +299,7 @@ ; CHECK-LABEL: vor_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -311,7 +311,7 @@ ; CHECK-LABEL: vor_vx_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -323,7 +323,7 @@ ; CHECK-LABEL: vor_vx_nxv64i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -336,7 +336,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +348,7 @@ ; CHECK-LABEL: vor_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -360,7 +360,7 @@ ; CHECK-LABEL: vor_vx_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -372,7 +372,7 @@ ; CHECK-LABEL: vor_vx_nxv1i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -385,7 +385,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -397,7 +397,7 @@ ; CHECK-LABEL: vor_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -409,7 +409,7 @@ ; CHECK-LABEL: vor_vx_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -421,7 +421,7 @@ ; CHECK-LABEL: vor_vx_nxv2i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -434,7 +434,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -446,7 +446,7 @@ ; CHECK-LABEL: vor_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -458,7 +458,7 @@ ; CHECK-LABEL: vor_vx_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -470,7 +470,7 @@ ; CHECK-LABEL: vor_vx_nxv4i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -483,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -495,7 +495,7 @@ ; CHECK-LABEL: vor_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -507,7 +507,7 @@ ; CHECK-LABEL: vor_vx_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -519,7 +519,7 @@ ; CHECK-LABEL: vor_vx_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +532,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -544,7 +544,7 @@ ; CHECK-LABEL: vor_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -556,7 +556,7 @@ ; CHECK-LABEL: vor_vx_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -568,7 +568,7 @@ ; CHECK-LABEL: vor_vx_nxv16i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -581,7 +581,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -593,7 +593,7 @@ ; CHECK-LABEL: vor_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -605,7 +605,7 @@ ; CHECK-LABEL: vor_vx_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -617,7 +617,7 @@ ; CHECK-LABEL: vor_vx_nxv32i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -630,7 +630,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -642,7 +642,7 @@ ; CHECK-LABEL: vor_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -654,7 +654,7 @@ ; CHECK-LABEL: vor_vx_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -666,7 +666,7 @@ ; CHECK-LABEL: vor_vx_nxv1i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +679,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -691,7 +691,7 @@ ; CHECK-LABEL: vor_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -703,7 +703,7 @@ ; CHECK-LABEL: vor_vx_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -715,7 +715,7 @@ ; CHECK-LABEL: vor_vx_nxv2i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -728,7 +728,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -740,7 +740,7 @@ ; CHECK-LABEL: vor_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -752,7 +752,7 @@ ; CHECK-LABEL: vor_vx_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -764,7 +764,7 @@ ; CHECK-LABEL: vor_vx_nxv4i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -777,7 +777,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -789,7 +789,7 @@ ; CHECK-LABEL: vor_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -801,7 +801,7 @@ ; CHECK-LABEL: vor_vx_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -813,7 +813,7 @@ ; CHECK-LABEL: vor_vx_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -826,7 +826,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -838,7 +838,7 @@ ; CHECK-LABEL: vor_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -850,7 +850,7 @@ ; CHECK-LABEL: vor_vx_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -862,7 +862,7 @@ ; CHECK-LABEL: vor_vx_nxv16i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -875,7 +875,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -894,7 +894,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vor.vv v16, v16, v25 +; CHECK-NEXT: vor.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -906,7 +906,7 @@ ; CHECK-LABEL: vor_vx_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -918,7 +918,7 @@ ; CHECK-LABEL: vor_vx_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -931,7 +931,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -950,7 +950,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vor.vv v16, v16, v26 +; CHECK-NEXT: vor.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -962,7 +962,7 @@ ; CHECK-LABEL: vor_vx_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -974,7 +974,7 @@ ; CHECK-LABEL: vor_vx_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -987,7 +987,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1002,11 +1002,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vor.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vor.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1018,7 +1018,7 @@ ; CHECK-LABEL: vor_vx_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1030,7 +1030,7 @@ ; CHECK-LABEL: vor_vx_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1043,7 +1043,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1055,14 +1055,14 @@ ; CHECK-LABEL: vor_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vor.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1074,7 +1074,7 @@ ; CHECK-LABEL: vor_vx_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1086,7 +1086,7 @@ ; CHECK-LABEL: vor_vx_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1099,7 +1099,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vor_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vor_vx_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vor_vx_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -42,7 +42,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -54,7 +54,7 @@ ; CHECK-LABEL: vor_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -66,7 +66,7 @@ ; CHECK-LABEL: vor_vx_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -78,7 +78,7 @@ ; CHECK-LABEL: vor_vx_nxv2i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -91,7 +91,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -103,7 +103,7 @@ ; CHECK-LABEL: vor_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -115,7 +115,7 @@ ; CHECK-LABEL: vor_vx_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -127,7 +127,7 @@ ; CHECK-LABEL: vor_vx_nxv4i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -140,7 +140,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -152,7 +152,7 @@ ; CHECK-LABEL: vor_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -164,7 +164,7 @@ ; CHECK-LABEL: vor_vx_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -176,7 +176,7 @@ ; CHECK-LABEL: vor_vx_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -189,7 +189,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -201,7 +201,7 @@ ; CHECK-LABEL: vor_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -213,7 +213,7 @@ ; CHECK-LABEL: vor_vx_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -225,7 +225,7 @@ ; CHECK-LABEL: vor_vx_nxv16i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -238,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -250,7 +250,7 @@ ; CHECK-LABEL: vor_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -262,7 +262,7 @@ ; CHECK-LABEL: vor_vx_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +274,7 @@ ; CHECK-LABEL: vor_vx_nxv32i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -287,7 +287,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -299,7 +299,7 @@ ; CHECK-LABEL: vor_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -311,7 +311,7 @@ ; CHECK-LABEL: vor_vx_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i8 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -323,7 +323,7 @@ ; CHECK-LABEL: vor_vx_nxv64i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i8 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -336,7 +336,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -348,7 +348,7 @@ ; CHECK-LABEL: vor_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -360,7 +360,7 @@ ; CHECK-LABEL: vor_vx_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -372,7 +372,7 @@ ; CHECK-LABEL: vor_vx_nxv1i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -385,7 +385,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -397,7 +397,7 @@ ; CHECK-LABEL: vor_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -409,7 +409,7 @@ ; CHECK-LABEL: vor_vx_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -421,7 +421,7 @@ ; CHECK-LABEL: vor_vx_nxv2i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -434,7 +434,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -446,7 +446,7 @@ ; CHECK-LABEL: vor_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -458,7 +458,7 @@ ; CHECK-LABEL: vor_vx_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -470,7 +470,7 @@ ; CHECK-LABEL: vor_vx_nxv4i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -483,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -495,7 +495,7 @@ ; CHECK-LABEL: vor_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -507,7 +507,7 @@ ; CHECK-LABEL: vor_vx_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -519,7 +519,7 @@ ; CHECK-LABEL: vor_vx_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +532,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -544,7 +544,7 @@ ; CHECK-LABEL: vor_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -556,7 +556,7 @@ ; CHECK-LABEL: vor_vx_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -568,7 +568,7 @@ ; CHECK-LABEL: vor_vx_nxv16i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -581,7 +581,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -593,7 +593,7 @@ ; CHECK-LABEL: vor_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -605,7 +605,7 @@ ; CHECK-LABEL: vor_vx_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i16 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -617,7 +617,7 @@ ; CHECK-LABEL: vor_vx_nxv32i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i16 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -630,7 +630,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -642,7 +642,7 @@ ; CHECK-LABEL: vor_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -654,7 +654,7 @@ ; CHECK-LABEL: vor_vx_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -666,7 +666,7 @@ ; CHECK-LABEL: vor_vx_nxv1i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -679,7 +679,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -691,7 +691,7 @@ ; CHECK-LABEL: vor_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -703,7 +703,7 @@ ; CHECK-LABEL: vor_vx_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -715,7 +715,7 @@ ; CHECK-LABEL: vor_vx_nxv2i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -728,7 +728,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -740,7 +740,7 @@ ; CHECK-LABEL: vor_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -752,7 +752,7 @@ ; CHECK-LABEL: vor_vx_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -764,7 +764,7 @@ ; CHECK-LABEL: vor_vx_nxv4i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -777,7 +777,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -789,7 +789,7 @@ ; CHECK-LABEL: vor_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -801,7 +801,7 @@ ; CHECK-LABEL: vor_vx_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -813,7 +813,7 @@ ; CHECK-LABEL: vor_vx_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -826,7 +826,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -838,7 +838,7 @@ ; CHECK-LABEL: vor_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -850,7 +850,7 @@ ; CHECK-LABEL: vor_vx_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i32 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -862,7 +862,7 @@ ; CHECK-LABEL: vor_vx_nxv16i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i32 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -875,7 +875,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -887,7 +887,7 @@ ; CHECK-LABEL: vor_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -899,7 +899,7 @@ ; CHECK-LABEL: vor_vx_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -911,7 +911,7 @@ ; CHECK-LABEL: vor_vx_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -924,7 +924,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -936,7 +936,7 @@ ; CHECK-LABEL: vor_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -948,7 +948,7 @@ ; CHECK-LABEL: vor_vx_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -960,7 +960,7 @@ ; CHECK-LABEL: vor_vx_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -973,7 +973,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -985,7 +985,7 @@ ; CHECK-LABEL: vor_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -997,7 +997,7 @@ ; CHECK-LABEL: vor_vx_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1009,7 +1009,7 @@ ; CHECK-LABEL: vor_vx_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1022,7 +1022,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1034,7 +1034,7 @@ ; CHECK-LABEL: vor_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1046,7 +1046,7 @@ ; CHECK-LABEL: vor_vx_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, -12 +; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret %head = insertelement undef, i64 -12, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1058,7 +1058,7 @@ ; CHECK-LABEL: vor_vx_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vor.vi v16, v16, 15 +; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret %head = insertelement undef, i64 15, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1071,7 +1071,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vor.vx v16, v16, a0 +; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare i32 @llvm.riscv.vpopc.i32.nxv1i1( @@ -5,10 +6,12 @@ i32); define i32 @intrinsic_vpopc_m_i32_nxv1i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vpopc.i32.nxv1i1( %0, i32 %1) @@ -22,10 +25,14 @@ i32); define i32 @intrinsic_vpopc_mask_m_i32_nxv1i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv1i1( %0, %1, @@ -39,10 +46,12 @@ i32); define i32 @intrinsic_vpopc_m_i32_nxv2i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vpopc.i32.nxv2i1( %0, i32 %1) @@ -56,10 +65,14 @@ i32); define i32 @intrinsic_vpopc_mask_m_i32_nxv2i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv2i1( %0, %1, @@ -73,10 +86,12 @@ i32); define i32 @intrinsic_vpopc_m_i32_nxv4i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vpopc.i32.nxv4i1( %0, i32 %1) @@ -90,10 +105,14 @@ i32); define i32 @intrinsic_vpopc_mask_m_i32_nxv4i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv4i1( %0, %1, @@ -107,10 +126,12 @@ i32); define i32 @intrinsic_vpopc_m_i32_nxv8i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vpopc.i32.nxv8i1( %0, i32 %1) @@ -124,10 +145,14 @@ i32); define i32 @intrinsic_vpopc_mask_m_i32_nxv8i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv8i1( %0, %1, @@ -141,10 +166,12 @@ i32); define i32 @intrinsic_vpopc_m_i32_nxv16i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vpopc.i32.nxv16i1( %0, i32 %1) @@ -158,10 +185,14 @@ i32); define i32 @intrinsic_vpopc_mask_m_i32_nxv16i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv16i1( %0, %1, @@ -175,10 +206,12 @@ i32); define i32 @intrinsic_vpopc_m_i32_nxv32i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vpopc.i32.nxv32i1( %0, i32 %1) @@ -192,10 +225,14 @@ i32); define i32 @intrinsic_vpopc_mask_m_i32_nxv32i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv32i1( %0, %1, @@ -209,10 +246,12 @@ i32); define i32 @intrinsic_vpopc_m_i32_nxv64i1( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i32_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i32 @llvm.riscv.vpopc.i32.nxv64i1( %0, i32 %1) @@ -226,10 +265,14 @@ i32); define i32 @intrinsic_vpopc_mask_m_i32_nxv64i1( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i32_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i32 @llvm.riscv.vpopc.mask.i32.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare i64 @llvm.riscv.vpopc.i64.nxv1i1( @@ -5,10 +6,12 @@ i64); define i64 @intrinsic_vpopc_m_i64_nxv1i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vpopc.i64.nxv1i1( %0, i64 %1) @@ -22,10 +25,14 @@ i64); define i64 @intrinsic_vpopc_mask_m_i64_nxv1i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv1i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv1i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf8,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv1i1( %0, %1, @@ -39,10 +46,12 @@ i64); define i64 @intrinsic_vpopc_m_i64_nxv2i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vpopc.i64.nxv2i1( %0, i64 %1) @@ -56,10 +65,14 @@ i64); define i64 @intrinsic_vpopc_mask_m_i64_nxv2i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv2i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv2i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf4,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv2i1( %0, %1, @@ -73,10 +86,12 @@ i64); define i64 @intrinsic_vpopc_m_i64_nxv4i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vpopc.i64.nxv4i1( %0, i64 %1) @@ -90,10 +105,14 @@ i64); define i64 @intrinsic_vpopc_mask_m_i64_nxv4i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv4i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv4i1 -; CHECK: vsetvli {{.*}}, a0, e8,mf2,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv4i1( %0, %1, @@ -107,10 +126,12 @@ i64); define i64 @intrinsic_vpopc_m_i64_nxv8i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vpopc.i64.nxv8i1( %0, i64 %1) @@ -124,10 +145,14 @@ i64); define i64 @intrinsic_vpopc_mask_m_i64_nxv8i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv8i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv8i1 -; CHECK: vsetvli {{.*}}, a0, e8,m1,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv8i1( %0, %1, @@ -141,10 +166,12 @@ i64); define i64 @intrinsic_vpopc_m_i64_nxv16i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vpopc.i64.nxv16i1( %0, i64 %1) @@ -158,10 +185,14 @@ i64); define i64 @intrinsic_vpopc_mask_m_i64_nxv16i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv16i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv16i1 -; CHECK: vsetvli {{.*}}, a0, e8,m2,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv16i1( %0, %1, @@ -175,10 +206,12 @@ i64); define i64 @intrinsic_vpopc_m_i64_nxv32i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vpopc.i64.nxv32i1( %0, i64 %1) @@ -192,10 +225,14 @@ i64); define i64 @intrinsic_vpopc_mask_m_i64_nxv32i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv32i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv32i1 -; CHECK: vsetvli {{.*}}, a0, e8,m4,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv32i1( %0, %1, @@ -209,10 +246,12 @@ i64); define i64 @intrinsic_vpopc_m_i64_nxv64i1( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vpopc.m a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}} %a = call i64 @llvm.riscv.vpopc.i64.nxv64i1( %0, i64 %1) @@ -226,10 +265,14 @@ i64); define i64 @intrinsic_vpopc_mask_m_i64_nxv64i1( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv64i1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v25, v0 +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vpopc.m a0, v25, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv64i1 -; CHECK: vsetvli {{.*}}, a0, e8,m8,ta,mu -; CHECK: vpopc.m a0, {{v[0-9]+}}, v0.t %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv64i1( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredand.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredand.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv2i32.nxv16i32( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv1i64.nxv1i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv1i64.nxv1i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv1i64.nxv2i64( %0, %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv1i64.nxv2i64( %0, %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv1i64.nxv4i64( %0, %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv1i64.nxv4i64( %0, %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredand.nxv1i64.nxv8i64( %0, %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredand.mask.nxv1i64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredmax.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredmax.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv1i64.nxv1i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv1i64.nxv2i64( %0, %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64( %0, %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv1i64.nxv4i64( %0, %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64( %0, %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmax.nxv1i64.nxv8i64( %0, %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv1i64.nxv1i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv1i64.nxv2i64( %0, %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64( %0, %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv1i64.nxv4i64( %0, %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64( %0, %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmaxu.nxv1i64.nxv8i64( %0, %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredmin.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredmin.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv1i64.nxv1i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv1i64.nxv2i64( %0, %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64( %0, %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv1i64.nxv4i64( %0, %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64( %0, %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredmin.nxv1i64.nxv8i64( %0, %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredminu.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredminu.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv1i64.nxv1i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv1i64.nxv2i64( %0, %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64( %0, %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv1i64.nxv4i64( %0, %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64( %0, %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredminu.nxv1i64.nxv8i64( %0, %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredor.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredor.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv2i32.nxv16i32( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv1i64.nxv1i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv1i64.nxv1i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv1i64.nxv2i64( %0, %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv1i64.nxv2i64( %0, %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv1i64.nxv4i64( %0, %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv1i64.nxv4i64( %0, %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredor.nxv1i64.nxv8i64( %0, %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredor.mask.nxv1i64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredsum.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredsum.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv1i64.nxv1i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv1i64.nxv2i64( %0, %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64( %0, %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv1i64.nxv4i64( %0, %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64( %0, %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredsum.nxv1i64.nxv8i64( %0, %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredxor.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i32); define @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i32); define @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i32); define @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i32); define @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i32); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vredxor.nxv8i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv8i8.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv1i16( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv2i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv4i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv8i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv16i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv4i16.nxv32i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv1i32( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv2i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv4i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv8i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv2i32.nxv16i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv1i64.nxv1i64( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64( %0, %1, @@ -763,10 +836,12 @@ i64); define @intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv1i64.nxv2i64( %0, %1, @@ -784,10 +859,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64( %0, %1, @@ -805,10 +882,12 @@ i64); define @intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv1i64.nxv4i64( %0, %1, @@ -826,10 +905,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64( %0, %1, @@ -847,10 +928,12 @@ i64); define @intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vredxor.nxv1i64.nxv8i64( %0, %1, @@ -868,10 +951,12 @@ i64); define @intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vrem.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vrem_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vrem_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vrem_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vrem_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vrem_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vrem_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vrem_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vrem_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vrem_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vrem_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vrem_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vrem_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vrem_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vrem_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vrem_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vrem_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vrem_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vrem_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vrem_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vrem_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vrem_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vrem_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vrem_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vrem_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vrem.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vrem_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vrem.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vrem_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vrem.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vrem_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vrem_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vrem_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vrem_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vrem.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vrem_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vrem.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vrem_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vrem.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vrem_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vrem_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vrem_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vrem.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vrem_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vrem.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vrem_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vrem_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vrem.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vrem.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vrem_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vrem_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vrem_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vrem_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vrem_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vrem_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vrem_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vrem_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vrem_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vrem_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vrem_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vrem_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vrem_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vrem_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vrem_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vrem_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vrem_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vrem_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vrem_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vrem.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vrem_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vrem.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vrem_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vrem_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vrem.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vrem_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vrem.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vrem.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vrem_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vrem_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vrem_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vrem_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vrem_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vrem.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vrem_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vrem.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vrem_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vrem.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vrem_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vrem_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vrem_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vrem_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vrem.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vrem_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vrem.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vrem_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vrem.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vrem_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vrem_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vrem_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vrem.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vrem_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vrem.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vrem_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vrem.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vrem_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vrem.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vrem_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vrem.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vrem_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vrem.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vrem_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrem_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vrem.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrem.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vrem_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vrem.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrem_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vrem.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrem.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vrem_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vrem_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vrem_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vrem_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vrem_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vrem_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vrem_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vrem_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vrem_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v18 +; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vrem_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vrem_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v20 +; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vrem_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vrem_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vrem_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vrem.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vrem_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vrem_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vrem_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vrem_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vrem_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vrem_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vrem_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vrem_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v18 +; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vrem_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vrem_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v20 +; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vrem_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vrem_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vrem_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vrem.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vrem_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vrem_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vrem_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vrem_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vrem_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vrem_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v18 +; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vrem_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vrem_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v20 +; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vrem_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vrem_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vrem_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vrem.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vrem_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vrem_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -655,7 +652,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vrem.vv v16, v16, v25 +; CHECK-NEXT: vrem.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -668,7 +665,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -680,7 +677,7 @@ ; CHECK-LABEL: vrem_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v18 +; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -697,7 +694,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vrem.vv v16, v16, v26 +; CHECK-NEXT: vrem.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -710,7 +707,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -722,7 +719,7 @@ ; CHECK-LABEL: vrem_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v20 +; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -735,11 +732,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vrem.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vrem.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -752,7 +749,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -763,9 +760,8 @@ define @vrem_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vrem_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vrem.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -775,14 +771,14 @@ ; CHECK-LABEL: vrem_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vrem.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -795,7 +791,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vrem_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vrem_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vrem_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vrem_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vrem_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vrem_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vrem_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vrem_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vrem_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v18 +; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vrem_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vrem_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v20 +; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vrem_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vrem_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vrem_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vrem.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vrem_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vrem_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vrem_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vrem_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vrem_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vrem_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vrem_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vrem_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v18 +; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vrem_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vrem_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v20 +; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vrem_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vrem_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vrem_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vrem.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vrem_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vrem_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vrem_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vrem_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vrem_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vrem_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v18 +; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vrem_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vrem_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v20 +; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vrem_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vrem_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vrem_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vrem.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vrem_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vrem_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v17 +; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -648,7 +645,7 @@ ; CHECK-LABEL: vrem_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -661,7 +658,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -673,7 +670,7 @@ ; CHECK-LABEL: vrem_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v18 +; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -683,7 +680,7 @@ ; CHECK-LABEL: vrem_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -696,7 +693,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -708,7 +705,7 @@ ; CHECK-LABEL: vrem_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vrem.vv v16, v16, v20 +; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -718,7 +715,7 @@ ; CHECK-LABEL: vrem_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -731,7 +728,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -742,9 +739,8 @@ define @vrem_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vrem_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vrem.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = srem %va, %vb ret %vc @@ -754,7 +750,7 @@ ; CHECK-LABEL: vrem_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -767,7 +763,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vrem.vx v16, v16, a0 +; CHECK-NEXT: vrem.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vremu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vremu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vremu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vremu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vremu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vremu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vremu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vremu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vremu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vremu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vremu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vremu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vremu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vremu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vremu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vremu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vremu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vremu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vremu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vremu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vremu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vremu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vremu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vremu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vremu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vremu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vremu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vremu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vremu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vremu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vremu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vremu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vremu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vremu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vremu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vremu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vremu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vremu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vremu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vremu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vremu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vremu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vremu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vremu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vremu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vremu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vremu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vremu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vremu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vremu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vremu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vremu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vremu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vremu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vremu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vremu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vremu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vremu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vremu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vremu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vremu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vremu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vremu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vremu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vremu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vremu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vremu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vremu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vremu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vremu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vremu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vremu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vremu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vremu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vremu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vremu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vremu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vremu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vremu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vremu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vremu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vremu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vremu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vremu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vremu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vremu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vremu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vremu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vremu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vremu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vremu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vremu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vremu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vremu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vremu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vremu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vremu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vremu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vremu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vremu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vremu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vremu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vremu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vremu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vremu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vremu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vremu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vremu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vremu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vremu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vremu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vremu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vremu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vremu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vremu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vremu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vremu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vremu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vremu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vremu_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vremu_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vremu_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vremu_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vremu_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vremu_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vremu_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vremu_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vremu_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v18 +; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vremu_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vremu_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v20 +; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vremu_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vremu_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vremu_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vremu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vremu_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vremu_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vremu_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vremu_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vremu_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vremu_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vremu_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vremu_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v18 +; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vremu_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vremu_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v20 +; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vremu_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vremu_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vremu_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vremu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vremu_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vremu_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vremu_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vremu_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vremu_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vremu_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v18 +; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vremu_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vremu_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v20 +; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vremu_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vremu_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vremu_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vremu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vremu_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vremu_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -655,7 +652,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vremu.vv v16, v16, v25 +; CHECK-NEXT: vremu.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -668,7 +665,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -680,7 +677,7 @@ ; CHECK-LABEL: vremu_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v18 +; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -697,7 +694,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vremu.vv v16, v16, v26 +; CHECK-NEXT: vremu.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -710,7 +707,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -722,7 +719,7 @@ ; CHECK-LABEL: vremu_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v20 +; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -735,11 +732,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vremu.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vremu.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -752,7 +749,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -763,9 +760,8 @@ define @vremu_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vremu_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vremu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -775,14 +771,14 @@ ; CHECK-LABEL: vremu_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vremu.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -795,7 +791,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vremu_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vremu_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vremu_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vremu_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vremu_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vremu_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vremu_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vremu_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vremu_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v18 +; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vremu_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vremu_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v20 +; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vremu_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vremu_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vremu_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vremu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vremu_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vremu_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vremu_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vremu_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vremu_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vremu_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vremu_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vremu_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v18 +; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vremu_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vremu_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v20 +; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vremu_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vremu_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vremu_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vremu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vremu_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vremu_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vremu_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vremu_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vremu_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vremu_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v18 +; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vremu_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vremu_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v20 +; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vremu_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vremu_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vremu_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vremu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vremu_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vremu_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v17 +; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -648,7 +645,7 @@ ; CHECK-LABEL: vremu_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -661,7 +658,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -673,7 +670,7 @@ ; CHECK-LABEL: vremu_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v18 +; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -683,7 +680,7 @@ ; CHECK-LABEL: vremu_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -696,7 +693,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -708,7 +705,7 @@ ; CHECK-LABEL: vremu_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vremu.vv v16, v16, v20 +; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -718,7 +715,7 @@ ; CHECK-LABEL: vremu_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -731,7 +728,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -742,9 +739,8 @@ define @vremu_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vremu_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vremu.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = urem %va, %vb ret %vc @@ -754,7 +750,7 @@ ; CHECK-LABEL: vremu_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -767,7 +763,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, -7 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vremu.vx v16, v16, a0 +; CHECK-NEXT: vremu.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 -7, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll @@ -10,8 +10,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i8.nxv1i8( @@ -33,7 +33,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i8.nxv1i8( @@ -55,8 +55,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i8.nxv2i8( @@ -78,7 +78,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i8.nxv2i8( @@ -100,8 +100,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i8.nxv4i8( @@ -123,7 +123,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i8.nxv4i8( @@ -145,8 +145,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i8.nxv8i8( @@ -168,7 +168,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i8.nxv8i8( @@ -190,8 +190,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i8.nxv16i8( @@ -213,7 +213,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i8.nxv16i8( @@ -235,8 +235,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i8.nxv32i8( @@ -257,10 +257,8 @@ define @intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i8.nxv32i8( @@ -281,11 +279,9 @@ define @intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e8,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv64i8.nxv64i8( @@ -306,11 +302,10 @@ define @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vle8.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8( @@ -332,8 +327,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i16.nxv1i16( @@ -355,7 +350,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i16.nxv1i16( @@ -377,8 +372,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i16.nxv2i16( @@ -400,7 +395,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i16.nxv2i16( @@ -422,8 +417,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i16.nxv4i16( @@ -445,7 +440,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i16.nxv4i16( @@ -467,8 +462,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i16.nxv8i16( @@ -490,7 +485,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i16.nxv8i16( @@ -512,8 +507,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i16.nxv16i16( @@ -534,10 +529,8 @@ define @intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i16.nxv16i16( @@ -558,11 +551,9 @@ define @intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i16.nxv32i16( @@ -583,11 +574,10 @@ define @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16( @@ -609,8 +599,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i32.nxv1i32( @@ -632,7 +622,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i32.nxv1i32( @@ -654,8 +644,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i32.nxv2i32( @@ -677,7 +667,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i32.nxv2i32( @@ -699,8 +689,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i32.nxv4i32( @@ -722,7 +712,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i32.nxv4i32( @@ -744,8 +734,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i32.nxv8i32( @@ -766,10 +756,8 @@ define @intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i32.nxv8i32( @@ -790,11 +778,9 @@ define @intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i32.nxv16i32( @@ -815,11 +801,10 @@ define @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32( @@ -841,8 +826,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f16.nxv1i16( @@ -864,7 +849,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f16.nxv1i16( @@ -886,8 +871,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f16.nxv2i16( @@ -909,7 +894,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f16.nxv2i16( @@ -931,8 +916,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f16.nxv4i16( @@ -954,7 +939,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f16.nxv4i16( @@ -976,8 +961,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f16.nxv8i16( @@ -999,7 +984,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f16.nxv8i16( @@ -1021,8 +1006,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f16.nxv16i16( @@ -1043,10 +1028,8 @@ define @intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f16.nxv16i16( @@ -1067,11 +1050,9 @@ define @intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32f16.nxv32i16( @@ -1092,11 +1073,10 @@ define @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16( @@ -1118,8 +1098,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f32.nxv1i32( @@ -1141,7 +1121,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f32.nxv1i32( @@ -1163,8 +1143,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f32.nxv2i32( @@ -1186,7 +1166,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f32.nxv2i32( @@ -1208,8 +1188,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f32.nxv4i32( @@ -1231,7 +1211,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f32.nxv4i32( @@ -1253,8 +1233,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f32.nxv8i32( @@ -1275,10 +1255,8 @@ define @intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f32.nxv8i32( @@ -1299,11 +1277,9 @@ define @intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f32.nxv16i32( @@ -1324,11 +1300,10 @@ define @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32( @@ -1350,8 +1325,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i8.i8( @@ -1373,7 +1348,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i8.i8( @@ -1395,8 +1370,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i8.i8( @@ -1418,7 +1393,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i8.i8( @@ -1440,8 +1415,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i8.i8( @@ -1463,7 +1438,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i8.i8( @@ -1485,8 +1460,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i8.i8( @@ -1508,7 +1483,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i8.i8( @@ -1530,8 +1505,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i8.i8( @@ -1553,7 +1528,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i8.i8( @@ -1575,8 +1550,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i8.i8( @@ -1598,7 +1573,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i8.i8( @@ -1620,8 +1595,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv64i8.i8( @@ -1642,10 +1617,8 @@ define @intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv64i8.i8( @@ -1667,8 +1640,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i16.i16( @@ -1690,7 +1663,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i16.i16( @@ -1712,8 +1685,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i16.i16( @@ -1735,7 +1708,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i16.i16( @@ -1757,8 +1730,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i16.i16( @@ -1780,7 +1753,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i16.i16( @@ -1802,8 +1775,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i16.i16( @@ -1825,7 +1798,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i16.i16( @@ -1847,8 +1820,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i16.i16( @@ -1870,7 +1843,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i16.i16( @@ -1892,8 +1865,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i16.i16( @@ -1914,10 +1887,8 @@ define @intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i16.i16( @@ -1939,8 +1910,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i32.i32( @@ -1962,7 +1933,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i32.i32( @@ -1984,8 +1955,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i32.i32( @@ -2007,7 +1978,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i32.i32( @@ -2029,8 +2000,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i32.i32( @@ -2052,7 +2023,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i32.i32( @@ -2074,8 +2045,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i32.i32( @@ -2097,7 +2068,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i32.i32( @@ -2119,8 +2090,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i32.i32( @@ -2141,10 +2112,8 @@ define @intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i32.i32( @@ -2166,8 +2135,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f16_nxv1f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f16.i16( @@ -2189,7 +2158,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f16.i16( @@ -2211,8 +2180,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f16_nxv2f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f16.i16( @@ -2234,7 +2203,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f16.i16( @@ -2256,8 +2225,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f16.i16( @@ -2279,7 +2248,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f16.i16( @@ -2301,8 +2270,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f16.i16( @@ -2324,7 +2293,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f16.i16( @@ -2346,8 +2315,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f16.i16( @@ -2369,7 +2338,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f16.i16( @@ -2391,8 +2360,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv32f16_nxv32f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32f16.i16( @@ -2413,10 +2382,8 @@ define @intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32f16.i16( @@ -2438,8 +2405,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f32_nxv1f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f32.i32( @@ -2461,7 +2428,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f32.i32( @@ -2483,8 +2450,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f32.i32( @@ -2506,7 +2473,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f32.i32( @@ -2528,8 +2495,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f32.i32( @@ -2551,7 +2518,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f32.i32( @@ -2573,8 +2540,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f32.i32( @@ -2596,7 +2563,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f32.i32( @@ -2618,8 +2585,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f32_nxv16f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f32.i32( @@ -2640,10 +2607,8 @@ define @intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f32.i32( @@ -2660,8 +2625,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i8.i8( @@ -2676,7 +2641,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i8.i8( @@ -2693,8 +2658,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i8.i8( @@ -2709,7 +2674,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i8.i8( @@ -2726,8 +2691,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i8.i8( @@ -2742,7 +2707,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i8.i8( @@ -2759,8 +2724,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i8.i8( @@ -2775,7 +2740,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i8.i8( @@ -2792,8 +2757,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i8.i8( @@ -2808,7 +2773,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i8.i8( @@ -2825,8 +2790,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i8.i8( @@ -2841,7 +2806,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i8.i8( @@ -2858,8 +2823,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv64i8.i8( @@ -2873,10 +2838,8 @@ define @intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv64i8.i8( @@ -2893,8 +2856,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i16.i16( @@ -2909,7 +2872,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i16.i16( @@ -2926,8 +2889,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i16.i16( @@ -2942,7 +2905,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i16.i16( @@ -2959,8 +2922,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i16.i16( @@ -2975,7 +2938,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i16.i16( @@ -2992,8 +2955,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i16.i16( @@ -3008,7 +2971,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i16.i16( @@ -3025,8 +2988,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i16.i16( @@ -3041,7 +3004,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i16.i16( @@ -3058,8 +3021,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i16.i16( @@ -3073,10 +3036,8 @@ define @intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i16.i16( @@ -3093,8 +3054,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i32.i32( @@ -3109,7 +3070,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i32.i32( @@ -3126,8 +3087,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i32.i32( @@ -3142,7 +3103,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i32.i32( @@ -3159,8 +3120,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i32.i32( @@ -3175,7 +3136,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i32.i32( @@ -3192,8 +3153,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i32.i32( @@ -3208,7 +3169,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i32.i32( @@ -3225,8 +3186,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i32.i32( @@ -3240,10 +3201,8 @@ define @intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i32.i32( @@ -3260,8 +3219,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f16_nxv1f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f16.i16( @@ -3276,7 +3235,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f16.i16( @@ -3293,8 +3252,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f16_nxv2f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f16.i16( @@ -3309,7 +3268,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f16.i16( @@ -3326,8 +3285,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f16.i16( @@ -3342,7 +3301,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f16.i16( @@ -3359,8 +3318,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f16.i16( @@ -3375,7 +3334,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f16.i16( @@ -3392,8 +3351,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f16.i16( @@ -3408,7 +3367,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f16.i16( @@ -3425,8 +3384,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv32f16_nxv32f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32f16.i16( @@ -3440,10 +3399,8 @@ define @intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32f16.i16( @@ -3460,8 +3417,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f32_nxv1f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f32.i32( @@ -3476,7 +3433,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f32.i32( @@ -3493,8 +3450,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f32.i32( @@ -3509,7 +3466,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f32.i32( @@ -3526,8 +3483,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f32.i32( @@ -3542,7 +3499,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f32.i32( @@ -3559,8 +3516,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f32.i32( @@ -3575,7 +3532,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f32.i32( @@ -3592,8 +3549,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f32_nxv16f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f32.i32( @@ -3607,10 +3564,8 @@ define @intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll @@ -10,8 +10,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i8.nxv1i8( @@ -33,7 +33,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i8.nxv1i8( @@ -55,8 +55,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i8.nxv2i8( @@ -78,7 +78,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i8.nxv2i8( @@ -100,8 +100,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i8.nxv4i8( @@ -123,7 +123,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i8.nxv4i8( @@ -145,8 +145,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i8.nxv8i8( @@ -168,7 +168,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i8.nxv8i8( @@ -190,8 +190,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i8.nxv16i8( @@ -213,7 +213,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i8.nxv16i8( @@ -235,8 +235,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i8.nxv32i8( @@ -257,10 +257,8 @@ define @intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i8.nxv32i8( @@ -281,11 +279,9 @@ define @intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e8,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv64i8.nxv64i8( @@ -306,11 +302,10 @@ define @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu ; CHECK-NEXT: vle8.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8( @@ -332,8 +327,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i16.nxv1i16( @@ -355,7 +350,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i16.nxv1i16( @@ -377,8 +372,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i16.nxv2i16( @@ -400,7 +395,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i16.nxv2i16( @@ -422,8 +417,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i16.nxv4i16( @@ -445,7 +440,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i16.nxv4i16( @@ -467,8 +462,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i16.nxv8i16( @@ -490,7 +485,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i16.nxv8i16( @@ -512,8 +507,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i16.nxv16i16( @@ -534,10 +529,8 @@ define @intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i16.nxv16i16( @@ -558,11 +551,9 @@ define @intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i16.nxv32i16( @@ -583,11 +574,10 @@ define @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16( @@ -609,8 +599,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i32.nxv1i32( @@ -632,7 +622,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i32.nxv1i32( @@ -654,8 +644,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i32.nxv2i32( @@ -677,7 +667,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i32.nxv2i32( @@ -699,8 +689,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i32.nxv4i32( @@ -722,7 +712,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i32.nxv4i32( @@ -744,8 +734,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i32.nxv8i32( @@ -766,10 +756,8 @@ define @intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i32.nxv8i32( @@ -790,11 +778,9 @@ define @intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i32.nxv16i32( @@ -815,11 +801,10 @@ define @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32( @@ -841,8 +826,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i64.nxv1i64( @@ -864,7 +849,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i64.nxv1i64( @@ -886,8 +871,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i64.nxv2i64( @@ -909,7 +894,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i64.nxv2i64( @@ -931,8 +916,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i64.nxv4i64( @@ -953,10 +938,8 @@ define @intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i64.nxv4i64( @@ -977,11 +960,9 @@ define @intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i64.nxv8i64( @@ -1002,11 +983,10 @@ define @intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i64.nxv8i64( @@ -1028,8 +1008,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f16.nxv1i16( @@ -1051,7 +1031,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f16.nxv1i16( @@ -1073,8 +1053,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f16.nxv2i16( @@ -1096,7 +1076,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f16.nxv2i16( @@ -1118,8 +1098,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f16.nxv4i16( @@ -1141,7 +1121,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f16.nxv4i16( @@ -1163,8 +1143,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f16.nxv8i16( @@ -1186,7 +1166,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f16.nxv8i16( @@ -1208,8 +1188,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f16.nxv16i16( @@ -1230,10 +1210,8 @@ define @intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f16.nxv16i16( @@ -1254,11 +1232,9 @@ define @intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32f16.nxv32i16( @@ -1279,11 +1255,10 @@ define @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu ; CHECK-NEXT: vle16.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16( @@ -1305,8 +1280,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f32.nxv1i32( @@ -1328,7 +1303,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f32.nxv1i32( @@ -1350,8 +1325,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f32.nxv2i32( @@ -1373,7 +1348,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f32.nxv2i32( @@ -1395,8 +1370,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f32.nxv4i32( @@ -1418,7 +1393,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f32.nxv4i32( @@ -1440,8 +1415,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f32.nxv8i32( @@ -1462,10 +1437,8 @@ define @intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f32.nxv8i32( @@ -1486,11 +1459,9 @@ define @intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f32.nxv16i32( @@ -1511,11 +1482,10 @@ define @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu ; CHECK-NEXT: vle32.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32( @@ -1537,8 +1507,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vrgather.vv v25, v16, v17 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f64.nxv1i64( @@ -1560,7 +1530,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vrgather.vv v16, v17, v18, v0.t +; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f64.nxv1i64( @@ -1582,8 +1552,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vrgather.vv v26, v16, v18 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f64.nxv2i64( @@ -1605,7 +1575,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vrgather.vv v16, v18, v20, v0.t +; CHECK-NEXT: vrgather.vv v8, v10, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f64.nxv2i64( @@ -1627,8 +1597,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vrgather.vv v28, v16, v20 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f64.nxv4i64( @@ -1649,10 +1619,8 @@ define @intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m4,ta,mu -; CHECK-NEXT: vle64.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m4,tu,mu -; CHECK-NEXT: vrgather.vv v16, v20, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vrgather.vv v8, v12, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f64.nxv4i64( @@ -1673,11 +1641,9 @@ define @intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,ta,mu -; CHECK-NEXT: vrgather.vv v8, v16, v24 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vrgather.vv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f64.nxv8i64( @@ -1698,11 +1664,10 @@ define @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu ; CHECK-NEXT: vle64.v v24, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vrgather.vv v16, v24, v8, v0.t +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vrgather.vv v8, v16, v24, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f64.nxv8i64( @@ -1724,8 +1689,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i8.i8( @@ -1747,7 +1712,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i8.i8( @@ -1769,8 +1734,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i8.i8( @@ -1792,7 +1757,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i8.i8( @@ -1814,8 +1779,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i8.i8( @@ -1837,7 +1802,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i8.i8( @@ -1859,8 +1824,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i8.i8( @@ -1882,7 +1847,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i8.i8( @@ -1904,8 +1869,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i8.i8( @@ -1927,7 +1892,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i8.i8( @@ -1949,8 +1914,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i8.i8( @@ -1972,7 +1937,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i8.i8( @@ -1994,8 +1959,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv64i8.i8( @@ -2016,10 +1981,8 @@ define @intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv64i8.i8( @@ -2041,8 +2004,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i16.i16( @@ -2064,7 +2027,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i16.i16( @@ -2086,8 +2049,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i16.i16( @@ -2109,7 +2072,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i16.i16( @@ -2131,8 +2094,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i16.i16( @@ -2154,7 +2117,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i16.i16( @@ -2176,8 +2139,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i16.i16( @@ -2199,7 +2162,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i16.i16( @@ -2221,8 +2184,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i16.i16( @@ -2244,7 +2207,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i16.i16( @@ -2266,8 +2229,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i16.i16( @@ -2288,10 +2251,8 @@ define @intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i16.i16( @@ -2313,8 +2274,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i32.i32( @@ -2336,7 +2297,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i32.i32( @@ -2358,8 +2319,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i32.i32( @@ -2381,7 +2342,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i32.i32( @@ -2403,8 +2364,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i32.i32( @@ -2426,7 +2387,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i32.i32( @@ -2448,8 +2409,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i32.i32( @@ -2471,7 +2432,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i32.i32( @@ -2493,8 +2454,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i32.i32( @@ -2515,10 +2476,8 @@ define @intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i32.i32( @@ -2540,8 +2499,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i64.i64( @@ -2563,7 +2522,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i64.i64( @@ -2585,8 +2544,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i64.i64( @@ -2608,7 +2567,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i64.i64( @@ -2630,8 +2589,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i64.i64( @@ -2653,7 +2612,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i64.i64( @@ -2675,8 +2634,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i64.i64( @@ -2697,10 +2656,8 @@ define @intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i64.i64( @@ -2722,8 +2679,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f16_nxv1f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f16.i16( @@ -2745,7 +2702,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f16.i16( @@ -2767,8 +2724,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f16_nxv2f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f16.i16( @@ -2790,7 +2747,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f16.i16( @@ -2812,8 +2769,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f16.i16( @@ -2835,7 +2792,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f16.i16( @@ -2857,8 +2814,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f16.i16( @@ -2880,7 +2837,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f16.i16( @@ -2902,8 +2859,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f16.i16( @@ -2925,7 +2882,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f16.i16( @@ -2947,8 +2904,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv32f16_nxv32f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32f16.i16( @@ -2969,10 +2926,8 @@ define @intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32f16.i16( @@ -2994,8 +2949,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f32_nxv1f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f32.i32( @@ -3017,7 +2972,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f32.i32( @@ -3039,8 +2994,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f32.i32( @@ -3062,7 +3017,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f32.i32( @@ -3084,8 +3039,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f32.i32( @@ -3107,7 +3062,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f32.i32( @@ -3129,8 +3084,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f32.i32( @@ -3152,7 +3107,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f32.i32( @@ -3174,8 +3129,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f32_nxv16f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f32.i32( @@ -3196,10 +3151,8 @@ define @intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f32.i32( @@ -3221,8 +3174,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f64_nxv1f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vrgather.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f64.i64( @@ -3244,7 +3197,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vrgather.vx v16, v17, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f64.i64( @@ -3266,8 +3219,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f64_nxv2f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vrgather.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f64.i64( @@ -3289,7 +3242,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vrgather.vx v16, v18, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f64.i64( @@ -3311,8 +3264,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f64_nxv4f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vrgather.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f64.i64( @@ -3334,7 +3287,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vrgather.vx v16, v20, a0, v0.t +; CHECK-NEXT: vrgather.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f64.i64( @@ -3356,8 +3309,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f64_nxv8f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vrgather.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f64.i64( @@ -3378,10 +3331,8 @@ define @intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vrgather.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vrgather.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f64.i64( @@ -3398,8 +3349,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i8.i8( @@ -3414,7 +3365,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i8.i8( @@ -3431,8 +3382,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i8.i8( @@ -3447,7 +3398,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i8.i8( @@ -3464,8 +3415,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i8.i8( @@ -3480,7 +3431,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i8.i8( @@ -3497,8 +3448,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i8.i8( @@ -3513,7 +3464,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i8.i8( @@ -3530,8 +3481,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i8.i8( @@ -3546,7 +3497,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i8.i8( @@ -3563,8 +3514,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i8.i8( @@ -3579,7 +3530,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i8.i8( @@ -3596,8 +3547,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv64i8.i8( @@ -3611,10 +3562,8 @@ define @intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv64i8.i8( @@ -3631,8 +3580,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i16.i16( @@ -3647,7 +3596,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i16.i16( @@ -3664,8 +3613,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i16.i16( @@ -3680,7 +3629,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i16.i16( @@ -3697,8 +3646,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i16.i16( @@ -3713,7 +3662,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i16.i16( @@ -3730,8 +3679,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i16.i16( @@ -3746,7 +3695,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i16.i16( @@ -3763,8 +3712,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i16.i16( @@ -3779,7 +3728,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i16.i16( @@ -3796,8 +3745,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32i16.i16( @@ -3811,10 +3760,8 @@ define @intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32i16.i16( @@ -3831,8 +3778,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i32.i32( @@ -3847,7 +3794,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i32.i32( @@ -3864,8 +3811,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i32.i32( @@ -3880,7 +3827,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i32.i32( @@ -3897,8 +3844,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i32.i32( @@ -3913,7 +3860,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i32.i32( @@ -3930,8 +3877,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i32.i32( @@ -3946,7 +3893,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i32.i32( @@ -3963,8 +3910,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16i32.i32( @@ -3978,10 +3925,8 @@ define @intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16i32.i32( @@ -3998,8 +3943,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1i64.i64( @@ -4014,7 +3959,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1i64.i64( @@ -4031,8 +3976,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2i64.i64( @@ -4047,7 +3992,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2i64.i64( @@ -4064,8 +4009,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4i64.i64( @@ -4080,7 +4025,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4i64.i64( @@ -4097,8 +4042,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8i64.i64( @@ -4112,10 +4057,8 @@ define @intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8i64.i64( @@ -4132,8 +4075,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f16_nxv1f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f16.i16( @@ -4148,7 +4091,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f16.i16( @@ -4165,8 +4108,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f16_nxv2f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f16.i16( @@ -4181,7 +4124,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f16.i16( @@ -4198,8 +4141,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f16.i16( @@ -4214,7 +4157,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f16.i16( @@ -4231,8 +4174,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f16.i16( @@ -4247,7 +4190,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f16.i16( @@ -4264,8 +4207,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f16.i16( @@ -4280,7 +4223,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f16.i16( @@ -4297,8 +4240,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv32f16_nxv32f16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv32f16.i16( @@ -4312,10 +4255,8 @@ define @intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv32f16.i16( @@ -4332,8 +4273,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f32_nxv1f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f32.i32( @@ -4348,7 +4289,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f32.i32( @@ -4365,8 +4306,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f32.i32( @@ -4381,7 +4322,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f32.i32( @@ -4398,8 +4339,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f32.i32( @@ -4414,7 +4355,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f32.i32( @@ -4431,8 +4372,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f32.i32( @@ -4447,7 +4388,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f32.i32( @@ -4464,8 +4405,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f32_nxv16f32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv16f32.i32( @@ -4479,10 +4420,8 @@ define @intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv16f32.i32( @@ -4499,8 +4438,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f64_nxv1f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vrgather.vi v25, v16, 9 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vrgather.vi v25, v8, 9 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv1f64.i64( @@ -4515,7 +4454,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vrgather.vi v16, v17, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv1f64.i64( @@ -4532,8 +4471,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f64_nxv2f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vrgather.vi v26, v16, 9 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vrgather.vi v26, v8, 9 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv2f64.i64( @@ -4548,7 +4487,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vrgather.vi v16, v18, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv2f64.i64( @@ -4565,8 +4504,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f64_nxv4f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vrgather.vi v28, v16, 9 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vrgather.vi v28, v8, 9 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv4f64.i64( @@ -4581,7 +4520,7 @@ ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vrgather.vi v16, v20, 9, v0.t +; CHECK-NEXT: vrgather.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv4f64.i64( @@ -4598,8 +4537,8 @@ ; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f64_nxv8f64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vrgather.vi v8, v16, 9 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vrgather.vi v16, v8, 9 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.nxv8f64.i64( @@ -4613,10 +4552,8 @@ define @intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64_i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vrgather.vi v16, v8, 9, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vrgather.vi v8, v16, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vrgather.mask.nxv8f64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vrsub.nxv1i8.i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv1i8.i8( %0, i8 %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i8.i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv2i8.i8( %0, i8 %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i8.i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv4i8.i8( %0, i8 %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i8.i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv8i8.i8( %0, i8 %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i8.i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv16i8.i8( %0, i8 %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i8.i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv32i8.i8( %0, i8 %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv32i8.i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv64i8.i8( %0, i8 %1, @@ -266,10 +293,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv64i8.i8( %0, %1, @@ -286,10 +315,12 @@ i32); define @intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv1i16.i16( %0, i16 %1, @@ -306,10 +337,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i16.i16( %0, %1, @@ -326,10 +359,12 @@ i32); define @intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv2i16.i16( %0, i16 %1, @@ -346,10 +381,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i16.i16( %0, %1, @@ -366,10 +403,12 @@ i32); define @intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv4i16.i16( %0, i16 %1, @@ -386,10 +425,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i16.i16( %0, %1, @@ -406,10 +447,12 @@ i32); define @intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv8i16.i16( %0, i16 %1, @@ -426,10 +469,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i16.i16( %0, %1, @@ -446,10 +491,12 @@ i32); define @intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv16i16.i16( %0, i16 %1, @@ -466,10 +513,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i16.i16( %0, %1, @@ -486,10 +535,12 @@ i32); define @intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv32i16.i16( %0, i16 %1, @@ -506,10 +557,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv32i16.i16( %0, %1, @@ -526,10 +579,12 @@ i32); define @intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv1i32.i32( %0, i32 %1, @@ -546,10 +601,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i32.i32( %0, %1, @@ -566,10 +623,12 @@ i32); define @intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv2i32.i32( %0, i32 %1, @@ -586,10 +645,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i32.i32( %0, %1, @@ -606,10 +667,12 @@ i32); define @intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv4i32.i32( %0, i32 %1, @@ -626,10 +689,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i32.i32( %0, %1, @@ -646,10 +711,12 @@ i32); define @intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv8i32.i32( %0, i32 %1, @@ -666,10 +733,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i32.i32( %0, %1, @@ -686,10 +755,12 @@ i32); define @intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv16i32.i32( %0, i32 %1, @@ -706,10 +777,12 @@ i32); define @intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i32.i32( %0, %1, @@ -721,10 +794,12 @@ } define @intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv1i8.i8( %0, i8 9, @@ -734,10 +809,12 @@ } define @intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i8.i8( %0, %1, @@ -749,10 +826,12 @@ } define @intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv2i8.i8( %0, i8 9, @@ -762,10 +841,12 @@ } define @intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i8.i8( %0, %1, @@ -777,10 +858,12 @@ } define @intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv4i8.i8( %0, i8 9, @@ -790,10 +873,12 @@ } define @intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i8.i8( %0, %1, @@ -805,10 +890,12 @@ } define @intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv8i8.i8( %0, i8 9, @@ -818,10 +905,12 @@ } define @intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i8.i8( %0, %1, @@ -833,10 +922,12 @@ } define @intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv16i8.i8( %0, i8 9, @@ -846,10 +937,12 @@ } define @intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v10, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i8.i8( %0, %1, @@ -861,10 +954,12 @@ } define @intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv32i8.i8( %0, i8 9, @@ -874,10 +969,12 @@ } define @intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v12, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv32i8.i8( %0, %1, @@ -889,10 +986,12 @@ } define @intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv64i8.i8( %0, i8 9, @@ -902,10 +1001,12 @@ } define @intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vrsub.vi v8, v16, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv64i8.i8( %0, %1, @@ -917,10 +1018,12 @@ } define @intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv1i16.i16( %0, i16 9, @@ -930,10 +1033,12 @@ } define @intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i16.i16( %0, %1, @@ -945,10 +1050,12 @@ } define @intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv2i16.i16( %0, i16 9, @@ -958,10 +1065,12 @@ } define @intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i16.i16( %0, %1, @@ -973,10 +1082,12 @@ } define @intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv4i16.i16( %0, i16 9, @@ -986,10 +1097,12 @@ } define @intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i16.i16( %0, %1, @@ -1001,10 +1114,12 @@ } define @intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv8i16.i16( %0, i16 9, @@ -1014,10 +1129,12 @@ } define @intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v10, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i16.i16( %0, %1, @@ -1029,10 +1146,12 @@ } define @intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv16i16.i16( %0, i16 9, @@ -1042,10 +1161,12 @@ } define @intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v12, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i16.i16( %0, %1, @@ -1057,10 +1178,12 @@ } define @intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv32i16.i16( %0, i16 9, @@ -1070,10 +1193,12 @@ } define @intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vrsub.vi v8, v16, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv32i16.i16( %0, %1, @@ -1085,10 +1210,12 @@ } define @intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv1i32.i32( %0, i32 9, @@ -1098,10 +1225,12 @@ } define @intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i32.i32( %0, %1, @@ -1113,10 +1242,12 @@ } define @intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv2i32.i32( %0, i32 9, @@ -1126,10 +1257,12 @@ } define @intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i32.i32( %0, %1, @@ -1141,10 +1274,12 @@ } define @intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv4i32.i32( %0, i32 9, @@ -1154,10 +1289,12 @@ } define @intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v10, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i32.i32( %0, %1, @@ -1169,10 +1306,12 @@ } define @intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv8i32.i32( %0, i32 9, @@ -1182,10 +1321,12 @@ } define @intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v12, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i32.i32( %0, %1, @@ -1197,10 +1338,12 @@ } define @intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv16i32.i32( %0, i32 9, @@ -1210,10 +1353,12 @@ } define @intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vrsub.vi v8, v16, -9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, -9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vrsub.nxv1i8.i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv1i8.i8( %0, i8 %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i8.i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv2i8.i8( %0, i8 %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i8.i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv4i8.i8( %0, i8 %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i8.i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv8i8.i8( %0, i8 %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i8.i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv16i8.i8( %0, i8 %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i8.i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv32i8.i8( %0, i8 %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv32i8.i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv64i8.i8( %0, i8 %1, @@ -266,10 +293,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv64i8.i8( %0, %1, @@ -286,10 +315,12 @@ i64); define @intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv1i16.i16( %0, i16 %1, @@ -306,10 +337,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i16.i16( %0, %1, @@ -326,10 +359,12 @@ i64); define @intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv2i16.i16( %0, i16 %1, @@ -346,10 +381,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i16.i16( %0, %1, @@ -366,10 +403,12 @@ i64); define @intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv4i16.i16( %0, i16 %1, @@ -386,10 +425,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i16.i16( %0, %1, @@ -406,10 +447,12 @@ i64); define @intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv8i16.i16( %0, i16 %1, @@ -426,10 +469,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i16.i16( %0, %1, @@ -446,10 +491,12 @@ i64); define @intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv16i16.i16( %0, i16 %1, @@ -466,10 +513,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i16.i16( %0, %1, @@ -486,10 +535,12 @@ i64); define @intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv32i16.i16( %0, i16 %1, @@ -506,10 +557,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv32i16.i16( %0, %1, @@ -526,10 +579,12 @@ i64); define @intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv1i32.i32( %0, i32 %1, @@ -546,10 +601,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i32.i32( %0, %1, @@ -566,10 +623,12 @@ i64); define @intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv2i32.i32( %0, i32 %1, @@ -586,10 +645,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i32.i32( %0, %1, @@ -606,10 +667,12 @@ i64); define @intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv4i32.i32( %0, i32 %1, @@ -626,10 +689,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i32.i32( %0, %1, @@ -646,10 +711,12 @@ i64); define @intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv8i32.i32( %0, i32 %1, @@ -666,10 +733,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i32.i32( %0, %1, @@ -686,10 +755,12 @@ i64); define @intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv16i32.i32( %0, i32 %1, @@ -706,10 +777,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i32.i32( %0, %1, @@ -726,10 +799,12 @@ i64); define @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv1i64.i64( %0, i64 %1, @@ -746,10 +821,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i64.i64( %0, %1, @@ -766,10 +843,12 @@ i64); define @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv2i64.i64( %0, i64 %1, @@ -786,10 +865,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i64.i64( %0, %1, @@ -806,10 +887,12 @@ i64); define @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv4i64.i64( %0, i64 %1, @@ -826,10 +909,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i64.i64( %0, %1, @@ -846,10 +931,12 @@ i64); define @intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vrsub.nxv8i64.i64( %0, i64 %1, @@ -866,10 +953,12 @@ i64); define @intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vrsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i64.i64( %0, %1, @@ -881,10 +970,12 @@ } define @intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv1i8.i8( %0, i8 9, @@ -894,10 +985,12 @@ } define @intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i8.i8( %0, %1, @@ -909,10 +1002,12 @@ } define @intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv2i8.i8( %0, i8 9, @@ -922,10 +1017,12 @@ } define @intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i8.i8( %0, %1, @@ -937,10 +1034,12 @@ } define @intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv4i8.i8( %0, i8 9, @@ -950,10 +1049,12 @@ } define @intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i8.i8( %0, %1, @@ -965,10 +1066,12 @@ } define @intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv8i8.i8( %0, i8 9, @@ -978,10 +1081,12 @@ } define @intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i8.i8( %0, %1, @@ -993,10 +1098,12 @@ } define @intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv16i8.i8( %0, i8 9, @@ -1006,10 +1113,12 @@ } define @intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i8.i8( %0, %1, @@ -1021,10 +1130,12 @@ } define @intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv32i8.i8( %0, i8 9, @@ -1034,10 +1145,12 @@ } define @intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv32i8.i8( %0, %1, @@ -1049,10 +1162,12 @@ } define @intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv64i8.i8( %0, i8 9, @@ -1062,10 +1177,12 @@ } define @intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vrsub.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv64i8.i8( %0, %1, @@ -1077,10 +1194,12 @@ } define @intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv1i16.i16( %0, i16 9, @@ -1090,10 +1209,12 @@ } define @intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i16.i16( %0, %1, @@ -1105,10 +1226,12 @@ } define @intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv2i16.i16( %0, i16 9, @@ -1118,10 +1241,12 @@ } define @intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i16.i16( %0, %1, @@ -1133,10 +1258,12 @@ } define @intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv4i16.i16( %0, i16 9, @@ -1146,10 +1273,12 @@ } define @intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i16.i16( %0, %1, @@ -1161,10 +1290,12 @@ } define @intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv8i16.i16( %0, i16 9, @@ -1174,10 +1305,12 @@ } define @intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i16.i16( %0, %1, @@ -1189,10 +1322,12 @@ } define @intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv16i16.i16( %0, i16 9, @@ -1202,10 +1337,12 @@ } define @intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i16.i16( %0, %1, @@ -1217,10 +1354,12 @@ } define @intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv32i16.i16( %0, i16 9, @@ -1230,10 +1369,12 @@ } define @intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vrsub.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv32i16.i16( %0, %1, @@ -1245,10 +1386,12 @@ } define @intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv1i32.i32( %0, i32 9, @@ -1258,10 +1401,12 @@ } define @intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i32.i32( %0, %1, @@ -1273,10 +1418,12 @@ } define @intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv2i32.i32( %0, i32 9, @@ -1286,10 +1433,12 @@ } define @intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i32.i32( %0, %1, @@ -1301,10 +1450,12 @@ } define @intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv4i32.i32( %0, i32 9, @@ -1314,10 +1465,12 @@ } define @intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i32.i32( %0, %1, @@ -1329,10 +1482,12 @@ } define @intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv8i32.i32( %0, i32 9, @@ -1342,10 +1497,12 @@ } define @intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i32.i32( %0, %1, @@ -1357,10 +1514,12 @@ } define @intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv16i32.i32( %0, i32 9, @@ -1370,10 +1529,12 @@ } define @intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vrsub.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv16i32.i32( %0, %1, @@ -1385,10 +1546,12 @@ } define @intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv1i64.i64( %0, i64 9, @@ -1398,10 +1561,12 @@ } define @intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv1i64.i64( %0, %1, @@ -1413,10 +1578,12 @@ } define @intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv2i64.i64( %0, i64 9, @@ -1426,10 +1593,12 @@ } define @intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vrsub.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv2i64.i64( %0, %1, @@ -1441,10 +1610,12 @@ } define @intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv4i64.i64( %0, i64 9, @@ -1454,10 +1625,12 @@ } define @intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vrsub.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv4i64.i64( %0, %1, @@ -1469,10 +1642,12 @@ } define @intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vrsub.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vrsub.nxv8i64.i64( %0, i64 9, @@ -1482,10 +1657,12 @@ } define @intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vrsub.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vrsub.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vrsub.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vrsub_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vrsub_vi_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vrsub_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -41,7 +41,7 @@ ; CHECK-LABEL: vrsub_vi_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -53,7 +53,7 @@ ; CHECK-LABEL: vrsub_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -65,7 +65,7 @@ ; CHECK-LABEL: vrsub_vi_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -77,7 +77,7 @@ ; CHECK-LABEL: vrsub_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -89,7 +89,7 @@ ; CHECK-LABEL: vrsub_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -101,7 +101,7 @@ ; CHECK-LABEL: vrsub_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -113,7 +113,7 @@ ; CHECK-LABEL: vrsub_vi_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -125,7 +125,7 @@ ; CHECK-LABEL: vrsub_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -137,7 +137,7 @@ ; CHECK-LABEL: vrsub_vi_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -149,7 +149,7 @@ ; CHECK-LABEL: vrsub_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -161,7 +161,7 @@ ; CHECK-LABEL: vrsub_vi_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -173,7 +173,7 @@ ; CHECK-LABEL: vrsub_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -185,7 +185,7 @@ ; CHECK-LABEL: vrsub_vi_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vrsub_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -209,7 +209,7 @@ ; CHECK-LABEL: vrsub_vi_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -221,7 +221,7 @@ ; CHECK-LABEL: vrsub_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -233,7 +233,7 @@ ; CHECK-LABEL: vrsub_vi_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +245,7 @@ ; CHECK-LABEL: vrsub_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,7 +257,7 @@ ; CHECK-LABEL: vrsub_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -269,7 +269,7 @@ ; CHECK-LABEL: vrsub_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +281,7 @@ ; CHECK-LABEL: vrsub_vi_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -293,7 +293,7 @@ ; CHECK-LABEL: vrsub_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -305,7 +305,7 @@ ; CHECK-LABEL: vrsub_vi_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -317,7 +317,7 @@ ; CHECK-LABEL: vrsub_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -329,7 +329,7 @@ ; CHECK-LABEL: vrsub_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -341,7 +341,7 @@ ; CHECK-LABEL: vrsub_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -353,7 +353,7 @@ ; CHECK-LABEL: vrsub_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -365,7 +365,7 @@ ; CHECK-LABEL: vrsub_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -377,7 +377,7 @@ ; CHECK-LABEL: vrsub_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -389,7 +389,7 @@ ; CHECK-LABEL: vrsub_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -401,7 +401,7 @@ ; CHECK-LABEL: vrsub_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,7 +413,7 @@ ; CHECK-LABEL: vrsub_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,7 +425,7 @@ ; CHECK-LABEL: vrsub_vi_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -444,7 +444,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vsub.vv v16, v25, v16 +; CHECK-NEXT: vsub.vv v8, v25, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -456,7 +456,7 @@ ; CHECK-LABEL: vrsub_vi_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i64 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -475,7 +475,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vsub.vv v16, v26, v16 +; CHECK-NEXT: vsub.vv v8, v26, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -487,7 +487,7 @@ ; CHECK-LABEL: vrsub_vi_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i64 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -502,11 +502,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vsub.vv v16, v28, v16 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vsub.vv v8, v28, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -518,7 +518,7 @@ ; CHECK-LABEL: vrsub_vi_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i64 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -530,14 +530,14 @@ ; CHECK-LABEL: vrsub_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vsub.vv v16, v8, v16 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vsub.vv v8, v16, v8 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -549,7 +549,7 @@ ; CHECK-LABEL: vrsub_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i64 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vrsub_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vrsub_vi_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vrsub_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -41,7 +41,7 @@ ; CHECK-LABEL: vrsub_vi_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -53,7 +53,7 @@ ; CHECK-LABEL: vrsub_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -65,7 +65,7 @@ ; CHECK-LABEL: vrsub_vi_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -77,7 +77,7 @@ ; CHECK-LABEL: vrsub_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -89,7 +89,7 @@ ; CHECK-LABEL: vrsub_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -101,7 +101,7 @@ ; CHECK-LABEL: vrsub_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -113,7 +113,7 @@ ; CHECK-LABEL: vrsub_vi_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -125,7 +125,7 @@ ; CHECK-LABEL: vrsub_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -137,7 +137,7 @@ ; CHECK-LABEL: vrsub_vi_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -149,7 +149,7 @@ ; CHECK-LABEL: vrsub_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -161,7 +161,7 @@ ; CHECK-LABEL: vrsub_vi_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i8 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -173,7 +173,7 @@ ; CHECK-LABEL: vrsub_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -185,7 +185,7 @@ ; CHECK-LABEL: vrsub_vi_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vrsub_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -209,7 +209,7 @@ ; CHECK-LABEL: vrsub_vi_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -221,7 +221,7 @@ ; CHECK-LABEL: vrsub_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -233,7 +233,7 @@ ; CHECK-LABEL: vrsub_vi_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +245,7 @@ ; CHECK-LABEL: vrsub_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,7 +257,7 @@ ; CHECK-LABEL: vrsub_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -269,7 +269,7 @@ ; CHECK-LABEL: vrsub_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +281,7 @@ ; CHECK-LABEL: vrsub_vi_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -293,7 +293,7 @@ ; CHECK-LABEL: vrsub_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -305,7 +305,7 @@ ; CHECK-LABEL: vrsub_vi_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i16 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -317,7 +317,7 @@ ; CHECK-LABEL: vrsub_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -329,7 +329,7 @@ ; CHECK-LABEL: vrsub_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -341,7 +341,7 @@ ; CHECK-LABEL: vrsub_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -353,7 +353,7 @@ ; CHECK-LABEL: vrsub_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -365,7 +365,7 @@ ; CHECK-LABEL: vrsub_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -377,7 +377,7 @@ ; CHECK-LABEL: vrsub_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -389,7 +389,7 @@ ; CHECK-LABEL: vrsub_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -401,7 +401,7 @@ ; CHECK-LABEL: vrsub_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,7 +413,7 @@ ; CHECK-LABEL: vrsub_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,7 +425,7 @@ ; CHECK-LABEL: vrsub_vi_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i32 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -437,7 +437,7 @@ ; CHECK-LABEL: vrsub_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +449,7 @@ ; CHECK-LABEL: vrsub_vi_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i64 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -461,7 +461,7 @@ ; CHECK-LABEL: vrsub_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -473,7 +473,7 @@ ; CHECK-LABEL: vrsub_vi_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i64 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +485,7 @@ ; CHECK-LABEL: vrsub_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +497,7 @@ ; CHECK-LABEL: vrsub_vi_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i64 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -509,7 +509,7 @@ ; CHECK-LABEL: vrsub_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vrsub.vx v16, v16, a0 +; CHECK-NEXT: vrsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -521,7 +521,7 @@ ; CHECK-LABEL: vrsub_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vrsub.vi v16, v16, -4 +; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret %head = insertelement undef, i64 -4, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsadd.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vsadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vsadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vsadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vsadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vsadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vsadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vsadd_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vsadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vsadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vsadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vsadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vsadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vsadd_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vsadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vsadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vsadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vsadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vsadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vsadd_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vsadd_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vsadd_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vsadd_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vsadd_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vsadd_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vsadd_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vsadd_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vsadd_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vsadd_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vsadd_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vsadd_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vsadd_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vsadd_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vsadd_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vsadd_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vsadd_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vsadd_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vsadd_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vsadd_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vsadd_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vsadd_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vsadd_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vsadd_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vsadd_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vsadd_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vsadd_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vsadd_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vsadd_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vsadd_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vsadd_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vsadd_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vsadd_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vsadd_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vsadd_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vsadd_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vsadd_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vsadd_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vsadd_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vsadd_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vsadd_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vsadd_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vsadd_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vsadd_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vsadd_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vsadd_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vsadd_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vsadd_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vsadd_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vsadd_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vsadd_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vsadd_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vsadd_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vsadd_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vsadd_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vsadd_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsadd.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vsadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vsadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vsadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vsadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vsadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vsadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vsadd_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vsadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vsadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vsadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vsadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vsadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vsadd_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vsadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vsadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vsadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vsadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vsadd_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vsadd_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vsadd_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsadd.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vsadd_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vsadd_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsadd.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vsadd_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsadd.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vsadd.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vsadd_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vsadd_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vsadd_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vsadd_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vsadd_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vsadd_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vsadd_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vsadd_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vsadd_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vsadd_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vsadd_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vsadd_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vsadd_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vsadd_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vsadd_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vsadd_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vsadd_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vsadd_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vsadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vsadd_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vsadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vsadd_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vsadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vsadd_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsadd.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsadd.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vsadd_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vsadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vsadd_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vsadd_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vsadd_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vsadd_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vsadd_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vsadd_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vsadd_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vsadd_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vsadd_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vsadd_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vsadd_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vsadd_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vsadd_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vsadd_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vsadd_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vsadd_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vsadd_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vsadd_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vsadd_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vsadd_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vsadd_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vsadd_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vsadd_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vsadd_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vsadd_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vsadd_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vsadd_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vsadd_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vsadd_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vsadd_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vsadd_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vsadd_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vsadd_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vsadd_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vsadd_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vsadd_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vsadd_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vsadd_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsadd.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vsadd_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vsadd_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsadd.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vsadd_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vsadd_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsadd.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vsadd_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsadd.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsadd.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vsadd_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vsadd.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsadd_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsadd.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsadd.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vsaddu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vsaddu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vsaddu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vsaddu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vsaddu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vsaddu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vsaddu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vsaddu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vsaddu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vsaddu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vsaddu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vsaddu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vsaddu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vsaddu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vsaddu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vsaddu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vsaddu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vsaddu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vsaddu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vsaddu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vsaddu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vsaddu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vsaddu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vsaddu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vsaddu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vsaddu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vsaddu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vsaddu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vsaddu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vsaddu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vsaddu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vsaddu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vsaddu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vsaddu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vsaddu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vsaddu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vsaddu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vsaddu_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vsaddu_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vsaddu_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vsaddu_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vsaddu_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vsaddu_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vsaddu_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vsaddu_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vsaddu_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vsaddu_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vsaddu_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vsaddu_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vsaddu_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vsaddu_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vsaddu_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vsaddu_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vsaddu_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vsaddu_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsaddu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vsaddu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vsaddu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vsaddu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vsaddu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vsaddu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vsaddu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vsaddu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vsaddu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vsaddu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vsaddu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vsaddu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vsaddu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vsaddu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vsaddu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vsaddu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vsaddu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vsaddu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vsaddu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vsaddu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vsaddu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vsaddu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vsaddu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsaddu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vsaddu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vsaddu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vsaddu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vsaddu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vsaddu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vsaddu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vsaddu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vsaddu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vsaddu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vsaddu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vsaddu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vsaddu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vsaddu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vsaddu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vsaddu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vsaddu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vsaddu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vsaddu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vsaddu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vsaddu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vsaddu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vsaddu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vsaddu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsaddu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsaddu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vsaddu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vsaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vsaddu_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vsaddu_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vsaddu_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vsaddu_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vsaddu_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vsaddu_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vsaddu_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vsaddu_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vsaddu_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vsaddu_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vsaddu_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vsaddu_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vsaddu_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vsaddu_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vsaddu_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vsaddu_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vsaddu_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vsaddu_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vsaddu_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vsaddu_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vsaddu_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vsaddu_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsaddu.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsaddu.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vsaddu_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vsaddu.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsaddu_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsaddu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsaddu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsbc.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +30,12 @@ i32); define @intrinsic_vsbc_vvm_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +52,12 @@ i32); define @intrinsic_vsbc_vvm_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +74,12 @@ i32); define @intrinsic_vsbc_vvm_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +96,12 @@ i32); define @intrinsic_vsbc_vvm_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +118,12 @@ i32); define @intrinsic_vsbc_vvm_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +140,12 @@ i32); define @intrinsic_vsbc_vvm_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +162,12 @@ i32); define @intrinsic_vsbc_vvm_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +184,12 @@ i32); define @intrinsic_vsbc_vvm_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +206,12 @@ i32); define @intrinsic_vsbc_vvm_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +228,12 @@ i32); define @intrinsic_vsbc_vvm_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +250,12 @@ i32); define @intrinsic_vsbc_vvm_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +272,12 @@ i32); define @intrinsic_vsbc_vvm_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +294,12 @@ i32); define @intrinsic_vsbc_vvm_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +316,12 @@ i32); define @intrinsic_vsbc_vvm_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +338,12 @@ i32); define @intrinsic_vsbc_vvm_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +360,12 @@ i32); define @intrinsic_vsbc_vvm_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +382,12 @@ i32); define @intrinsic_vsbc_vvm_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +404,12 @@ i32); define @intrinsic_vsbc_vxm_nxv1i8_nxv1i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i8.i8( %0, i8 %1, @@ -387,10 +426,12 @@ i32); define @intrinsic_vsbc_vxm_nxv2i8_nxv2i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i8.i8( %0, i8 %1, @@ -407,10 +448,12 @@ i32); define @intrinsic_vsbc_vxm_nxv4i8_nxv4i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i8.i8( %0, i8 %1, @@ -427,10 +470,12 @@ i32); define @intrinsic_vsbc_vxm_nxv8i8_nxv8i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i8.i8( %0, i8 %1, @@ -447,10 +492,12 @@ i32); define @intrinsic_vsbc_vxm_nxv16i8_nxv16i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i8.i8( %0, i8 %1, @@ -467,10 +514,12 @@ i32); define @intrinsic_vsbc_vxm_nxv32i8_nxv32i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv32i8.i8( %0, i8 %1, @@ -487,10 +536,12 @@ i32); define @intrinsic_vsbc_vxm_nxv64i8_nxv64i8_i8( %0, i8 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv64i8.i8( %0, i8 %1, @@ -507,10 +558,12 @@ i32); define @intrinsic_vsbc_vxm_nxv1i16_nxv1i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i16.i16( %0, i16 %1, @@ -527,10 +580,12 @@ i32); define @intrinsic_vsbc_vxm_nxv2i16_nxv2i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i16.i16( %0, i16 %1, @@ -547,10 +602,12 @@ i32); define @intrinsic_vsbc_vxm_nxv4i16_nxv4i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i16.i16( %0, i16 %1, @@ -567,10 +624,12 @@ i32); define @intrinsic_vsbc_vxm_nxv8i16_nxv8i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i16.i16( %0, i16 %1, @@ -587,10 +646,12 @@ i32); define @intrinsic_vsbc_vxm_nxv16i16_nxv16i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i16.i16( %0, i16 %1, @@ -607,10 +668,12 @@ i32); define @intrinsic_vsbc_vxm_nxv32i16_nxv32i16_i16( %0, i16 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv32i16.i16( %0, i16 %1, @@ -627,10 +690,12 @@ i32); define @intrinsic_vsbc_vxm_nxv1i32_nxv1i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i32.i32( %0, i32 %1, @@ -647,10 +712,12 @@ i32); define @intrinsic_vsbc_vxm_nxv2i32_nxv2i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i32.i32( %0, i32 %1, @@ -667,10 +734,12 @@ i32); define @intrinsic_vsbc_vxm_nxv4i32_nxv4i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i32.i32( %0, i32 %1, @@ -687,10 +756,12 @@ i32); define @intrinsic_vsbc_vxm_nxv8i32_nxv8i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i32.i32( %0, i32 %1, @@ -707,10 +778,12 @@ i32); define @intrinsic_vsbc_vxm_nxv16i32_nxv16i32_i32( %0, i32 %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i32.i32( %0, i32 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsbc-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsbc.nxv1i8.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i8.nxv1i8( %0, %1, @@ -27,10 +30,12 @@ i64); define @intrinsic_vsbc_vvm_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i8.nxv2i8( %0, %1, @@ -47,10 +52,12 @@ i64); define @intrinsic_vsbc_vvm_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i8.nxv4i8( %0, %1, @@ -67,10 +74,12 @@ i64); define @intrinsic_vsbc_vvm_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i8.nxv8i8( %0, %1, @@ -87,10 +96,12 @@ i64); define @intrinsic_vsbc_vvm_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i8.nxv16i8( %0, %1, @@ -107,10 +118,12 @@ i64); define @intrinsic_vsbc_vvm_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv32i8.nxv32i8( %0, %1, @@ -127,10 +140,12 @@ i64); define @intrinsic_vsbc_vvm_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv64i8.nxv64i8( %0, %1, @@ -147,10 +162,12 @@ i64); define @intrinsic_vsbc_vvm_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i16.nxv1i16( %0, %1, @@ -167,10 +184,12 @@ i64); define @intrinsic_vsbc_vvm_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i16.nxv2i16( %0, %1, @@ -187,10 +206,12 @@ i64); define @intrinsic_vsbc_vvm_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i16.nxv4i16( %0, %1, @@ -207,10 +228,12 @@ i64); define @intrinsic_vsbc_vvm_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i16.nxv8i16( %0, %1, @@ -227,10 +250,12 @@ i64); define @intrinsic_vsbc_vvm_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i16.nxv16i16( %0, %1, @@ -247,10 +272,12 @@ i64); define @intrinsic_vsbc_vvm_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv32i16.nxv32i16( %0, %1, @@ -267,10 +294,12 @@ i64); define @intrinsic_vsbc_vvm_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i32.nxv1i32( %0, %1, @@ -287,10 +316,12 @@ i64); define @intrinsic_vsbc_vvm_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i32.nxv2i32( %0, %1, @@ -307,10 +338,12 @@ i64); define @intrinsic_vsbc_vvm_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i32.nxv4i32( %0, %1, @@ -327,10 +360,12 @@ i64); define @intrinsic_vsbc_vvm_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i32.nxv8i32( %0, %1, @@ -347,10 +382,12 @@ i64); define @intrinsic_vsbc_vvm_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i32.nxv16i32( %0, %1, @@ -367,10 +404,12 @@ i64); define @intrinsic_vsbc_vvm_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i64.nxv1i64( %0, %1, @@ -387,10 +426,12 @@ i64); define @intrinsic_vsbc_vvm_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i64.nxv2i64( %0, %1, @@ -407,10 +448,12 @@ i64); define @intrinsic_vsbc_vvm_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i64.nxv4i64( %0, %1, @@ -427,10 +470,12 @@ i64); define @intrinsic_vsbc_vvm_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsbc.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i64.nxv8i64( %0, %1, @@ -447,10 +492,12 @@ i64); define @intrinsic_vsbc_vxm_nxv1i8_nxv1i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i8.i8( %0, i8 %1, @@ -467,10 +514,12 @@ i64); define @intrinsic_vsbc_vxm_nxv2i8_nxv2i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i8.i8( %0, i8 %1, @@ -487,10 +536,12 @@ i64); define @intrinsic_vsbc_vxm_nxv4i8_nxv4i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i8.i8( %0, i8 %1, @@ -507,10 +558,12 @@ i64); define @intrinsic_vsbc_vxm_nxv8i8_nxv8i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i8.i8( %0, i8 %1, @@ -527,10 +580,12 @@ i64); define @intrinsic_vsbc_vxm_nxv16i8_nxv16i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i8.i8( %0, i8 %1, @@ -547,10 +602,12 @@ i64); define @intrinsic_vsbc_vxm_nxv32i8_nxv32i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv32i8.i8( %0, i8 %1, @@ -567,10 +624,12 @@ i64); define @intrinsic_vsbc_vxm_nxv64i8_nxv64i8_i8( %0, i8 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv64i8.i8( %0, i8 %1, @@ -587,10 +646,12 @@ i64); define @intrinsic_vsbc_vxm_nxv1i16_nxv1i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i16.i16( %0, i16 %1, @@ -607,10 +668,12 @@ i64); define @intrinsic_vsbc_vxm_nxv2i16_nxv2i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i16.i16( %0, i16 %1, @@ -627,10 +690,12 @@ i64); define @intrinsic_vsbc_vxm_nxv4i16_nxv4i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i16.i16( %0, i16 %1, @@ -647,10 +712,12 @@ i64); define @intrinsic_vsbc_vxm_nxv8i16_nxv8i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i16.i16( %0, i16 %1, @@ -667,10 +734,12 @@ i64); define @intrinsic_vsbc_vxm_nxv16i16_nxv16i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i16.i16( %0, i16 %1, @@ -687,10 +756,12 @@ i64); define @intrinsic_vsbc_vxm_nxv32i16_nxv32i16_i16( %0, i16 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv32i16.i16( %0, i16 %1, @@ -707,10 +778,12 @@ i64); define @intrinsic_vsbc_vxm_nxv1i32_nxv1i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i32.i32( %0, i32 %1, @@ -727,10 +800,12 @@ i64); define @intrinsic_vsbc_vxm_nxv2i32_nxv2i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i32.i32( %0, i32 %1, @@ -747,10 +822,12 @@ i64); define @intrinsic_vsbc_vxm_nxv4i32_nxv4i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i32.i32( %0, i32 %1, @@ -767,10 +844,12 @@ i64); define @intrinsic_vsbc_vxm_nxv8i32_nxv8i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i32.i32( %0, i32 %1, @@ -787,10 +866,12 @@ i64); define @intrinsic_vsbc_vxm_nxv16i32_nxv16i32_i32( %0, i32 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv16i32.i32( %0, i32 %1, @@ -807,10 +888,12 @@ i64); define @intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv1i64.i64( %0, i64 %1, @@ -827,10 +910,12 @@ i64); define @intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv2i64.i64( %0, i64 %1, @@ -847,10 +932,12 @@ i64); define @intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv4i64.i64( %0, i64 %1, @@ -867,10 +954,12 @@ i64); define @intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64( %0, i64 %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsbc.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0 %a = call @llvm.riscv.vsbc.nxv8i64.i64( %0, i64 %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: -mattr=+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s @@ -7,10 +8,12 @@ i32); define void @intrinsic_vse_v_nxv1i32_nxv1i32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1i32( %0, * %1, @@ -26,10 +29,12 @@ i32); define void @intrinsic_vse_mask_v_nxv1i32_nxv1i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1i32( %0, * %1, @@ -45,10 +50,12 @@ i32); define void @intrinsic_vse_v_nxv2i32_nxv2i32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2i32( %0, * %1, @@ -64,10 +71,12 @@ i32); define void @intrinsic_vse_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2i32( %0, * %1, @@ -83,10 +92,12 @@ i32); define void @intrinsic_vse_v_nxv4i32_nxv4i32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4i32( %0, * %1, @@ -102,10 +113,12 @@ i32); define void @intrinsic_vse_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4i32( %0, * %1, @@ -121,10 +134,12 @@ i32); define void @intrinsic_vse_v_nxv8i32_nxv8i32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8i32( %0, * %1, @@ -140,10 +155,12 @@ i32); define void @intrinsic_vse_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8i32( %0, * %1, @@ -159,10 +176,12 @@ i32); define void @intrinsic_vse_v_nxv16i32_nxv16i32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16i32( %0, * %1, @@ -178,10 +197,12 @@ i32); define void @intrinsic_vse_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16i32( %0, * %1, @@ -197,10 +218,12 @@ i32); define void @intrinsic_vse_v_nxv1f32_nxv1f32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1f32( %0, * %1, @@ -216,10 +239,12 @@ i32); define void @intrinsic_vse_mask_v_nxv1f32_nxv1f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1f32( %0, * %1, @@ -235,10 +260,12 @@ i32); define void @intrinsic_vse_v_nxv2f32_nxv2f32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2f32( %0, * %1, @@ -254,10 +281,12 @@ i32); define void @intrinsic_vse_mask_v_nxv2f32_nxv2f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2f32( %0, * %1, @@ -273,10 +302,12 @@ i32); define void @intrinsic_vse_v_nxv4f32_nxv4f32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4f32( %0, * %1, @@ -292,10 +323,12 @@ i32); define void @intrinsic_vse_mask_v_nxv4f32_nxv4f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4f32( %0, * %1, @@ -311,10 +344,12 @@ i32); define void @intrinsic_vse_v_nxv8f32_nxv8f32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8f32( %0, * %1, @@ -330,10 +365,12 @@ i32); define void @intrinsic_vse_mask_v_nxv8f32_nxv8f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8f32( %0, * %1, @@ -349,10 +386,12 @@ i32); define void @intrinsic_vse_v_nxv16f32_nxv16f32( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16f32( %0, * %1, @@ -368,10 +407,12 @@ i32); define void @intrinsic_vse_mask_v_nxv16f32_nxv16f32( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16f32( %0, * %1, @@ -387,10 +428,12 @@ i32); define void @intrinsic_vse_v_nxv1i16_nxv1i16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1i16( %0, * %1, @@ -406,10 +449,12 @@ i32); define void @intrinsic_vse_mask_v_nxv1i16_nxv1i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1i16( %0, * %1, @@ -425,10 +470,12 @@ i32); define void @intrinsic_vse_v_nxv2i16_nxv2i16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2i16( %0, * %1, @@ -444,10 +491,12 @@ i32); define void @intrinsic_vse_mask_v_nxv2i16_nxv2i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2i16( %0, * %1, @@ -463,10 +512,12 @@ i32); define void @intrinsic_vse_v_nxv4i16_nxv4i16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4i16( %0, * %1, @@ -482,10 +533,12 @@ i32); define void @intrinsic_vse_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4i16( %0, * %1, @@ -501,10 +554,12 @@ i32); define void @intrinsic_vse_v_nxv8i16_nxv8i16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8i16( %0, * %1, @@ -520,10 +575,12 @@ i32); define void @intrinsic_vse_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8i16( %0, * %1, @@ -539,10 +596,12 @@ i32); define void @intrinsic_vse_v_nxv16i16_nxv16i16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16i16( %0, * %1, @@ -558,10 +617,12 @@ i32); define void @intrinsic_vse_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16i16( %0, * %1, @@ -577,10 +638,12 @@ i32); define void @intrinsic_vse_v_nxv32i16_nxv32i16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv32i16( %0, * %1, @@ -596,10 +659,12 @@ i32); define void @intrinsic_vse_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv32i16( %0, * %1, @@ -615,10 +680,12 @@ i32); define void @intrinsic_vse_v_nxv1f16_nxv1f16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1f16( %0, * %1, @@ -634,10 +701,12 @@ i32); define void @intrinsic_vse_mask_v_nxv1f16_nxv1f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1f16( %0, * %1, @@ -653,10 +722,12 @@ i32); define void @intrinsic_vse_v_nxv2f16_nxv2f16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2f16( %0, * %1, @@ -672,10 +743,12 @@ i32); define void @intrinsic_vse_mask_v_nxv2f16_nxv2f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2f16( %0, * %1, @@ -691,10 +764,12 @@ i32); define void @intrinsic_vse_v_nxv4f16_nxv4f16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4f16( %0, * %1, @@ -710,10 +785,12 @@ i32); define void @intrinsic_vse_mask_v_nxv4f16_nxv4f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4f16( %0, * %1, @@ -729,10 +806,12 @@ i32); define void @intrinsic_vse_v_nxv8f16_nxv8f16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8f16( %0, * %1, @@ -748,10 +827,12 @@ i32); define void @intrinsic_vse_mask_v_nxv8f16_nxv8f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8f16( %0, * %1, @@ -767,10 +848,12 @@ i32); define void @intrinsic_vse_v_nxv16f16_nxv16f16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16f16( %0, * %1, @@ -786,10 +869,12 @@ i32); define void @intrinsic_vse_mask_v_nxv16f16_nxv16f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16f16( %0, * %1, @@ -805,10 +890,12 @@ i32); define void @intrinsic_vse_v_nxv32f16_nxv32f16( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv32f16( %0, * %1, @@ -824,10 +911,12 @@ i32); define void @intrinsic_vse_mask_v_nxv32f16_nxv32f16( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv32f16( %0, * %1, @@ -843,10 +932,12 @@ i32); define void @intrinsic_vse_v_nxv1i8_nxv1i8( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1i8( %0, * %1, @@ -862,10 +953,12 @@ i32); define void @intrinsic_vse_mask_v_nxv1i8_nxv1i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1i8( %0, * %1, @@ -881,10 +974,12 @@ i32); define void @intrinsic_vse_v_nxv2i8_nxv2i8( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2i8( %0, * %1, @@ -900,10 +995,12 @@ i32); define void @intrinsic_vse_mask_v_nxv2i8_nxv2i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2i8( %0, * %1, @@ -919,10 +1016,12 @@ i32); define void @intrinsic_vse_v_nxv4i8_nxv4i8( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4i8( %0, * %1, @@ -938,10 +1037,12 @@ i32); define void @intrinsic_vse_mask_v_nxv4i8_nxv4i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4i8( %0, * %1, @@ -957,10 +1058,12 @@ i32); define void @intrinsic_vse_v_nxv8i8_nxv8i8( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8i8( %0, * %1, @@ -976,10 +1079,12 @@ i32); define void @intrinsic_vse_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8i8( %0, * %1, @@ -995,10 +1100,12 @@ i32); define void @intrinsic_vse_v_nxv16i8_nxv16i8( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16i8( %0, * %1, @@ -1014,10 +1121,12 @@ i32); define void @intrinsic_vse_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16i8( %0, * %1, @@ -1033,10 +1142,12 @@ i32); define void @intrinsic_vse_v_nxv32i8_nxv32i8( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv32i8( %0, * %1, @@ -1052,10 +1163,12 @@ i32); define void @intrinsic_vse_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv32i8( %0, * %1, @@ -1071,10 +1184,12 @@ i32); define void @intrinsic_vse_v_nxv64i8_nxv64i8( %0, * %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv64i8( %0, * %1, @@ -1090,10 +1205,12 @@ i32); define void @intrinsic_vse_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv64i8( %0, * %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s @@ -7,10 +8,12 @@ i64); define void @intrinsic_vse_v_nxv1i64_nxv1i64( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vse64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1i64( %0, * %1, @@ -26,10 +29,12 @@ i64); define void @intrinsic_vse_mask_v_nxv1i64_nxv1i64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vse64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1i64( %0, * %1, @@ -45,10 +50,12 @@ i64); define void @intrinsic_vse_v_nxv2i64_nxv2i64( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vse64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2i64( %0, * %1, @@ -64,10 +71,12 @@ i64); define void @intrinsic_vse_mask_v_nxv2i64_nxv2i64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vse64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2i64( %0, * %1, @@ -83,10 +92,12 @@ i64); define void @intrinsic_vse_v_nxv4i64_nxv4i64( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vse64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4i64( %0, * %1, @@ -102,10 +113,12 @@ i64); define void @intrinsic_vse_mask_v_nxv4i64_nxv4i64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vse64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4i64( %0, * %1, @@ -121,10 +134,12 @@ i64); define void @intrinsic_vse_v_nxv8i64_nxv8i64( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vse64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8i64( %0, * %1, @@ -140,10 +155,12 @@ i64); define void @intrinsic_vse_mask_v_nxv8i64_nxv8i64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vse64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8i64( %0, * %1, @@ -159,10 +176,12 @@ i64); define void @intrinsic_vse_v_nxv1f64_nxv1f64( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vse64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1f64( %0, * %1, @@ -178,10 +197,12 @@ i64); define void @intrinsic_vse_mask_v_nxv1f64_nxv1f64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vse64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1f64( %0, * %1, @@ -197,10 +218,12 @@ i64); define void @intrinsic_vse_v_nxv2f64_nxv2f64( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vse64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2f64( %0, * %1, @@ -216,10 +239,12 @@ i64); define void @intrinsic_vse_mask_v_nxv2f64_nxv2f64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vse64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2f64( %0, * %1, @@ -235,10 +260,12 @@ i64); define void @intrinsic_vse_v_nxv4f64_nxv4f64( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vse64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4f64( %0, * %1, @@ -254,10 +281,12 @@ i64); define void @intrinsic_vse_mask_v_nxv4f64_nxv4f64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vse64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4f64( %0, * %1, @@ -273,10 +302,12 @@ i64); define void @intrinsic_vse_v_nxv8f64_nxv8f64( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vse64.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8f64( %0, * %1, @@ -292,10 +323,12 @@ i64); define void @intrinsic_vse_mask_v_nxv8f64_nxv8f64( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vse64.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vse64.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8f64( %0, * %1, @@ -311,10 +344,12 @@ i64); define void @intrinsic_vse_v_nxv1i32_nxv1i32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1i32( %0, * %1, @@ -330,10 +365,12 @@ i64); define void @intrinsic_vse_mask_v_nxv1i32_nxv1i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1i32( %0, * %1, @@ -349,10 +386,12 @@ i64); define void @intrinsic_vse_v_nxv2i32_nxv2i32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2i32( %0, * %1, @@ -368,10 +407,12 @@ i64); define void @intrinsic_vse_mask_v_nxv2i32_nxv2i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2i32( %0, * %1, @@ -387,10 +428,12 @@ i64); define void @intrinsic_vse_v_nxv4i32_nxv4i32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4i32( %0, * %1, @@ -406,10 +449,12 @@ i64); define void @intrinsic_vse_mask_v_nxv4i32_nxv4i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4i32( %0, * %1, @@ -425,10 +470,12 @@ i64); define void @intrinsic_vse_v_nxv8i32_nxv8i32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8i32( %0, * %1, @@ -444,10 +491,12 @@ i64); define void @intrinsic_vse_mask_v_nxv8i32_nxv8i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8i32( %0, * %1, @@ -463,10 +512,12 @@ i64); define void @intrinsic_vse_v_nxv16i32_nxv16i32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16i32( %0, * %1, @@ -482,10 +533,12 @@ i64); define void @intrinsic_vse_mask_v_nxv16i32_nxv16i32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16i32( %0, * %1, @@ -501,10 +554,12 @@ i64); define void @intrinsic_vse_v_nxv1f32_nxv1f32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1f32( %0, * %1, @@ -520,10 +575,12 @@ i64); define void @intrinsic_vse_mask_v_nxv1f32_nxv1f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1f32( %0, * %1, @@ -539,10 +596,12 @@ i64); define void @intrinsic_vse_v_nxv2f32_nxv2f32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2f32( %0, * %1, @@ -558,10 +617,12 @@ i64); define void @intrinsic_vse_mask_v_nxv2f32_nxv2f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2f32( %0, * %1, @@ -577,10 +638,12 @@ i64); define void @intrinsic_vse_v_nxv4f32_nxv4f32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4f32( %0, * %1, @@ -596,10 +659,12 @@ i64); define void @intrinsic_vse_mask_v_nxv4f32_nxv4f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4f32( %0, * %1, @@ -615,10 +680,12 @@ i64); define void @intrinsic_vse_v_nxv8f32_nxv8f32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8f32( %0, * %1, @@ -634,10 +701,12 @@ i64); define void @intrinsic_vse_mask_v_nxv8f32_nxv8f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8f32( %0, * %1, @@ -653,10 +722,12 @@ i64); define void @intrinsic_vse_v_nxv16f32_nxv16f32( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16f32( %0, * %1, @@ -672,10 +743,12 @@ i64); define void @intrinsic_vse_mask_v_nxv16f32_nxv16f32( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vse32.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vse32.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16f32( %0, * %1, @@ -691,10 +764,12 @@ i64); define void @intrinsic_vse_v_nxv1i16_nxv1i16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1i16( %0, * %1, @@ -710,10 +785,12 @@ i64); define void @intrinsic_vse_mask_v_nxv1i16_nxv1i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1i16( %0, * %1, @@ -729,10 +806,12 @@ i64); define void @intrinsic_vse_v_nxv2i16_nxv2i16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2i16( %0, * %1, @@ -748,10 +827,12 @@ i64); define void @intrinsic_vse_mask_v_nxv2i16_nxv2i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2i16( %0, * %1, @@ -767,10 +848,12 @@ i64); define void @intrinsic_vse_v_nxv4i16_nxv4i16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4i16( %0, * %1, @@ -786,10 +869,12 @@ i64); define void @intrinsic_vse_mask_v_nxv4i16_nxv4i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4i16( %0, * %1, @@ -805,10 +890,12 @@ i64); define void @intrinsic_vse_v_nxv8i16_nxv8i16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8i16( %0, * %1, @@ -824,10 +911,12 @@ i64); define void @intrinsic_vse_mask_v_nxv8i16_nxv8i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8i16( %0, * %1, @@ -843,10 +932,12 @@ i64); define void @intrinsic_vse_v_nxv16i16_nxv16i16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16i16( %0, * %1, @@ -862,10 +953,12 @@ i64); define void @intrinsic_vse_mask_v_nxv16i16_nxv16i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16i16( %0, * %1, @@ -881,10 +974,12 @@ i64); define void @intrinsic_vse_v_nxv32i16_nxv32i16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv32i16( %0, * %1, @@ -900,10 +995,12 @@ i64); define void @intrinsic_vse_mask_v_nxv32i16_nxv32i16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv32i16( %0, * %1, @@ -919,10 +1016,12 @@ i64); define void @intrinsic_vse_v_nxv1f16_nxv1f16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1f16( %0, * %1, @@ -938,10 +1037,12 @@ i64); define void @intrinsic_vse_mask_v_nxv1f16_nxv1f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1f16( %0, * %1, @@ -957,10 +1058,12 @@ i64); define void @intrinsic_vse_v_nxv2f16_nxv2f16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2f16( %0, * %1, @@ -976,10 +1079,12 @@ i64); define void @intrinsic_vse_mask_v_nxv2f16_nxv2f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2f16( %0, * %1, @@ -995,10 +1100,12 @@ i64); define void @intrinsic_vse_v_nxv4f16_nxv4f16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4f16( %0, * %1, @@ -1014,10 +1121,12 @@ i64); define void @intrinsic_vse_mask_v_nxv4f16_nxv4f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4f16( %0, * %1, @@ -1033,10 +1142,12 @@ i64); define void @intrinsic_vse_v_nxv8f16_nxv8f16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8f16( %0, * %1, @@ -1052,10 +1163,12 @@ i64); define void @intrinsic_vse_mask_v_nxv8f16_nxv8f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8f16( %0, * %1, @@ -1071,10 +1184,12 @@ i64); define void @intrinsic_vse_v_nxv16f16_nxv16f16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16f16( %0, * %1, @@ -1090,10 +1205,12 @@ i64); define void @intrinsic_vse_mask_v_nxv16f16_nxv16f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16f16( %0, * %1, @@ -1109,10 +1226,12 @@ i64); define void @intrinsic_vse_v_nxv32f16_nxv32f16( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vse16.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv32f16( %0, * %1, @@ -1128,10 +1247,12 @@ i64); define void @intrinsic_vse_mask_v_nxv32f16_nxv32f16( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vse16.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vse16.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv32f16( %0, * %1, @@ -1147,10 +1268,12 @@ i64); define void @intrinsic_vse_v_nxv1i8_nxv1i8( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv1i8( %0, * %1, @@ -1166,10 +1289,12 @@ i64); define void @intrinsic_vse_mask_v_nxv1i8_nxv1i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv1i8( %0, * %1, @@ -1185,10 +1310,12 @@ i64); define void @intrinsic_vse_v_nxv2i8_nxv2i8( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv2i8( %0, * %1, @@ -1204,10 +1331,12 @@ i64); define void @intrinsic_vse_mask_v_nxv2i8_nxv2i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv2i8( %0, * %1, @@ -1223,10 +1352,12 @@ i64); define void @intrinsic_vse_v_nxv4i8_nxv4i8( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv4i8( %0, * %1, @@ -1242,10 +1373,12 @@ i64); define void @intrinsic_vse_mask_v_nxv4i8_nxv4i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv4i8( %0, * %1, @@ -1261,10 +1394,12 @@ i64); define void @intrinsic_vse_v_nxv8i8_nxv8i8( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv8i8( %0, * %1, @@ -1280,10 +1415,12 @@ i64); define void @intrinsic_vse_mask_v_nxv8i8_nxv8i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv8i8( %0, * %1, @@ -1299,10 +1436,12 @@ i64); define void @intrinsic_vse_v_nxv16i8_nxv16i8( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv16i8( %0, * %1, @@ -1318,10 +1457,12 @@ i64); define void @intrinsic_vse_mask_v_nxv16i8_nxv16i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv16i8( %0, * %1, @@ -1337,10 +1478,12 @@ i64); define void @intrinsic_vse_v_nxv32i8_nxv32i8( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv32i8( %0, * %1, @@ -1356,10 +1499,12 @@ i64); define void @intrinsic_vse_mask_v_nxv32i8_nxv32i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv32i8( %0, * %1, @@ -1375,10 +1520,12 @@ i64); define void @intrinsic_vse_v_nxv64i8_nxv64i8( %0, * %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vse_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0) call void @llvm.riscv.vse.nxv64i8( %0, * %1, @@ -1394,10 +1541,12 @@ i64); define void @intrinsic_vse_mask_v_nxv64i8_nxv64i8( %0, * %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vse_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vse8.v v8, (a0), v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vse_mask_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vse8.v {{v[0-9]+}}, (a0), v0.t call void @llvm.riscv.vse.mask.nxv64i8( %0, * %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK-LABEL: vfmerge_zv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 0, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half zeroinitializer, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -121,7 +121,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -132,9 +132,8 @@ define @vfmerge_vv_nxv32f16( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -145,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +156,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -167,7 +166,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -179,7 +178,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -189,7 +188,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -201,7 +200,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -211,7 +210,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -223,7 +222,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -233,7 +232,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +244,7 @@ ; CHECK-LABEL: vfmerge_zv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 0, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float zeroinitializer, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -256,9 +255,8 @@ define @vfmerge_vv_nxv16f32( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -268,7 +266,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -280,7 +278,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -290,7 +288,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -302,7 +300,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -312,7 +310,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -324,7 +322,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -334,7 +332,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -345,9 +343,8 @@ define @vfmerge_vv_nxv8f64( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -357,7 +354,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -369,7 +366,7 @@ ; CHECK-LABEL: vfmerge_zv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 0, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double zeroinitializer, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll @@ -6,7 +6,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -17,7 +17,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv2f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -40,7 +40,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv4f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -86,7 +86,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK-LABEL: vfmerge_zv_nxv8f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 0, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half zeroinitializer, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv16f16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -121,7 +121,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -132,9 +132,8 @@ define @vfmerge_vv_nxv32f16( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv32f16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -145,7 +144,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, half %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +156,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -167,7 +166,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -179,7 +178,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -189,7 +188,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv2f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -201,7 +200,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -211,7 +210,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv4f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -223,7 +222,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -233,7 +232,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +244,7 @@ ; CHECK-LABEL: vfmerge_zv_nxv8f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 0, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float zeroinitializer, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -256,9 +255,8 @@ define @vfmerge_vv_nxv16f32( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv16f32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -268,7 +266,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv16f32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, float %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -280,7 +278,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -290,7 +288,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -302,7 +300,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -312,7 +310,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv2f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -324,7 +322,7 @@ ; CHECK-LABEL: vfmerge_vv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -334,7 +332,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv4f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -345,9 +343,8 @@ define @vfmerge_vv_nxv8f64( %va, %vb, %cond) { ; CHECK-LABEL: vfmerge_vv_nxv8f64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -357,7 +354,7 @@ ; CHECK-LABEL: vfmerge_fv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0 +; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -369,7 +366,7 @@ ; CHECK-LABEL: vfmerge_zv_nxv8f64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 0, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 0, v0 ; CHECK-NEXT: ret %head = insertelement undef, double zeroinitializer, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmerge_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vmerge_xv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -27,7 +27,7 @@ ; CHECK-LABEL: vmerge_iv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -39,7 +39,7 @@ ; CHECK-LABEL: vmerge_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -49,7 +49,7 @@ ; CHECK-LABEL: vmerge_xv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -61,7 +61,7 @@ ; CHECK-LABEL: vmerge_iv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -73,7 +73,7 @@ ; CHECK-LABEL: vmerge_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -83,7 +83,7 @@ ; CHECK-LABEL: vmerge_xv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -95,7 +95,7 @@ ; CHECK-LABEL: vmerge_iv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -107,7 +107,7 @@ ; CHECK-LABEL: vmerge_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -117,7 +117,7 @@ ; CHECK-LABEL: vmerge_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -129,7 +129,7 @@ ; CHECK-LABEL: vmerge_iv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -141,7 +141,7 @@ ; CHECK-LABEL: vmerge_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -151,7 +151,7 @@ ; CHECK-LABEL: vmerge_xv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -163,7 +163,7 @@ ; CHECK-LABEL: vmerge_iv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -175,7 +175,7 @@ ; CHECK-LABEL: vmerge_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -185,7 +185,7 @@ ; CHECK-LABEL: vmerge_xv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vmerge_iv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -208,9 +208,8 @@ define @vmerge_vv_nxv64i8( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -220,7 +219,7 @@ ; CHECK-LABEL: vmerge_xv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,7 +231,7 @@ ; CHECK-LABEL: vmerge_iv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -244,7 +243,7 @@ ; CHECK-LABEL: vmerge_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -254,7 +253,7 @@ ; CHECK-LABEL: vmerge_xv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -266,7 +265,7 @@ ; CHECK-LABEL: vmerge_iv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -278,7 +277,7 @@ ; CHECK-LABEL: vmerge_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -288,7 +287,7 @@ ; CHECK-LABEL: vmerge_xv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +299,7 @@ ; CHECK-LABEL: vmerge_iv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -312,7 +311,7 @@ ; CHECK-LABEL: vmerge_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -322,7 +321,7 @@ ; CHECK-LABEL: vmerge_xv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,7 +333,7 @@ ; CHECK-LABEL: vmerge_iv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,7 +345,7 @@ ; CHECK-LABEL: vmerge_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -356,7 +355,7 @@ ; CHECK-LABEL: vmerge_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -368,7 +367,7 @@ ; CHECK-LABEL: vmerge_iv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -380,7 +379,7 @@ ; CHECK-LABEL: vmerge_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -390,7 +389,7 @@ ; CHECK-LABEL: vmerge_xv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -402,7 +401,7 @@ ; CHECK-LABEL: vmerge_iv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,9 +412,8 @@ define @vmerge_vv_nxv32i16( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -425,7 +423,7 @@ ; CHECK-LABEL: vmerge_xv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -437,7 +435,7 @@ ; CHECK-LABEL: vmerge_iv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +447,7 @@ ; CHECK-LABEL: vmerge_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -459,7 +457,7 @@ ; CHECK-LABEL: vmerge_xv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -471,7 +469,7 @@ ; CHECK-LABEL: vmerge_iv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -483,7 +481,7 @@ ; CHECK-LABEL: vmerge_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -493,7 +491,7 @@ ; CHECK-LABEL: vmerge_xv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -505,7 +503,7 @@ ; CHECK-LABEL: vmerge_iv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -517,7 +515,7 @@ ; CHECK-LABEL: vmerge_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -527,7 +525,7 @@ ; CHECK-LABEL: vmerge_xv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmerge_iv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -551,7 +549,7 @@ ; CHECK-LABEL: vmerge_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -561,7 +559,7 @@ ; CHECK-LABEL: vmerge_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -573,7 +571,7 @@ ; CHECK-LABEL: vmerge_iv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -584,9 +582,8 @@ define @vmerge_vv_nxv16i32( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -596,7 +593,7 @@ ; CHECK-LABEL: vmerge_xv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -608,7 +605,7 @@ ; CHECK-LABEL: vmerge_iv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -620,7 +617,7 @@ ; CHECK-LABEL: vmerge_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -637,7 +634,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vmerge.vvm v16, v16, v25, v0 +; CHECK-NEXT: vmerge.vvm v8, v8, v25, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -649,7 +646,7 @@ ; CHECK-LABEL: vmerge_iv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -661,7 +658,7 @@ ; CHECK-LABEL: vmerge_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -678,7 +675,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vmerge.vvm v16, v16, v26, v0 +; CHECK-NEXT: vmerge.vvm v8, v8, v26, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -690,7 +687,7 @@ ; CHECK-LABEL: vmerge_iv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -702,7 +699,7 @@ ; CHECK-LABEL: vmerge_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -715,11 +712,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vmerge.vvm v16, v16, v28, v0 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vmerge.vvm v8, v8, v28, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -731,7 +728,7 @@ ; CHECK-LABEL: vmerge_iv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -742,9 +739,8 @@ define @vmerge_vv_nxv8i64( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -754,14 +750,14 @@ ; CHECK-LABEL: vmerge_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -773,7 +769,7 @@ ; CHECK-LABEL: vmerge_iv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-int-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vmerge_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vmerge_xv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -27,7 +27,7 @@ ; CHECK-LABEL: vmerge_iv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -39,7 +39,7 @@ ; CHECK-LABEL: vmerge_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -49,7 +49,7 @@ ; CHECK-LABEL: vmerge_xv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -61,7 +61,7 @@ ; CHECK-LABEL: vmerge_iv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -73,7 +73,7 @@ ; CHECK-LABEL: vmerge_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -83,7 +83,7 @@ ; CHECK-LABEL: vmerge_xv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -95,7 +95,7 @@ ; CHECK-LABEL: vmerge_iv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -107,7 +107,7 @@ ; CHECK-LABEL: vmerge_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -117,7 +117,7 @@ ; CHECK-LABEL: vmerge_xv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -129,7 +129,7 @@ ; CHECK-LABEL: vmerge_iv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -141,7 +141,7 @@ ; CHECK-LABEL: vmerge_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -151,7 +151,7 @@ ; CHECK-LABEL: vmerge_xv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -163,7 +163,7 @@ ; CHECK-LABEL: vmerge_iv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -175,7 +175,7 @@ ; CHECK-LABEL: vmerge_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -185,7 +185,7 @@ ; CHECK-LABEL: vmerge_xv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vmerge_iv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -208,9 +208,8 @@ define @vmerge_vv_nxv64i8( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -220,7 +219,7 @@ ; CHECK-LABEL: vmerge_xv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,7 +231,7 @@ ; CHECK-LABEL: vmerge_iv_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i8 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -244,7 +243,7 @@ ; CHECK-LABEL: vmerge_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -254,7 +253,7 @@ ; CHECK-LABEL: vmerge_xv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -266,7 +265,7 @@ ; CHECK-LABEL: vmerge_iv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -278,7 +277,7 @@ ; CHECK-LABEL: vmerge_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -288,7 +287,7 @@ ; CHECK-LABEL: vmerge_xv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +299,7 @@ ; CHECK-LABEL: vmerge_iv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -312,7 +311,7 @@ ; CHECK-LABEL: vmerge_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -322,7 +321,7 @@ ; CHECK-LABEL: vmerge_xv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,7 +333,7 @@ ; CHECK-LABEL: vmerge_iv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,7 +345,7 @@ ; CHECK-LABEL: vmerge_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -356,7 +355,7 @@ ; CHECK-LABEL: vmerge_xv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -368,7 +367,7 @@ ; CHECK-LABEL: vmerge_iv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -380,7 +379,7 @@ ; CHECK-LABEL: vmerge_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -390,7 +389,7 @@ ; CHECK-LABEL: vmerge_xv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -402,7 +401,7 @@ ; CHECK-LABEL: vmerge_iv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,9 +412,8 @@ define @vmerge_vv_nxv32i16( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -425,7 +423,7 @@ ; CHECK-LABEL: vmerge_xv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -437,7 +435,7 @@ ; CHECK-LABEL: vmerge_iv_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i16 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +447,7 @@ ; CHECK-LABEL: vmerge_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -459,7 +457,7 @@ ; CHECK-LABEL: vmerge_xv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -471,7 +469,7 @@ ; CHECK-LABEL: vmerge_iv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -483,7 +481,7 @@ ; CHECK-LABEL: vmerge_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -493,7 +491,7 @@ ; CHECK-LABEL: vmerge_xv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -505,7 +503,7 @@ ; CHECK-LABEL: vmerge_iv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -517,7 +515,7 @@ ; CHECK-LABEL: vmerge_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -527,7 +525,7 @@ ; CHECK-LABEL: vmerge_xv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vmerge_iv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -551,7 +549,7 @@ ; CHECK-LABEL: vmerge_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -561,7 +559,7 @@ ; CHECK-LABEL: vmerge_xv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -573,7 +571,7 @@ ; CHECK-LABEL: vmerge_iv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -584,9 +582,8 @@ define @vmerge_vv_nxv16i32( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -596,7 +593,7 @@ ; CHECK-LABEL: vmerge_xv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -608,7 +605,7 @@ ; CHECK-LABEL: vmerge_iv_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i32 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -620,7 +617,7 @@ ; CHECK-LABEL: vmerge_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v17, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -630,7 +627,7 @@ ; CHECK-LABEL: vmerge_xv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -642,7 +639,7 @@ ; CHECK-LABEL: vmerge_iv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -654,7 +651,7 @@ ; CHECK-LABEL: vmerge_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v18, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -664,7 +661,7 @@ ; CHECK-LABEL: vmerge_xv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -676,7 +673,7 @@ ; CHECK-LABEL: vmerge_iv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -688,7 +685,7 @@ ; CHECK-LABEL: vmerge_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmerge.vvm v16, v20, v16, v0 +; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -698,7 +695,7 @@ ; CHECK-LABEL: vmerge_xv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -710,7 +707,7 @@ ; CHECK-LABEL: vmerge_iv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -721,9 +718,8 @@ define @vmerge_vv_nxv8i64( %va, %vb, %cond) { ; CHECK-LABEL: vmerge_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: ret %vc = select %cond, %va, %vb ret %vc @@ -733,7 +729,7 @@ ; CHECK-LABEL: vmerge_xv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vmerge.vxm v16, v16, a0, v0 +; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -745,7 +741,7 @@ ; CHECK-LABEL: vmerge_iv_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vmerge.vim v16, v16, 3, v0 +; CHECK-NEXT: vmerge.vim v8, v8, 3, v0 ; CHECK-NEXT: ret %head = insertelement undef, i64 3, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll @@ -9,8 +9,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv1i32.nxv1i8( @@ -30,7 +30,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v17, v0.t +; CHECK-NEXT: vsext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8( @@ -50,8 +50,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv2i32.nxv2i8( @@ -71,7 +71,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v17, v0.t +; CHECK-NEXT: vsext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8( @@ -91,8 +91,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vsext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv4i32.nxv4i8( @@ -112,7 +112,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v18, v0.t +; CHECK-NEXT: vsext.vf4 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv4i32.nxv4i8( @@ -132,8 +132,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vsext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv8i32.nxv8i8( @@ -153,7 +153,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v20, v0.t +; CHECK-NEXT: vsext.vf4 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv8i32.nxv8i8( @@ -173,8 +173,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vsext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv16i32.nxv16i8( @@ -193,10 +193,8 @@ define @intrinsic_vsext_mask_vf4_nxv16i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v26, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsext.vf4 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv16i32.nxv16i8( @@ -216,8 +214,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv1i32.nxv1i16( @@ -237,7 +235,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i16( @@ -257,8 +255,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv2i32.nxv2i16( @@ -278,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i16( @@ -298,8 +296,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv4i32.nxv4i16( @@ -319,7 +317,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v18, v0.t +; CHECK-NEXT: vsext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv4i32.nxv4i16( @@ -339,8 +337,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv8i32.nxv8i16( @@ -360,7 +358,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v20, v0.t +; CHECK-NEXT: vsext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv8i32.nxv8i16( @@ -380,8 +378,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv16i32.nxv16i16( @@ -400,10 +398,8 @@ define @intrinsic_vsext_mask_vf2_nxv16i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv16i32.nxv16i16( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv1i16.nxv1i8( @@ -444,7 +440,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv1i16.nxv1i8( @@ -464,8 +460,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv2i16.nxv2i8( @@ -485,7 +481,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv2i16.nxv2i8( @@ -505,8 +501,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv4i16.nxv4i8( @@ -526,7 +522,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv4i16.nxv4i8( @@ -546,8 +542,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv8i16.nxv8i8( @@ -567,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v18, v0.t +; CHECK-NEXT: vsext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv8i16.nxv8i8( @@ -587,8 +583,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv16i16.nxv16i8( @@ -608,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v20, v0.t +; CHECK-NEXT: vsext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv16i16.nxv16i8( @@ -628,8 +624,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv32i16.nxv32i8( @@ -648,10 +644,8 @@ define @intrinsic_vsext_mask_vf2_nxv32i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv32i16.nxv32i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll @@ -9,8 +9,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vsext.vf8 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf8 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv1i64.nxv1i8( @@ -30,7 +30,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vsext.vf8 v16, v17, v0.t +; CHECK-NEXT: vsext.vf8 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i8( @@ -50,8 +50,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vsext.vf8 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf8 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv2i64.nxv2i8( @@ -71,7 +71,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vsext.vf8 v16, v18, v0.t +; CHECK-NEXT: vsext.vf8 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i8( @@ -91,8 +91,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vsext.vf8 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf8 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv4i64.nxv4i8( @@ -112,7 +112,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vsext.vf8 v16, v20, v0.t +; CHECK-NEXT: vsext.vf8 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i8( @@ -132,8 +132,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf8_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vsext.vf8 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf8 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv8i64.nxv8i8( @@ -152,10 +152,8 @@ define @intrinsic_vsext_mask_vf8_nxv8i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsext_mask_vf8_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vsext.vf8 v16, v25, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vsext.vf8 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i8( @@ -175,8 +173,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv1i64.nxv1i16( @@ -196,7 +194,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v17, v0.t +; CHECK-NEXT: vsext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i16( @@ -216,8 +214,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vsext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv2i64.nxv2i16( @@ -237,7 +235,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v18, v0.t +; CHECK-NEXT: vsext.vf4 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i16( @@ -257,8 +255,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vsext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv4i64.nxv4i16( @@ -278,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v20, v0.t +; CHECK-NEXT: vsext.vf4 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i16( @@ -298,8 +296,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vsext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv8i64.nxv8i16( @@ -318,10 +316,8 @@ define @intrinsic_vsext_mask_vf4_nxv8i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v26, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vsext.vf4 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i16( @@ -341,8 +337,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv1i32.nxv1i8( @@ -362,7 +358,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v17, v0.t +; CHECK-NEXT: vsext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i8( @@ -382,8 +378,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vsext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv2i32.nxv2i8( @@ -403,7 +399,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v17, v0.t +; CHECK-NEXT: vsext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i8( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vsext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv4i32.nxv4i8( @@ -444,7 +440,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v18, v0.t +; CHECK-NEXT: vsext.vf4 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv4i32.nxv4i8( @@ -464,8 +460,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vsext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv8i32.nxv8i8( @@ -485,7 +481,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v20, v0.t +; CHECK-NEXT: vsext.vf4 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv8i32.nxv8i8( @@ -505,8 +501,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf4_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vsext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv16i32.nxv16i8( @@ -525,10 +521,8 @@ define @intrinsic_vsext_mask_vf4_nxv16i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vsext.vf4 v16, v26, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsext.vf4 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv16i32.nxv16i8( @@ -548,8 +542,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv1i64.nxv1i32( @@ -569,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv1i64.nxv1i32( @@ -589,8 +583,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv2i64.nxv2i32( @@ -610,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v18, v0.t +; CHECK-NEXT: vsext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv2i64.nxv2i32( @@ -630,8 +624,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv4i64.nxv4i32( @@ -651,7 +645,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v20, v0.t +; CHECK-NEXT: vsext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv4i64.nxv4i32( @@ -671,8 +665,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv8i64.nxv8i32( @@ -691,10 +685,8 @@ define @intrinsic_vsext_mask_vf2_nxv8i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vsext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv8i64.nxv8i32( @@ -714,8 +706,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv1i32.nxv1i16( @@ -735,7 +727,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv1i32.nxv1i16( @@ -755,8 +747,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv2i32.nxv2i16( @@ -776,7 +768,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv2i32.nxv2i16( @@ -796,8 +788,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv4i32.nxv4i16( @@ -817,7 +809,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v18, v0.t +; CHECK-NEXT: vsext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv4i32.nxv4i16( @@ -837,8 +829,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv8i32.nxv8i16( @@ -858,7 +850,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v20, v0.t +; CHECK-NEXT: vsext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv8i32.nxv8i16( @@ -878,8 +870,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv16i32.nxv16i16( @@ -898,10 +890,8 @@ define @intrinsic_vsext_mask_vf2_nxv16i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv16i32.nxv16i16( @@ -921,8 +911,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv1i16.nxv1i8( @@ -942,7 +932,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv1i16.nxv1i8( @@ -962,8 +952,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv2i16.nxv2i8( @@ -983,7 +973,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv2i16.nxv2i8( @@ -1003,8 +993,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vsext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vsext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv4i16.nxv4i8( @@ -1024,7 +1014,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v17, v0.t +; CHECK-NEXT: vsext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv4i16.nxv4i8( @@ -1044,8 +1034,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vsext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vsext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv8i16.nxv8i8( @@ -1065,7 +1055,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v18, v0.t +; CHECK-NEXT: vsext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv8i16.nxv8i8( @@ -1085,8 +1075,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vsext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vsext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv16i16.nxv16i8( @@ -1106,7 +1096,7 @@ ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v20, v0.t +; CHECK-NEXT: vsext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv16i16.nxv16i8( @@ -1126,8 +1116,8 @@ ; CHECK-LABEL: intrinsic_vsext_vf2_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vsext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vsext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.nxv32i16.nxv32i8( @@ -1146,10 +1136,8 @@ define @intrinsic_vsext_mask_vf2_nxv32i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vsext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vsext.mask.nxv32i16.nxv32i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -41,7 +41,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -53,7 +53,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -65,7 +65,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -77,7 +77,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -89,7 +89,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -101,7 +101,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -113,7 +113,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -125,7 +125,7 @@ ; CHECK-LABEL: vshl_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -137,7 +137,7 @@ ; CHECK-LABEL: vshl_vx_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -149,7 +149,7 @@ ; CHECK-LABEL: vshl_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -161,7 +161,7 @@ ; CHECK-LABEL: vshl_vx_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -173,7 +173,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -185,7 +185,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -209,7 +209,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -221,7 +221,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -233,7 +233,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +245,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,7 +257,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -269,7 +269,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +281,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -293,7 +293,7 @@ ; CHECK-LABEL: vshl_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -305,7 +305,7 @@ ; CHECK-LABEL: vshl_vx_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -317,7 +317,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -329,7 +329,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -341,7 +341,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -353,7 +353,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -365,7 +365,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -377,7 +377,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -389,7 +389,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -401,7 +401,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,7 +413,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,7 +425,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -444,7 +444,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vsll.vv v16, v16, v25 +; CHECK-NEXT: vsll.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -456,7 +456,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -469,7 +469,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +488,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vsll.vv v16, v16, v26 +; CHECK-NEXT: vsll.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -500,7 +500,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -513,7 +513,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -528,11 +528,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vsll.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vsll.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -544,7 +544,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -557,7 +557,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -569,14 +569,14 @@ ; CHECK-LABEL: vshl_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vsll.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vsll.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -588,7 +588,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,7 +601,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -41,7 +41,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -53,7 +53,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -65,7 +65,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -77,7 +77,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -89,7 +89,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -101,7 +101,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -113,7 +113,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -125,7 +125,7 @@ ; CHECK-LABEL: vshl_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -137,7 +137,7 @@ ; CHECK-LABEL: vshl_vx_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -149,7 +149,7 @@ ; CHECK-LABEL: vshl_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -161,7 +161,7 @@ ; CHECK-LABEL: vshl_vx_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -173,7 +173,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -185,7 +185,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -209,7 +209,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -221,7 +221,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -233,7 +233,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +245,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,7 +257,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -269,7 +269,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +281,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -293,7 +293,7 @@ ; CHECK-LABEL: vshl_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -305,7 +305,7 @@ ; CHECK-LABEL: vshl_vx_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 6 +; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -317,7 +317,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -329,7 +329,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -341,7 +341,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -353,7 +353,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -365,7 +365,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -377,7 +377,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -389,7 +389,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -401,7 +401,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,7 +413,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,7 +425,7 @@ ; CHECK-LABEL: vshl_vx_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -437,7 +437,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +449,7 @@ ; CHECK-LABEL: vshl_vx_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +462,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -474,7 +474,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -486,7 +486,7 @@ ; CHECK-LABEL: vshl_vx_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -499,7 +499,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -511,7 +511,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -523,7 +523,7 @@ ; CHECK-LABEL: vshl_vx_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -536,7 +536,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -548,7 +548,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -560,7 +560,7 @@ ; CHECK-LABEL: vshl_vx_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsll.vi v16, v16, 31 +; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -573,7 +573,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsll.vx v16, v16, a0 +; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv1i8.i8( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv1i8.i8( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv2i8.i8( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv2i8.i8( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv4i8.i8( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv4i8.i8( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv8i8.i8( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv8i8.i8( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv16i8.i8( @@ -208,7 +208,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv16i8.i8( @@ -230,7 +230,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv32i8.i8( @@ -252,7 +252,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv32i8.i8( @@ -274,7 +274,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv64i8.i8( @@ -295,10 +295,8 @@ define @intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m8,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv64i8.i8( @@ -320,7 +318,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv1i16.i16( @@ -342,7 +340,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv1i16.i16( @@ -364,7 +362,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv2i16.i16( @@ -386,7 +384,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv2i16.i16( @@ -408,7 +406,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv4i16.i16( @@ -430,7 +428,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv4i16.i16( @@ -452,7 +450,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv8i16.i16( @@ -474,7 +472,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv8i16.i16( @@ -496,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv16i16.i16( @@ -518,7 +516,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv16i16.i16( @@ -540,7 +538,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv32i16.i16( @@ -561,10 +559,8 @@ define @intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv32i16.i16( @@ -586,7 +582,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv1i32.i32( @@ -608,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv1i32.i32( @@ -630,7 +626,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv2i32.i32( @@ -652,7 +648,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv2i32.i32( @@ -674,7 +670,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv4i32.i32( @@ -696,7 +692,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv4i32.i32( @@ -718,7 +714,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv8i32.i32( @@ -740,7 +736,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv8i32.i32( @@ -762,7 +758,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv16i32.i32( @@ -783,10 +779,8 @@ define @intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv16i32.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll @@ -10,7 +10,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv1i8.i8( @@ -32,7 +32,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv1i8.i8( @@ -54,7 +54,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv2i8.i8( @@ -76,7 +76,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv2i8.i8( @@ -98,7 +98,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv4i8.i8( @@ -120,7 +120,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv4i8.i8( @@ -142,7 +142,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv8i8.i8( @@ -164,7 +164,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv8i8.i8( @@ -186,7 +186,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv16i8.i8( @@ -208,7 +208,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv16i8.i8( @@ -230,7 +230,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv32i8.i8( @@ -252,7 +252,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv32i8.i8( @@ -274,7 +274,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv64i8.i8( @@ -295,10 +295,8 @@ define @intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m8,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv64i8.i8( @@ -320,7 +318,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv1i16.i16( @@ -342,7 +340,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv1i16.i16( @@ -364,7 +362,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv2i16.i16( @@ -386,7 +384,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv2i16.i16( @@ -408,7 +406,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv4i16.i16( @@ -430,7 +428,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv4i16.i16( @@ -452,7 +450,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv8i16.i16( @@ -474,7 +472,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv8i16.i16( @@ -496,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv16i16.i16( @@ -518,7 +516,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv16i16.i16( @@ -540,7 +538,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv32i16.i16( @@ -561,10 +559,8 @@ define @intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv32i16.i16( @@ -586,7 +582,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv1i32.i32( @@ -608,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv1i32.i32( @@ -630,7 +626,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv2i32.i32( @@ -652,7 +648,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv2i32.i32( @@ -674,7 +670,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv4i32.i32( @@ -696,7 +692,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv4i32.i32( @@ -718,7 +714,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv8i32.i32( @@ -740,7 +736,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv8i32.i32( @@ -762,7 +758,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv16i32.i32( @@ -783,10 +779,8 @@ define @intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv16i32.i32( @@ -808,7 +802,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv1i64.i64( @@ -830,7 +824,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv1i64.i64( @@ -852,7 +846,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv2i64.i64( @@ -874,7 +868,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv2i64.i64( @@ -896,7 +890,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv4i64.i64( @@ -918,7 +912,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv4i64.i64( @@ -940,7 +934,7 @@ ; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vslide1down.vx v16, v16, a0 +; CHECK-NEXT: vslide1down.vx v8, v8, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.nxv8i64.i64( @@ -961,10 +955,8 @@ define @intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vslide1down.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1down.mask.nxv8i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll @@ -10,8 +10,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv1i8.i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll @@ -10,8 +10,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv1i8.i8( @@ -33,7 +33,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv1i8.i8( @@ -55,8 +55,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv2i8.i8( @@ -78,7 +78,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv2i8.i8( @@ -100,8 +100,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv4i8.i8( @@ -123,7 +123,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv4i8.i8( @@ -145,8 +145,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv8i8.i8( @@ -168,7 +168,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv8i8.i8( @@ -190,8 +190,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vslide1up.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vslide1up.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv16i8.i8( @@ -213,7 +213,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv16i8.i8( @@ -235,8 +235,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vslide1up.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vslide1up.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv32i8.i8( @@ -258,7 +258,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv32i8.i8( @@ -280,8 +280,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu -; CHECK-NEXT: vslide1up.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vslide1up.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv64i8.i8( @@ -302,10 +302,8 @@ define @intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m8,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv64i8.i8( @@ -327,8 +325,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv1i16.i16( @@ -350,7 +348,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv1i16.i16( @@ -372,8 +370,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv2i16.i16( @@ -395,7 +393,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv2i16.i16( @@ -417,8 +415,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv4i16.i16( @@ -440,7 +438,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv4i16.i16( @@ -462,8 +460,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vslide1up.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vslide1up.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv8i16.i16( @@ -485,7 +483,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv8i16.i16( @@ -507,8 +505,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vslide1up.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vslide1up.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv16i16.i16( @@ -530,7 +528,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv16i16.i16( @@ -552,8 +550,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu -; CHECK-NEXT: vslide1up.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vslide1up.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv32i16.i16( @@ -574,10 +572,8 @@ define @intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m8,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv32i16.i16( @@ -599,8 +595,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv1i32.i32( @@ -622,7 +618,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv1i32.i32( @@ -644,8 +640,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv2i32.i32( @@ -667,7 +663,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv2i32.i32( @@ -689,8 +685,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vslide1up.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vslide1up.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv4i32.i32( @@ -712,7 +708,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv4i32.i32( @@ -734,8 +730,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vslide1up.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vslide1up.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv8i32.i32( @@ -757,7 +753,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv8i32.i32( @@ -779,8 +775,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu -; CHECK-NEXT: vslide1up.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vslide1up.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv16i32.i32( @@ -801,10 +797,8 @@ define @intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m8,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv16i32.i32( @@ -826,8 +820,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vslide1up.vx v25, v16, a0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vslide1up.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv1i64.i64( @@ -849,7 +843,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv1i64.i64( @@ -871,8 +865,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vslide1up.vx v26, v16, a0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vslide1up.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv2i64.i64( @@ -894,7 +888,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv2i64.i64( @@ -916,8 +910,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vslide1up.vx v28, v16, a0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vslide1up.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv4i64.i64( @@ -939,7 +933,7 @@ ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv4i64.i64( @@ -961,8 +955,8 @@ ; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu -; CHECK-NEXT: vslide1up.vx v8, v16, a0 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vslide1up.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.nxv8i64.i64( @@ -983,10 +977,8 @@ define @intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e64,m8,tu,mu -; CHECK-NEXT: vslide1up.vx v16, v8, a1, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslide1up.mask.nxv8i64.i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1i8( @@ -51,7 +51,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1i8( @@ -67,7 +67,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1i8( @@ -90,7 +90,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2i8( @@ -113,7 +113,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2i8( @@ -130,7 +130,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2i8( @@ -146,7 +146,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2i8( @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4i8( @@ -192,7 +192,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4i8( @@ -209,7 +209,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4i8( @@ -225,7 +225,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4i8( @@ -248,7 +248,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8i8( @@ -271,7 +271,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8i8( @@ -288,7 +288,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8i8( @@ -304,7 +304,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8i8( @@ -327,7 +327,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0 +; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv16i8( @@ -350,7 +350,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv16i8( @@ -367,7 +367,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9 +; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv16i8( @@ -383,7 +383,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv16i8( @@ -406,7 +406,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0 +; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv32i8( @@ -429,7 +429,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv32i8( @@ -446,7 +446,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9 +; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv32i8( @@ -462,7 +462,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv32i8( @@ -485,7 +485,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1i16( @@ -508,7 +508,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1i16( @@ -525,7 +525,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1i16( @@ -541,7 +541,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1i16( @@ -564,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2i16( @@ -587,7 +587,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2i16( @@ -604,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2i16( @@ -620,7 +620,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2i16( @@ -643,7 +643,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4i16( @@ -666,7 +666,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4i16( @@ -683,7 +683,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4i16( @@ -699,7 +699,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4i16( @@ -722,7 +722,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0 +; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8i16( @@ -745,7 +745,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8i16( @@ -762,7 +762,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9 +; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8i16( @@ -778,7 +778,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8i16( @@ -801,7 +801,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0 +; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv16i16( @@ -824,7 +824,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv16i16( @@ -841,7 +841,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9 +; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv16i16( @@ -857,7 +857,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv16i16( @@ -880,7 +880,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1i32( @@ -903,7 +903,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1i32( @@ -920,7 +920,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1i32( @@ -936,7 +936,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1i32( @@ -959,7 +959,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2i32( @@ -982,7 +982,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2i32( @@ -999,7 +999,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2i32( @@ -1015,7 +1015,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2i32( @@ -1038,7 +1038,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0 +; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4i32( @@ -1061,7 +1061,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4i32( @@ -1078,7 +1078,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9 +; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4i32( @@ -1094,7 +1094,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4i32( @@ -1117,7 +1117,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0 +; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8i32( @@ -1140,7 +1140,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8i32( @@ -1157,7 +1157,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9 +; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8i32( @@ -1173,7 +1173,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8i32( @@ -1196,7 +1196,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1f16( @@ -1219,7 +1219,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1f16( @@ -1236,7 +1236,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1f16( @@ -1252,7 +1252,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1f16( @@ -1275,7 +1275,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2f16( @@ -1298,7 +1298,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2f16( @@ -1315,7 +1315,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2f16( @@ -1331,7 +1331,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2f16( @@ -1354,7 +1354,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4f16( @@ -1377,7 +1377,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4f16( @@ -1394,7 +1394,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4f16( @@ -1410,7 +1410,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4f16( @@ -1433,7 +1433,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0 +; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8f16( @@ -1456,7 +1456,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8f16( @@ -1473,7 +1473,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9 +; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8f16( @@ -1489,7 +1489,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8f16( @@ -1512,7 +1512,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0 +; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv16f16( @@ -1535,7 +1535,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv16f16( @@ -1552,7 +1552,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9 +; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv16f16( @@ -1568,7 +1568,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv16f16( @@ -1591,7 +1591,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1f32( @@ -1614,7 +1614,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1f32( @@ -1631,7 +1631,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1f32( @@ -1647,7 +1647,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1f32( @@ -1670,7 +1670,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2f32( @@ -1693,7 +1693,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2f32( @@ -1710,7 +1710,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2f32( @@ -1726,7 +1726,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2f32( @@ -1749,7 +1749,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0 +; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4f32( @@ -1772,7 +1772,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4f32( @@ -1789,7 +1789,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9 +; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4f32( @@ -1805,7 +1805,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4f32( @@ -1828,7 +1828,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0 +; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8f32( @@ -1851,7 +1851,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8f32( @@ -1868,7 +1868,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9 +; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv8f32( @@ -1884,7 +1884,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv8f32( @@ -1907,7 +1907,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0 +; CHECK-NEXT: vslidedown.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1f64( @@ -1930,7 +1930,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1f64( @@ -1947,7 +1947,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9 +; CHECK-NEXT: vslidedown.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv1f64( @@ -1963,7 +1963,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv1f64( @@ -1986,7 +1986,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0 +; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2f64( @@ -2009,7 +2009,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2f64( @@ -2026,7 +2026,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9 +; CHECK-NEXT: vslidedown.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv2f64( @@ -2042,7 +2042,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv2f64( @@ -2065,7 +2065,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0 +; CHECK-NEXT: vslidedown.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4f64( @@ -2088,7 +2088,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vslidedown.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4f64( @@ -2105,7 +2105,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9 +; CHECK-NEXT: vslidedown.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.nxv4f64( @@ -2121,7 +2121,7 @@ ; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vslidedown.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslidedown.mask.nxv4f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vslidedown.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vslidedown_vx_nxv1i8_nxv1i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1i8( %0, %1, @@ -43,10 +48,12 @@ } define @intrinsic_vslidedown_vi_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv1i8( %0, %1, @@ -57,10 +64,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1i8( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vslidedown_vx_nxv2i8_nxv2i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv2i8( %0, %1, @@ -99,10 +110,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2i8( %0, %1, @@ -114,10 +127,12 @@ } define @intrinsic_vslidedown_vi_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv2i8( %0, %1, @@ -128,10 +143,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2i8( %0, %1, @@ -149,10 +166,12 @@ i64); define @intrinsic_vslidedown_vx_nxv4i8_nxv4i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv4i8( %0, %1, @@ -170,10 +189,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4i8( %0, %1, @@ -185,10 +206,12 @@ } define @intrinsic_vslidedown_vi_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv4i8( %0, %1, @@ -199,10 +222,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4i8( %0, %1, @@ -220,10 +245,12 @@ i64); define @intrinsic_vslidedown_vx_nxv8i8_nxv8i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv8i8( %0, %1, @@ -241,10 +268,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8i8( %0, %1, @@ -256,10 +285,12 @@ } define @intrinsic_vslidedown_vi_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv8i8( %0, %1, @@ -270,10 +301,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8i8( %0, %1, @@ -291,10 +324,12 @@ i64); define @intrinsic_vslidedown_vx_nxv16i8_nxv16i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv16i8( %0, %1, @@ -312,10 +347,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv16i8( %0, %1, @@ -327,10 +364,12 @@ } define @intrinsic_vslidedown_vi_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv16i8( %0, %1, @@ -341,10 +380,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv16i8( %0, %1, @@ -362,10 +403,12 @@ i64); define @intrinsic_vslidedown_vx_nxv32i8_nxv32i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv32i8( %0, %1, @@ -383,10 +426,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv32i8( %0, %1, @@ -398,10 +443,12 @@ } define @intrinsic_vslidedown_vi_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv32i8( %0, %1, @@ -412,10 +459,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv32i8( %0, %1, @@ -433,10 +482,12 @@ i64); define @intrinsic_vslidedown_vx_nxv1i16_nxv1i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv1i16( %0, %1, @@ -454,10 +505,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1i16( %0, %1, @@ -469,10 +522,12 @@ } define @intrinsic_vslidedown_vi_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv1i16( %0, %1, @@ -483,10 +538,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1i16( %0, %1, @@ -504,10 +561,12 @@ i64); define @intrinsic_vslidedown_vx_nxv2i16_nxv2i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv2i16( %0, %1, @@ -525,10 +584,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2i16( %0, %1, @@ -540,10 +601,12 @@ } define @intrinsic_vslidedown_vi_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv2i16( %0, %1, @@ -554,10 +617,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2i16( %0, %1, @@ -575,10 +640,12 @@ i64); define @intrinsic_vslidedown_vx_nxv4i16_nxv4i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv4i16( %0, %1, @@ -596,10 +663,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4i16( %0, %1, @@ -611,10 +680,12 @@ } define @intrinsic_vslidedown_vi_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv4i16( %0, %1, @@ -625,10 +696,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4i16( %0, %1, @@ -646,10 +719,12 @@ i64); define @intrinsic_vslidedown_vx_nxv8i16_nxv8i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv8i16( %0, %1, @@ -667,10 +742,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8i16( %0, %1, @@ -682,10 +759,12 @@ } define @intrinsic_vslidedown_vi_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv8i16( %0, %1, @@ -696,10 +775,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8i16( %0, %1, @@ -717,10 +798,12 @@ i64); define @intrinsic_vslidedown_vx_nxv16i16_nxv16i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv16i16( %0, %1, @@ -738,10 +821,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv16i16( %0, %1, @@ -753,10 +838,12 @@ } define @intrinsic_vslidedown_vi_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv16i16( %0, %1, @@ -767,10 +854,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv16i16( %0, %1, @@ -788,10 +877,12 @@ i64); define @intrinsic_vslidedown_vx_nxv1i32_nxv1i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv1i32( %0, %1, @@ -809,10 +900,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1i32( %0, %1, @@ -824,10 +917,12 @@ } define @intrinsic_vslidedown_vi_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv1i32( %0, %1, @@ -838,10 +933,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1i32( %0, %1, @@ -859,10 +956,12 @@ i64); define @intrinsic_vslidedown_vx_nxv2i32_nxv2i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv2i32( %0, %1, @@ -880,10 +979,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2i32( %0, %1, @@ -895,10 +996,12 @@ } define @intrinsic_vslidedown_vi_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv2i32( %0, %1, @@ -909,10 +1012,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2i32( %0, %1, @@ -930,10 +1035,12 @@ i64); define @intrinsic_vslidedown_vx_nxv4i32_nxv4i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv4i32( %0, %1, @@ -951,10 +1058,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4i32( %0, %1, @@ -966,10 +1075,12 @@ } define @intrinsic_vslidedown_vi_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv4i32( %0, %1, @@ -980,10 +1091,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4i32( %0, %1, @@ -1001,10 +1114,12 @@ i64); define @intrinsic_vslidedown_vx_nxv8i32_nxv8i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv8i32( %0, %1, @@ -1022,10 +1137,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8i32( %0, %1, @@ -1037,10 +1154,12 @@ } define @intrinsic_vslidedown_vi_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv8i32( %0, %1, @@ -1051,10 +1170,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8i32( %0, %1, @@ -1072,10 +1193,12 @@ i64); define @intrinsic_vslidedown_vx_nxv1i64_nxv1i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv1i64( %0, %1, @@ -1093,10 +1216,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1i64( %0, %1, @@ -1108,10 +1233,12 @@ } define @intrinsic_vslidedown_vi_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv1i64( %0, %1, @@ -1122,10 +1249,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1i64( %0, %1, @@ -1143,10 +1272,12 @@ i64); define @intrinsic_vslidedown_vx_nxv2i64_nxv2i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv2i64( %0, %1, @@ -1164,10 +1295,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2i64( %0, %1, @@ -1179,10 +1312,12 @@ } define @intrinsic_vslidedown_vi_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv2i64( %0, %1, @@ -1193,10 +1328,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2i64( %0, %1, @@ -1214,10 +1351,12 @@ i64); define @intrinsic_vslidedown_vx_nxv4i64_nxv4i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv4i64( %0, %1, @@ -1235,10 +1374,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4i64( %0, %1, @@ -1250,10 +1391,12 @@ } define @intrinsic_vslidedown_vi_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv4i64( %0, %1, @@ -1264,10 +1407,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4i64( %0, %1, @@ -1285,10 +1430,12 @@ i64); define @intrinsic_vslidedown_vx_nxv1f16_nxv1f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv1f16( %0, %1, @@ -1306,10 +1453,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1f16( %0, %1, @@ -1321,10 +1470,12 @@ } define @intrinsic_vslidedown_vi_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv1f16( %0, %1, @@ -1335,10 +1486,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1f16( %0, %1, @@ -1356,10 +1509,12 @@ i64); define @intrinsic_vslidedown_vx_nxv2f16_nxv2f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv2f16( %0, %1, @@ -1377,10 +1532,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2f16( %0, %1, @@ -1392,10 +1549,12 @@ } define @intrinsic_vslidedown_vi_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv2f16( %0, %1, @@ -1406,10 +1565,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2f16( %0, %1, @@ -1427,10 +1588,12 @@ i64); define @intrinsic_vslidedown_vx_nxv4f16_nxv4f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv4f16( %0, %1, @@ -1448,10 +1611,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4f16( %0, %1, @@ -1463,10 +1628,12 @@ } define @intrinsic_vslidedown_vi_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv4f16( %0, %1, @@ -1477,10 +1644,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4f16( %0, %1, @@ -1498,10 +1667,12 @@ i64); define @intrinsic_vslidedown_vx_nxv8f16_nxv8f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv8f16( %0, %1, @@ -1519,10 +1690,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8f16( %0, %1, @@ -1534,10 +1707,12 @@ } define @intrinsic_vslidedown_vi_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv8f16( %0, %1, @@ -1548,10 +1723,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8f16( %0, %1, @@ -1569,10 +1746,12 @@ i64); define @intrinsic_vslidedown_vx_nxv16f16_nxv16f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv16f16( %0, %1, @@ -1590,10 +1769,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv16f16( %0, %1, @@ -1605,10 +1786,12 @@ } define @intrinsic_vslidedown_vi_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv16f16( %0, %1, @@ -1619,10 +1802,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv16f16( %0, %1, @@ -1640,10 +1825,12 @@ i64); define @intrinsic_vslidedown_vx_nxv1f32_nxv1f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv1f32( %0, %1, @@ -1661,10 +1848,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1f32( %0, %1, @@ -1676,10 +1865,12 @@ } define @intrinsic_vslidedown_vi_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv1f32( %0, %1, @@ -1690,10 +1881,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1f32( %0, %1, @@ -1711,10 +1904,12 @@ i64); define @intrinsic_vslidedown_vx_nxv2f32_nxv2f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv2f32( %0, %1, @@ -1732,10 +1927,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2f32( %0, %1, @@ -1747,10 +1944,12 @@ } define @intrinsic_vslidedown_vi_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv2f32( %0, %1, @@ -1761,10 +1960,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2f32( %0, %1, @@ -1782,10 +1983,12 @@ i64); define @intrinsic_vslidedown_vx_nxv4f32_nxv4f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv4f32( %0, %1, @@ -1803,10 +2006,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4f32( %0, %1, @@ -1818,10 +2023,12 @@ } define @intrinsic_vslidedown_vi_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv4f32( %0, %1, @@ -1832,10 +2039,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4f32( %0, %1, @@ -1853,10 +2062,12 @@ i64); define @intrinsic_vslidedown_vx_nxv8f32_nxv8f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv8f32( %0, %1, @@ -1874,10 +2085,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8f32( %0, %1, @@ -1889,10 +2102,12 @@ } define @intrinsic_vslidedown_vi_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv8f32( %0, %1, @@ -1903,10 +2118,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv8f32( %0, %1, @@ -1924,10 +2141,12 @@ i64); define @intrinsic_vslidedown_vx_nxv1f64_nxv1f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv1f64( %0, %1, @@ -1945,10 +2164,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1f64( %0, %1, @@ -1960,10 +2181,12 @@ } define @intrinsic_vslidedown_vi_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv1f64( %0, %1, @@ -1974,10 +2197,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv1f64( %0, %1, @@ -1995,10 +2220,12 @@ i64); define @intrinsic_vslidedown_vx_nxv2f64_nxv2f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv2f64( %0, %1, @@ -2016,10 +2243,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2f64( %0, %1, @@ -2031,10 +2260,12 @@ } define @intrinsic_vslidedown_vi_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv2f64( %0, %1, @@ -2045,10 +2276,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv2f64( %0, %1, @@ -2066,10 +2299,12 @@ i64); define @intrinsic_vslidedown_vx_nxv4f64_nxv4f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslidedown.nxv4f64( %0, %1, @@ -2087,10 +2322,12 @@ i64); define @intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vslidedown.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslidedown.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4f64( %0, %1, @@ -2102,10 +2339,12 @@ } define @intrinsic_vslidedown_vi_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslidedown.nxv4f64( %0, %1, @@ -2116,10 +2355,12 @@ } define @intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vslidedown.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslidedown.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslidedown.mask.nxv4f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1i8( @@ -51,7 +51,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1i8( @@ -67,7 +67,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1i8( @@ -90,7 +90,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2i8( @@ -113,7 +113,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2i8( @@ -130,7 +130,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2i8( @@ -146,7 +146,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2i8( @@ -169,7 +169,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4i8( @@ -192,7 +192,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4i8( @@ -209,7 +209,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4i8( @@ -225,7 +225,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4i8( @@ -248,7 +248,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8i8( @@ -271,7 +271,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8i8( @@ -288,7 +288,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8i8( @@ -304,7 +304,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8i8( @@ -327,7 +327,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv16i8( @@ -350,7 +350,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv16i8( @@ -367,7 +367,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9 +; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv16i8( @@ -383,7 +383,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv16i8( @@ -406,7 +406,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv32i8( @@ -429,7 +429,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv32i8( @@ -446,7 +446,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9 +; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv32i8( @@ -462,7 +462,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv32i8( @@ -485,7 +485,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1i16( @@ -508,7 +508,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1i16( @@ -525,7 +525,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1i16( @@ -541,7 +541,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1i16( @@ -564,7 +564,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2i16( @@ -587,7 +587,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2i16( @@ -604,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2i16( @@ -620,7 +620,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2i16( @@ -643,7 +643,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4i16( @@ -666,7 +666,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4i16( @@ -683,7 +683,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4i16( @@ -699,7 +699,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4i16( @@ -722,7 +722,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8i16( @@ -745,7 +745,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8i16( @@ -762,7 +762,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9 +; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8i16( @@ -778,7 +778,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8i16( @@ -801,7 +801,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv16i16( @@ -824,7 +824,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv16i16( @@ -841,7 +841,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9 +; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv16i16( @@ -857,7 +857,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv16i16( @@ -880,7 +880,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1i32( @@ -903,7 +903,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1i32( @@ -920,7 +920,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1i32( @@ -936,7 +936,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1i32( @@ -959,7 +959,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2i32( @@ -982,7 +982,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2i32( @@ -999,7 +999,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2i32( @@ -1015,7 +1015,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2i32( @@ -1038,7 +1038,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4i32( @@ -1061,7 +1061,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4i32( @@ -1078,7 +1078,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9 +; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4i32( @@ -1094,7 +1094,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4i32( @@ -1117,7 +1117,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8i32( @@ -1140,7 +1140,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8i32( @@ -1157,7 +1157,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9 +; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8i32( @@ -1173,7 +1173,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8i32( @@ -1196,7 +1196,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1f16( @@ -1219,7 +1219,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1f16( @@ -1236,7 +1236,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1f16( @@ -1252,7 +1252,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1f16( @@ -1275,7 +1275,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2f16( @@ -1298,7 +1298,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2f16( @@ -1315,7 +1315,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2f16( @@ -1331,7 +1331,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2f16( @@ -1354,7 +1354,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4f16( @@ -1377,7 +1377,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4f16( @@ -1394,7 +1394,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4f16( @@ -1410,7 +1410,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4f16( @@ -1433,7 +1433,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8f16( @@ -1456,7 +1456,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8f16( @@ -1473,7 +1473,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9 +; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8f16( @@ -1489,7 +1489,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8f16( @@ -1512,7 +1512,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv16f16( @@ -1535,7 +1535,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv16f16( @@ -1552,7 +1552,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9 +; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv16f16( @@ -1568,7 +1568,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv16f16( @@ -1591,7 +1591,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1f32( @@ -1614,7 +1614,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1f32( @@ -1631,7 +1631,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1f32( @@ -1647,7 +1647,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1f32( @@ -1670,7 +1670,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2f32( @@ -1693,7 +1693,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2f32( @@ -1710,7 +1710,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2f32( @@ -1726,7 +1726,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2f32( @@ -1749,7 +1749,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4f32( @@ -1772,7 +1772,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4f32( @@ -1789,7 +1789,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9 +; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4f32( @@ -1805,7 +1805,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4f32( @@ -1828,7 +1828,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8f32( @@ -1851,7 +1851,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8f32( @@ -1868,7 +1868,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9 +; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv8f32( @@ -1884,7 +1884,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv8f32( @@ -1907,7 +1907,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0 +; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1f64( @@ -1930,7 +1930,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu -; CHECK-NEXT: vslideup.vx v16, v17, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1f64( @@ -1947,7 +1947,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9 +; CHECK-NEXT: vslideup.vi v8, v9, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv1f64( @@ -1963,7 +1963,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vslideup.vi v16, v17, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv1f64( @@ -1986,7 +1986,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0 +; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2f64( @@ -2009,7 +2009,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu -; CHECK-NEXT: vslideup.vx v16, v18, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2f64( @@ -2026,7 +2026,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9 +; CHECK-NEXT: vslideup.vi v8, v10, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv2f64( @@ -2042,7 +2042,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vslideup.vi v16, v18, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv2f64( @@ -2065,7 +2065,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0 +; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4f64( @@ -2088,7 +2088,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu -; CHECK-NEXT: vslideup.vx v16, v20, a0, v0.t +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4f64( @@ -2105,7 +2105,7 @@ ; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9 +; CHECK-NEXT: vslideup.vi v8, v12, 9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.nxv4f64( @@ -2121,7 +2121,7 @@ ; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vslideup.vi v16, v20, 9, v0.t +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vslideup.mask.nxv4f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vslideup.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vslideup_vx_nxv1i8_nxv1i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1i8( %0, %1, @@ -43,10 +48,12 @@ } define @intrinsic_vslideup_vi_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv1i8( %0, %1, @@ -57,10 +64,12 @@ } define @intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1i8( %0, %1, @@ -78,10 +87,12 @@ i64); define @intrinsic_vslideup_vx_nxv2i8_nxv2i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv2i8( %0, %1, @@ -99,10 +110,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2i8( %0, %1, @@ -114,10 +127,12 @@ } define @intrinsic_vslideup_vi_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv2i8( %0, %1, @@ -128,10 +143,12 @@ } define @intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2i8( %0, %1, @@ -149,10 +166,12 @@ i64); define @intrinsic_vslideup_vx_nxv4i8_nxv4i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv4i8( %0, %1, @@ -170,10 +189,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4i8( %0, %1, @@ -185,10 +206,12 @@ } define @intrinsic_vslideup_vi_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv4i8( %0, %1, @@ -199,10 +222,12 @@ } define @intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4i8( %0, %1, @@ -220,10 +245,12 @@ i64); define @intrinsic_vslideup_vx_nxv8i8_nxv8i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv8i8( %0, %1, @@ -241,10 +268,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8i8( %0, %1, @@ -256,10 +285,12 @@ } define @intrinsic_vslideup_vi_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv8i8( %0, %1, @@ -270,10 +301,12 @@ } define @intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8i8( %0, %1, @@ -291,10 +324,12 @@ i64); define @intrinsic_vslideup_vx_nxv16i8_nxv16i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv16i8( %0, %1, @@ -312,10 +347,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv16i8( %0, %1, @@ -327,10 +364,12 @@ } define @intrinsic_vslideup_vi_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv16i8( %0, %1, @@ -341,10 +380,12 @@ } define @intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv16i8( %0, %1, @@ -362,10 +403,12 @@ i64); define @intrinsic_vslideup_vx_nxv32i8_nxv32i8( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv32i8( %0, %1, @@ -383,10 +426,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv32i8( %0, %1, @@ -398,10 +443,12 @@ } define @intrinsic_vslideup_vi_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv32i8( %0, %1, @@ -412,10 +459,12 @@ } define @intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv32i8( %0, %1, @@ -433,10 +482,12 @@ i64); define @intrinsic_vslideup_vx_nxv1i16_nxv1i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv1i16( %0, %1, @@ -454,10 +505,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1i16( %0, %1, @@ -469,10 +522,12 @@ } define @intrinsic_vslideup_vi_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv1i16( %0, %1, @@ -483,10 +538,12 @@ } define @intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1i16( %0, %1, @@ -504,10 +561,12 @@ i64); define @intrinsic_vslideup_vx_nxv2i16_nxv2i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv2i16( %0, %1, @@ -525,10 +584,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2i16( %0, %1, @@ -540,10 +601,12 @@ } define @intrinsic_vslideup_vi_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv2i16( %0, %1, @@ -554,10 +617,12 @@ } define @intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2i16( %0, %1, @@ -575,10 +640,12 @@ i64); define @intrinsic_vslideup_vx_nxv4i16_nxv4i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv4i16( %0, %1, @@ -596,10 +663,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4i16( %0, %1, @@ -611,10 +680,12 @@ } define @intrinsic_vslideup_vi_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv4i16( %0, %1, @@ -625,10 +696,12 @@ } define @intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4i16( %0, %1, @@ -646,10 +719,12 @@ i64); define @intrinsic_vslideup_vx_nxv8i16_nxv8i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv8i16( %0, %1, @@ -667,10 +742,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8i16( %0, %1, @@ -682,10 +759,12 @@ } define @intrinsic_vslideup_vi_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv8i16( %0, %1, @@ -696,10 +775,12 @@ } define @intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8i16( %0, %1, @@ -717,10 +798,12 @@ i64); define @intrinsic_vslideup_vx_nxv16i16_nxv16i16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv16i16( %0, %1, @@ -738,10 +821,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv16i16( %0, %1, @@ -753,10 +838,12 @@ } define @intrinsic_vslideup_vi_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv16i16( %0, %1, @@ -767,10 +854,12 @@ } define @intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv16i16( %0, %1, @@ -788,10 +877,12 @@ i64); define @intrinsic_vslideup_vx_nxv1i32_nxv1i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv1i32( %0, %1, @@ -809,10 +900,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1i32( %0, %1, @@ -824,10 +917,12 @@ } define @intrinsic_vslideup_vi_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv1i32( %0, %1, @@ -838,10 +933,12 @@ } define @intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1i32( %0, %1, @@ -859,10 +956,12 @@ i64); define @intrinsic_vslideup_vx_nxv2i32_nxv2i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv2i32( %0, %1, @@ -880,10 +979,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2i32( %0, %1, @@ -895,10 +996,12 @@ } define @intrinsic_vslideup_vi_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv2i32( %0, %1, @@ -909,10 +1012,12 @@ } define @intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2i32( %0, %1, @@ -930,10 +1035,12 @@ i64); define @intrinsic_vslideup_vx_nxv4i32_nxv4i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv4i32( %0, %1, @@ -951,10 +1058,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4i32( %0, %1, @@ -966,10 +1075,12 @@ } define @intrinsic_vslideup_vi_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv4i32( %0, %1, @@ -980,10 +1091,12 @@ } define @intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4i32( %0, %1, @@ -1001,10 +1114,12 @@ i64); define @intrinsic_vslideup_vx_nxv8i32_nxv8i32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv8i32( %0, %1, @@ -1022,10 +1137,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8i32( %0, %1, @@ -1037,10 +1154,12 @@ } define @intrinsic_vslideup_vi_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv8i32( %0, %1, @@ -1051,10 +1170,12 @@ } define @intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8i32( %0, %1, @@ -1072,10 +1193,12 @@ i64); define @intrinsic_vslideup_vx_nxv1i64_nxv1i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv1i64( %0, %1, @@ -1093,10 +1216,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1i64( %0, %1, @@ -1108,10 +1233,12 @@ } define @intrinsic_vslideup_vi_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv1i64( %0, %1, @@ -1122,10 +1249,12 @@ } define @intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1i64( %0, %1, @@ -1143,10 +1272,12 @@ i64); define @intrinsic_vslideup_vx_nxv2i64_nxv2i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv2i64( %0, %1, @@ -1164,10 +1295,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2i64( %0, %1, @@ -1179,10 +1312,12 @@ } define @intrinsic_vslideup_vi_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv2i64( %0, %1, @@ -1193,10 +1328,12 @@ } define @intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2i64( %0, %1, @@ -1214,10 +1351,12 @@ i64); define @intrinsic_vslideup_vx_nxv4i64_nxv4i64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv4i64( %0, %1, @@ -1235,10 +1374,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4i64( %0, %1, @@ -1250,10 +1391,12 @@ } define @intrinsic_vslideup_vi_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv4i64( %0, %1, @@ -1264,10 +1407,12 @@ } define @intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4i64( %0, %1, @@ -1285,10 +1430,12 @@ i64); define @intrinsic_vslideup_vx_nxv1f16_nxv1f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv1f16( %0, %1, @@ -1306,10 +1453,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1f16( %0, %1, @@ -1321,10 +1470,12 @@ } define @intrinsic_vslideup_vi_nxv1f16_nxv1f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv1f16( %0, %1, @@ -1335,10 +1486,12 @@ } define @intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1f16( %0, %1, @@ -1356,10 +1509,12 @@ i64); define @intrinsic_vslideup_vx_nxv2f16_nxv2f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv2f16( %0, %1, @@ -1377,10 +1532,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2f16( %0, %1, @@ -1392,10 +1549,12 @@ } define @intrinsic_vslideup_vi_nxv2f16_nxv2f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv2f16( %0, %1, @@ -1406,10 +1565,12 @@ } define @intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2f16( %0, %1, @@ -1427,10 +1588,12 @@ i64); define @intrinsic_vslideup_vx_nxv4f16_nxv4f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv4f16( %0, %1, @@ -1448,10 +1611,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4f16( %0, %1, @@ -1463,10 +1628,12 @@ } define @intrinsic_vslideup_vi_nxv4f16_nxv4f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv4f16( %0, %1, @@ -1477,10 +1644,12 @@ } define @intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4f16( %0, %1, @@ -1498,10 +1667,12 @@ i64); define @intrinsic_vslideup_vx_nxv8f16_nxv8f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv8f16( %0, %1, @@ -1519,10 +1690,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8f16( %0, %1, @@ -1534,10 +1707,12 @@ } define @intrinsic_vslideup_vi_nxv8f16_nxv8f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv8f16( %0, %1, @@ -1548,10 +1723,12 @@ } define @intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8f16( %0, %1, @@ -1569,10 +1746,12 @@ i64); define @intrinsic_vslideup_vx_nxv16f16_nxv16f16( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv16f16( %0, %1, @@ -1590,10 +1769,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv16f16( %0, %1, @@ -1605,10 +1786,12 @@ } define @intrinsic_vslideup_vi_nxv16f16_nxv16f16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv16f16( %0, %1, @@ -1619,10 +1802,12 @@ } define @intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv16f16( %0, %1, @@ -1640,10 +1825,12 @@ i64); define @intrinsic_vslideup_vx_nxv1f32_nxv1f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv1f32( %0, %1, @@ -1661,10 +1848,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1f32( %0, %1, @@ -1676,10 +1865,12 @@ } define @intrinsic_vslideup_vi_nxv1f32_nxv1f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv1f32( %0, %1, @@ -1690,10 +1881,12 @@ } define @intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1f32( %0, %1, @@ -1711,10 +1904,12 @@ i64); define @intrinsic_vslideup_vx_nxv2f32_nxv2f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv2f32( %0, %1, @@ -1732,10 +1927,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2f32( %0, %1, @@ -1747,10 +1944,12 @@ } define @intrinsic_vslideup_vi_nxv2f32_nxv2f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv2f32( %0, %1, @@ -1761,10 +1960,12 @@ } define @intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2f32( %0, %1, @@ -1782,10 +1983,12 @@ i64); define @intrinsic_vslideup_vx_nxv4f32_nxv4f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv4f32( %0, %1, @@ -1803,10 +2006,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4f32( %0, %1, @@ -1818,10 +2023,12 @@ } define @intrinsic_vslideup_vi_nxv4f32_nxv4f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv4f32( %0, %1, @@ -1832,10 +2039,12 @@ } define @intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4f32( %0, %1, @@ -1853,10 +2062,12 @@ i64); define @intrinsic_vslideup_vx_nxv8f32_nxv8f32( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv8f32( %0, %1, @@ -1874,10 +2085,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8f32( %0, %1, @@ -1889,10 +2102,12 @@ } define @intrinsic_vslideup_vi_nxv8f32_nxv8f32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv8f32( %0, %1, @@ -1903,10 +2118,12 @@ } define @intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv8f32( %0, %1, @@ -1924,10 +2141,12 @@ i64); define @intrinsic_vslideup_vx_nxv1f64_nxv1f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv1f64( %0, %1, @@ -1945,10 +2164,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1f64( %0, %1, @@ -1960,10 +2181,12 @@ } define @intrinsic_vslideup_vi_nxv1f64_nxv1f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv1f64( %0, %1, @@ -1974,10 +2197,12 @@ } define @intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vslideup.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv1f64( %0, %1, @@ -1995,10 +2220,12 @@ i64); define @intrinsic_vslideup_vx_nxv2f64_nxv2f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv2f64( %0, %1, @@ -2016,10 +2243,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2f64( %0, %1, @@ -2031,10 +2260,12 @@ } define @intrinsic_vslideup_vi_nxv2f64_nxv2f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv2f64( %0, %1, @@ -2045,10 +2276,12 @@ } define @intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vslideup.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv2f64( %0, %1, @@ -2066,10 +2299,12 @@ i64); define @intrinsic_vslideup_vx_nxv4f64_nxv4f64( %0, %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vx_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0 %a = call @llvm.riscv.vslideup.nxv4f64( %0, %1, @@ -2087,10 +2322,12 @@ i64); define @intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vslideup.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vx_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslideup.vx {{v[0-9]+}}, {{v[0-9]+}}, a0, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4f64( %0, %1, @@ -2102,10 +2339,12 @@ } define @intrinsic_vslideup_vi_nxv4f64_nxv4f64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_vi_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vslideup.nxv4f64( %0, %1, @@ -2116,10 +2355,12 @@ } define @intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vslideup.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vslideup_mask_vi_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vslideup.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vslideup.mask.nxv4f64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsll.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vsll_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vsll_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vsll_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vsll_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vsll_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vsll_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsll.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vsll_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vsll_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vsll_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vsll_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vsll_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vsll_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsll.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vsll_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vsll_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vsll_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vsll_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vsll_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vsll_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsll.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vsll_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vsll_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vsll_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vsll_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vsll_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vsll_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vsll_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vsll_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vsll_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vsll_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vsll_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vsll_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vsll_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vsll_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vsll_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vsll_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vsll_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vsll_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vsll_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vsll_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vsll_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vsll_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vsll_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vsll_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vsll_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vsll_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vsll_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vsll_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vsll_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vsll_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vsll_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vsll_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vsll_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vsll_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vsll_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vsll_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsll.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vsll_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vsll_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vsll_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vsll_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vsll_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vsll_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsll.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vsll_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vsll_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vsll_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vsll_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vsll_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vsll_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsll.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vsll_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vsll_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vsll_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vsll_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vsll_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsll.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vsll_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vsll_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsll.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vsll_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vsll_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vsll_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsll.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vsll_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vsll.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsll.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vsll_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vsll_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vsll_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vsll_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vsll_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vsll_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vsll_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vsll_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vsll_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vsll_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vsll_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vsll_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vsll_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vsll_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vsll_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vsll_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vsll_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vsll_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vsll_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vsll.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vsll_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vsll_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vsll.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vsll_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsll_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsll.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsll.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vsll_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vsll.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsll.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vsll_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vsll_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vsll_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vsll_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vsll_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vsll_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vsll_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vsll_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vsll_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vsll_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vsll_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vsll_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vsll_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vsll_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vsll_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vsll_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vsll_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vsll_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vsll_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vsll_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vsll_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsll.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vsll_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vsll_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsll.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vsll_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsll_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsll.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsll.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vsll_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vsll.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsll.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsll.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsmul.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsmul.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsmul.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsmul.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i32( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i32( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i8.nxv2i32( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i32( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i8.nxv4i32( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i32( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i8.nxv8i32( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i32( @@ -194,10 +194,8 @@ define void @intrinsic_vsoxei_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i8.nxv16i32( @@ -219,10 +217,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i8.nxv16i32( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i16.nxv1i32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i16.nxv2i32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i16.nxv4i32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i32( @@ -383,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i16.nxv8i32( @@ -406,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i32( @@ -428,10 +424,8 @@ define void @intrinsic_vsoxei_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i16.nxv16i32( @@ -453,10 +447,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i16.nxv16i32( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i32.nxv1i32( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i32( @@ -525,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i32.nxv2i32( @@ -548,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i32( @@ -571,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i32.nxv4i32( @@ -594,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i32( @@ -617,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i32.nxv8i32( @@ -640,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i32( @@ -662,10 +654,8 @@ define void @intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i32.nxv16i32( @@ -687,10 +677,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i32.nxv16i32( @@ -713,7 +701,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f16.nxv1i32( @@ -736,7 +724,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i32( @@ -759,7 +747,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f16.nxv2i32( @@ -782,7 +770,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i32( @@ -805,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f16.nxv4i32( @@ -828,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i32( @@ -851,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f16.nxv8i32( @@ -874,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i32( @@ -896,10 +884,8 @@ define void @intrinsic_vsoxei_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f16.nxv16i32( @@ -921,10 +907,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f16.nxv16i32( @@ -947,7 +931,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f32.nxv1i32( @@ -970,7 +954,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i32( @@ -993,7 +977,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f32.nxv2i32( @@ -1016,7 +1000,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i32( @@ -1039,7 +1023,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f32.nxv4i32( @@ -1062,7 +1046,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i32( @@ -1085,7 +1069,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f32.nxv8i32( @@ -1108,7 +1092,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i32( @@ -1130,10 +1114,8 @@ define void @intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f32.nxv16i32( @@ -1155,10 +1137,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f32.nxv16i32( @@ -1181,7 +1161,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f64.nxv1i32( @@ -1204,7 +1184,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i32( @@ -1227,7 +1207,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f64.nxv2i32( @@ -1250,7 +1230,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i32( @@ -1273,7 +1253,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f64.nxv4i32( @@ -1296,7 +1276,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i32( @@ -1318,10 +1298,8 @@ define void @intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f64.nxv8i32( @@ -1343,10 +1321,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i32( @@ -1369,7 +1345,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i16( @@ -1392,7 +1368,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i16( @@ -1415,7 +1391,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i8.nxv2i16( @@ -1438,7 +1414,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i16( @@ -1461,7 +1437,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i8.nxv4i16( @@ -1484,7 +1460,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i16( @@ -1507,7 +1483,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i8.nxv8i16( @@ -1530,7 +1506,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i16( @@ -1553,7 +1529,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i8.nxv16i16( @@ -1576,7 +1552,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i8.nxv16i16( @@ -1598,10 +1574,8 @@ define void @intrinsic_vsoxei_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32i8.nxv32i16( @@ -1623,10 +1597,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32i8.nxv32i16( @@ -1649,7 +1621,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i16.nxv1i16( @@ -1672,7 +1644,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i16( @@ -1695,7 +1667,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i16.nxv2i16( @@ -1718,7 +1690,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i16( @@ -1741,7 +1713,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i16.nxv4i16( @@ -1764,7 +1736,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i16( @@ -1787,7 +1759,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i16.nxv8i16( @@ -1810,7 +1782,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i16( @@ -1833,7 +1805,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i16.nxv16i16( @@ -1856,7 +1828,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i16.nxv16i16( @@ -1878,10 +1850,8 @@ define void @intrinsic_vsoxei_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32i16.nxv32i16( @@ -1903,10 +1873,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32i16.nxv32i16( @@ -1929,7 +1897,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i32.nxv1i16( @@ -1952,7 +1920,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16( @@ -1975,7 +1943,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i32.nxv2i16( @@ -1998,7 +1966,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i16( @@ -2021,7 +1989,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i32.nxv4i16( @@ -2044,7 +2012,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i16( @@ -2067,7 +2035,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i32.nxv8i16( @@ -2090,7 +2058,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i16( @@ -2112,10 +2080,8 @@ define void @intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i32.nxv16i16( @@ -2137,10 +2103,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i32.nxv16i16( @@ -2163,7 +2127,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f16.nxv1i16( @@ -2186,7 +2150,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i16( @@ -2209,7 +2173,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f16.nxv2i16( @@ -2232,7 +2196,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i16( @@ -2255,7 +2219,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f16.nxv4i16( @@ -2278,7 +2242,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i16( @@ -2301,7 +2265,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f16.nxv8i16( @@ -2324,7 +2288,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i16( @@ -2347,7 +2311,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f16.nxv16i16( @@ -2370,7 +2334,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f16.nxv16i16( @@ -2392,10 +2356,8 @@ define void @intrinsic_vsoxei_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32f16.nxv32i16( @@ -2417,10 +2379,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32f16.nxv32i16( @@ -2443,7 +2403,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f32.nxv1i16( @@ -2466,7 +2426,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i16( @@ -2489,7 +2449,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f32.nxv2i16( @@ -2512,7 +2472,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i16( @@ -2535,7 +2495,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f32.nxv4i16( @@ -2558,7 +2518,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i16( @@ -2581,7 +2541,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f32.nxv8i16( @@ -2604,7 +2564,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i16( @@ -2626,10 +2586,8 @@ define void @intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f32.nxv16i16( @@ -2651,10 +2609,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f32.nxv16i16( @@ -2677,7 +2633,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f64.nxv1i16( @@ -2700,7 +2656,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i16( @@ -2723,7 +2679,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f64.nxv2i16( @@ -2746,7 +2702,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i16( @@ -2769,7 +2725,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f64.nxv4i16( @@ -2792,7 +2748,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i16( @@ -2814,10 +2770,8 @@ define void @intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f64.nxv8i16( @@ -2839,10 +2793,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i16( @@ -2865,7 +2817,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i8( @@ -2888,7 +2840,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i8( @@ -2911,7 +2863,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i8.nxv2i8( @@ -2934,7 +2886,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i8( @@ -2957,7 +2909,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i8.nxv4i8( @@ -2980,7 +2932,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i8( @@ -3003,7 +2955,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i8.nxv8i8( @@ -3026,7 +2978,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i8( @@ -3049,7 +3001,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i8.nxv16i8( @@ -3072,7 +3024,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i8.nxv16i8( @@ -3095,7 +3047,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32i8.nxv32i8( @@ -3118,7 +3070,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32i8.nxv32i8( @@ -3140,10 +3092,8 @@ define void @intrinsic_vsoxei_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv64i8.nxv64i8( @@ -3165,10 +3115,8 @@ define void @intrinsic_vsoxei_mask_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv64i8.nxv64i8( @@ -3191,7 +3139,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i16.nxv1i8( @@ -3214,7 +3162,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i8( @@ -3237,7 +3185,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i16.nxv2i8( @@ -3260,7 +3208,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i8( @@ -3283,7 +3231,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i16.nxv4i8( @@ -3306,7 +3254,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i8( @@ -3329,7 +3277,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i16.nxv8i8( @@ -3352,7 +3300,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i8( @@ -3375,7 +3323,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i16.nxv16i8( @@ -3398,7 +3346,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i16.nxv16i8( @@ -3420,10 +3368,8 @@ define void @intrinsic_vsoxei_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32i16.nxv32i8( @@ -3445,10 +3391,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32i16.nxv32i8( @@ -3471,7 +3415,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i32.nxv1i8( @@ -3494,7 +3438,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i8( @@ -3517,7 +3461,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i32.nxv2i8( @@ -3540,7 +3484,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i8( @@ -3563,7 +3507,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i32.nxv4i8( @@ -3586,7 +3530,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i8( @@ -3609,7 +3553,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i32.nxv8i8( @@ -3632,7 +3576,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i8( @@ -3654,10 +3598,8 @@ define void @intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i32.nxv16i8( @@ -3679,10 +3621,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i32.nxv16i8( @@ -3705,7 +3645,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f16.nxv1i8( @@ -3728,7 +3668,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i8( @@ -3751,7 +3691,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f16.nxv2i8( @@ -3774,7 +3714,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i8( @@ -3797,7 +3737,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f16.nxv4i8( @@ -3820,7 +3760,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i8( @@ -3843,7 +3783,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f16.nxv8i8( @@ -3866,7 +3806,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i8( @@ -3889,7 +3829,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f16.nxv16i8( @@ -3912,7 +3852,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f16.nxv16i8( @@ -3934,10 +3874,8 @@ define void @intrinsic_vsoxei_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32f16.nxv32i8( @@ -3959,10 +3897,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32f16.nxv32i8( @@ -3985,7 +3921,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f32.nxv1i8( @@ -4008,7 +3944,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i8( @@ -4031,7 +3967,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f32.nxv2i8( @@ -4054,7 +3990,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i8( @@ -4077,7 +4013,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f32.nxv4i8( @@ -4100,7 +4036,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i8( @@ -4123,7 +4059,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f32.nxv8i8( @@ -4146,7 +4082,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i8( @@ -4168,10 +4104,8 @@ define void @intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f32.nxv16i8( @@ -4193,10 +4127,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f32.nxv16i8( @@ -4219,7 +4151,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f64.nxv1i8( @@ -4242,7 +4174,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i8( @@ -4265,7 +4197,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f64.nxv2i8( @@ -4288,7 +4220,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i8( @@ -4311,7 +4243,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f64.nxv4i8( @@ -4334,7 +4266,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i8( @@ -4356,10 +4288,8 @@ define void @intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v25 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f64.nxv8i8( @@ -4381,10 +4311,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v25, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17 +; CHECK-NEXT: vsoxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i64( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i64( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18 +; CHECK-NEXT: vsoxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i8.nxv2i64( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i64( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20 +; CHECK-NEXT: vsoxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i8.nxv4i64( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i64( @@ -148,10 +148,8 @@ define void @intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i8.nxv8i64( @@ -173,10 +171,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i64( @@ -199,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17 +; CHECK-NEXT: vsoxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i16.nxv1i64( @@ -222,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i64( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18 +; CHECK-NEXT: vsoxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i16.nxv2i64( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i64( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20 +; CHECK-NEXT: vsoxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i16.nxv4i64( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i64( @@ -336,10 +332,8 @@ define void @intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i16.nxv8i64( @@ -361,10 +355,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i64( @@ -387,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17 +; CHECK-NEXT: vsoxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i32.nxv1i64( @@ -410,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i64( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18 +; CHECK-NEXT: vsoxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i32.nxv2i64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20 +; CHECK-NEXT: vsoxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i32.nxv4i64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i64( @@ -524,10 +516,8 @@ define void @intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i32.nxv8i64( @@ -549,10 +539,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i64( @@ -575,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17 +; CHECK-NEXT: vsoxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i64.nxv1i64( @@ -598,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i64( @@ -621,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18 +; CHECK-NEXT: vsoxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i64.nxv2i64( @@ -644,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i64.nxv2i64( @@ -667,7 +655,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20 +; CHECK-NEXT: vsoxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i64.nxv4i64( @@ -690,7 +678,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i64.nxv4i64( @@ -712,10 +700,8 @@ define void @intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i64.nxv8i64( @@ -737,10 +723,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i64.nxv8i64( @@ -763,7 +747,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17 +; CHECK-NEXT: vsoxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f16.nxv1i64( @@ -786,7 +770,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i64( @@ -809,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18 +; CHECK-NEXT: vsoxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f16.nxv2i64( @@ -832,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i64( @@ -855,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20 +; CHECK-NEXT: vsoxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f16.nxv4i64( @@ -878,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i64( @@ -900,10 +884,8 @@ define void @intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f16.nxv8i64( @@ -925,10 +907,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i64( @@ -951,7 +931,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17 +; CHECK-NEXT: vsoxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f32.nxv1i64( @@ -974,7 +954,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i64( @@ -997,7 +977,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18 +; CHECK-NEXT: vsoxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f32.nxv2i64( @@ -1020,7 +1000,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i64( @@ -1043,7 +1023,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20 +; CHECK-NEXT: vsoxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f32.nxv4i64( @@ -1066,7 +1046,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i64( @@ -1088,10 +1068,8 @@ define void @intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f32.nxv8i64( @@ -1113,10 +1091,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i64( @@ -1139,7 +1115,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17 +; CHECK-NEXT: vsoxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f64.nxv1i64( @@ -1162,7 +1138,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i64( @@ -1185,7 +1161,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18 +; CHECK-NEXT: vsoxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f64.nxv2i64( @@ -1208,7 +1184,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i64( @@ -1231,7 +1207,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20 +; CHECK-NEXT: vsoxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f64.nxv4i64( @@ -1254,7 +1230,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i64( @@ -1276,10 +1252,8 @@ define void @intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f64.nxv8i64( @@ -1301,10 +1275,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i64( @@ -1327,7 +1299,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i32( @@ -1350,7 +1322,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i32( @@ -1373,7 +1345,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i8.nxv2i32( @@ -1396,7 +1368,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i32( @@ -1419,7 +1391,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i8.nxv4i32( @@ -1442,7 +1414,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i32( @@ -1465,7 +1437,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i8.nxv8i32( @@ -1488,7 +1460,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i32( @@ -1510,10 +1482,8 @@ define void @intrinsic_vsoxei_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i8.nxv16i32( @@ -1535,10 +1505,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i8.nxv16i32( @@ -1561,7 +1529,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i16.nxv1i32( @@ -1584,7 +1552,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i32( @@ -1607,7 +1575,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i16.nxv2i32( @@ -1630,7 +1598,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i32( @@ -1653,7 +1621,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i16.nxv4i32( @@ -1676,7 +1644,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i32( @@ -1699,7 +1667,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i16.nxv8i32( @@ -1722,7 +1690,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i32( @@ -1744,10 +1712,8 @@ define void @intrinsic_vsoxei_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i16.nxv16i32( @@ -1769,10 +1735,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i16.nxv16i32( @@ -1795,7 +1759,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i32.nxv1i32( @@ -1818,7 +1782,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i32( @@ -1841,7 +1805,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i32.nxv2i32( @@ -1864,7 +1828,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i32( @@ -1887,7 +1851,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i32.nxv4i32( @@ -1910,7 +1874,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i32( @@ -1933,7 +1897,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i32.nxv8i32( @@ -1956,7 +1920,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i32( @@ -1978,10 +1942,8 @@ define void @intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i32.nxv16i32( @@ -2003,10 +1965,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i32.nxv16i32( @@ -2029,7 +1989,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i64.nxv1i32( @@ -2052,7 +2012,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i32( @@ -2075,7 +2035,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i64.nxv2i32( @@ -2098,7 +2058,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i64.nxv2i32( @@ -2121,7 +2081,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i64.nxv4i32( @@ -2144,7 +2104,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i64.nxv4i32( @@ -2166,10 +2126,8 @@ define void @intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i64.nxv8i32( @@ -2191,10 +2149,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i64.nxv8i32( @@ -2217,7 +2173,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f16.nxv1i32( @@ -2240,7 +2196,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i32( @@ -2263,7 +2219,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f16.nxv2i32( @@ -2286,7 +2242,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i32( @@ -2309,7 +2265,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f16.nxv4i32( @@ -2332,7 +2288,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i32( @@ -2355,7 +2311,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f16.nxv8i32( @@ -2378,7 +2334,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i32( @@ -2400,10 +2356,8 @@ define void @intrinsic_vsoxei_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f16.nxv16i32( @@ -2425,10 +2379,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f16.nxv16i32( @@ -2451,7 +2403,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f32.nxv1i32( @@ -2474,7 +2426,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i32( @@ -2497,7 +2449,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f32.nxv2i32( @@ -2520,7 +2472,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i32( @@ -2543,7 +2495,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f32.nxv4i32( @@ -2566,7 +2518,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i32( @@ -2589,7 +2541,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f32.nxv8i32( @@ -2612,7 +2564,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i32( @@ -2634,10 +2586,8 @@ define void @intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f32.nxv16i32( @@ -2659,10 +2609,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f32.nxv16i32( @@ -2685,7 +2633,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17 +; CHECK-NEXT: vsoxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f64.nxv1i32( @@ -2708,7 +2656,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i32( @@ -2731,7 +2679,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18 +; CHECK-NEXT: vsoxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f64.nxv2i32( @@ -2754,7 +2702,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i32( @@ -2777,7 +2725,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20 +; CHECK-NEXT: vsoxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f64.nxv4i32( @@ -2800,7 +2748,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i32( @@ -2822,10 +2770,8 @@ define void @intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f64.nxv8i32( @@ -2847,10 +2793,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei32.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i32( @@ -2873,7 +2817,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i16( @@ -2896,7 +2840,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i16( @@ -2919,7 +2863,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i8.nxv2i16( @@ -2942,7 +2886,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i16( @@ -2965,7 +2909,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i8.nxv4i16( @@ -2988,7 +2932,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i16( @@ -3011,7 +2955,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i8.nxv8i16( @@ -3034,7 +2978,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i16( @@ -3057,7 +3001,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i8.nxv16i16( @@ -3080,7 +3024,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i8.nxv16i16( @@ -3102,10 +3046,8 @@ define void @intrinsic_vsoxei_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32i8.nxv32i16( @@ -3127,10 +3069,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32i8.nxv32i16( @@ -3153,7 +3093,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i16.nxv1i16( @@ -3176,7 +3116,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i16( @@ -3199,7 +3139,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i16.nxv2i16( @@ -3222,7 +3162,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i16( @@ -3245,7 +3185,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i16.nxv4i16( @@ -3268,7 +3208,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i16( @@ -3291,7 +3231,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i16.nxv8i16( @@ -3314,7 +3254,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i16( @@ -3337,7 +3277,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i16.nxv16i16( @@ -3360,7 +3300,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i16.nxv16i16( @@ -3382,10 +3322,8 @@ define void @intrinsic_vsoxei_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32i16.nxv32i16( @@ -3407,10 +3345,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32i16.nxv32i16( @@ -3433,7 +3369,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i32.nxv1i16( @@ -3456,7 +3392,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16( @@ -3479,7 +3415,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i32.nxv2i16( @@ -3502,7 +3438,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i16( @@ -3525,7 +3461,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i32.nxv4i16( @@ -3548,7 +3484,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i16( @@ -3571,7 +3507,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i32.nxv8i16( @@ -3594,7 +3530,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i16( @@ -3616,10 +3552,8 @@ define void @intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i32.nxv16i16( @@ -3641,10 +3575,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i32.nxv16i16( @@ -3667,7 +3599,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i64.nxv1i16( @@ -3690,7 +3622,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i16( @@ -3713,7 +3645,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i64.nxv2i16( @@ -3736,7 +3668,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i64.nxv2i16( @@ -3759,7 +3691,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i64.nxv4i16( @@ -3782,7 +3714,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i64.nxv4i16( @@ -3804,10 +3736,8 @@ define void @intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i64.nxv8i16( @@ -3829,10 +3759,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i64.nxv8i16( @@ -3855,7 +3783,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f16.nxv1i16( @@ -3878,7 +3806,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i16( @@ -3901,7 +3829,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f16.nxv2i16( @@ -3924,7 +3852,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i16( @@ -3947,7 +3875,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f16.nxv4i16( @@ -3970,7 +3898,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i16( @@ -3993,7 +3921,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f16.nxv8i16( @@ -4016,7 +3944,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i16( @@ -4039,7 +3967,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f16.nxv16i16( @@ -4062,7 +3990,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f16.nxv16i16( @@ -4084,10 +4012,8 @@ define void @intrinsic_vsoxei_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32f16.nxv32i16( @@ -4109,10 +4035,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32f16.nxv32i16( @@ -4135,7 +4059,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f32.nxv1i16( @@ -4158,7 +4082,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i16( @@ -4181,7 +4105,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f32.nxv2i16( @@ -4204,7 +4128,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i16( @@ -4227,7 +4151,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f32.nxv4i16( @@ -4250,7 +4174,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i16( @@ -4273,7 +4197,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f32.nxv8i16( @@ -4296,7 +4220,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i16( @@ -4318,10 +4242,8 @@ define void @intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f32.nxv16i16( @@ -4343,10 +4265,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f32.nxv16i16( @@ -4369,7 +4289,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17 +; CHECK-NEXT: vsoxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f64.nxv1i16( @@ -4392,7 +4312,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i16( @@ -4415,7 +4335,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18 +; CHECK-NEXT: vsoxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f64.nxv2i16( @@ -4438,7 +4358,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i16( @@ -4461,7 +4381,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20 +; CHECK-NEXT: vsoxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f64.nxv4i16( @@ -4484,7 +4404,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i16( @@ -4506,10 +4426,8 @@ define void @intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f64.nxv8i16( @@ -4531,10 +4449,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei16.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i16( @@ -4557,7 +4473,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i8.nxv1i8( @@ -4580,7 +4496,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i8( @@ -4603,7 +4519,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i8.nxv2i8( @@ -4626,7 +4542,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i8( @@ -4649,7 +4565,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i8.nxv4i8( @@ -4672,7 +4588,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i8( @@ -4695,7 +4611,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i8.nxv8i8( @@ -4718,7 +4634,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i8( @@ -4741,7 +4657,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i8.nxv16i8( @@ -4764,7 +4680,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i8.nxv16i8( @@ -4787,7 +4703,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32i8.nxv32i8( @@ -4810,7 +4726,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32i8.nxv32i8( @@ -4832,10 +4748,8 @@ define void @intrinsic_vsoxei_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv64i8.nxv64i8( @@ -4857,10 +4771,8 @@ define void @intrinsic_vsoxei_mask_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv64i8.nxv64i8( @@ -4883,7 +4795,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i16.nxv1i8( @@ -4906,7 +4818,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i8( @@ -4929,7 +4841,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i16.nxv2i8( @@ -4952,7 +4864,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i8( @@ -4975,7 +4887,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i16.nxv4i8( @@ -4998,7 +4910,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i8( @@ -5021,7 +4933,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i16.nxv8i8( @@ -5044,7 +4956,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i8( @@ -5067,7 +4979,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i16.nxv16i8( @@ -5090,7 +5002,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i16.nxv16i8( @@ -5112,10 +5024,8 @@ define void @intrinsic_vsoxei_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32i16.nxv32i8( @@ -5137,10 +5047,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32i16.nxv32i8( @@ -5163,7 +5071,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i32.nxv1i8( @@ -5186,7 +5094,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i8( @@ -5209,7 +5117,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i32.nxv2i8( @@ -5232,7 +5140,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i8( @@ -5255,7 +5163,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i32.nxv4i8( @@ -5278,7 +5186,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i8( @@ -5301,7 +5209,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i32.nxv8i8( @@ -5324,7 +5232,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i8( @@ -5346,10 +5254,8 @@ define void @intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16i32.nxv16i8( @@ -5371,10 +5277,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16i32.nxv16i8( @@ -5397,7 +5301,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1i64.nxv1i8( @@ -5420,7 +5324,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i8( @@ -5443,7 +5347,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2i64.nxv2i8( @@ -5466,7 +5370,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2i64.nxv2i8( @@ -5489,7 +5393,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4i64.nxv4i8( @@ -5512,7 +5416,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4i64.nxv4i8( @@ -5534,10 +5438,8 @@ define void @intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v25 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8i64.nxv8i8( @@ -5559,10 +5461,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v25, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8i64.nxv8i8( @@ -5585,7 +5485,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f16.nxv1i8( @@ -5608,7 +5508,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i8( @@ -5631,7 +5531,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f16.nxv2i8( @@ -5654,7 +5554,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i8( @@ -5677,7 +5577,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f16.nxv4i8( @@ -5700,7 +5600,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i8( @@ -5723,7 +5623,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f16.nxv8i8( @@ -5746,7 +5646,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i8( @@ -5769,7 +5669,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f16.nxv16i8( @@ -5792,7 +5692,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f16.nxv16i8( @@ -5814,10 +5714,8 @@ define void @intrinsic_vsoxei_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv32f16.nxv32i8( @@ -5839,10 +5737,8 @@ define void @intrinsic_vsoxei_mask_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv32f16.nxv32i8( @@ -5865,7 +5761,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f32.nxv1i8( @@ -5888,7 +5784,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i8( @@ -5911,7 +5807,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f32.nxv2i8( @@ -5934,7 +5830,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i8( @@ -5957,7 +5853,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f32.nxv4i8( @@ -5980,7 +5876,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i8( @@ -6003,7 +5899,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f32.nxv8i8( @@ -6026,7 +5922,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i8( @@ -6048,10 +5944,8 @@ define void @intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv16f32.nxv16i8( @@ -6073,10 +5967,8 @@ define void @intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv16f32.nxv16i8( @@ -6099,7 +5991,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17 +; CHECK-NEXT: vsoxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv1f64.nxv1i8( @@ -6122,7 +6014,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i8( @@ -6145,7 +6037,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18 +; CHECK-NEXT: vsoxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv2f64.nxv2i8( @@ -6168,7 +6060,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i8( @@ -6191,7 +6083,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20 +; CHECK-NEXT: vsoxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv4f64.nxv4i8( @@ -6214,7 +6106,7 @@ ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsoxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i8( @@ -6236,10 +6128,8 @@ define void @intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v25 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.nxv8f64.nxv8i8( @@ -6261,10 +6151,8 @@ define void @intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsoxei8.v v16, (a0), v25, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsoxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll @@ -9,14 +9,14 @@ ; RV32V: # %bb.0: ; RV32V-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; RV32V-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; RV32V-NEXT: vfmv.v.f v16, fa0 +; RV32V-NEXT: vfmv.v.f v8, fa0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8f16: ; RV64V: # %bb.0: ; RV64V-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; RV64V-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; RV64V-NEXT: vfmv.v.f v16, fa0 +; RV64V-NEXT: vfmv.v.f v8, fa0 ; RV64V-NEXT: ret %head = insertelement undef, half %f, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -27,13 +27,13 @@ ; RV32V-LABEL: vsplat_zero_nxv8f16: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; RV32V-NEXT: vmv.v.i v16, 0 +; RV32V-NEXT: vmv.v.i v8, 0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_zero_nxv8f16: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; RV64V-NEXT: vmv.v.i v16, 0 +; RV64V-NEXT: vmv.v.i v8, 0 ; RV64V-NEXT: ret %head = insertelement undef, half zeroinitializer, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -44,13 +44,13 @@ ; RV32V-LABEL: vsplat_nxv8f32: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; RV32V-NEXT: vfmv.v.f v16, fa0 +; RV32V-NEXT: vfmv.v.f v8, fa0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8f32: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; RV64V-NEXT: vfmv.v.f v16, fa0 +; RV64V-NEXT: vfmv.v.f v8, fa0 ; RV64V-NEXT: ret %head = insertelement undef, float %f, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -61,13 +61,13 @@ ; RV32V-LABEL: vsplat_zero_nxv8f32: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; RV32V-NEXT: vmv.v.i v16, 0 +; RV32V-NEXT: vmv.v.i v8, 0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_zero_nxv8f32: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; RV64V-NEXT: vmv.v.i v16, 0 +; RV64V-NEXT: vmv.v.i v8, 0 ; RV64V-NEXT: ret %head = insertelement undef, float zeroinitializer, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -78,13 +78,13 @@ ; RV32V-LABEL: vsplat_nxv8f64: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV32V-NEXT: vfmv.v.f v16, fa0 +; RV32V-NEXT: vfmv.v.f v8, fa0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8f64: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV64V-NEXT: vfmv.v.f v16, fa0 +; RV64V-NEXT: vfmv.v.f v8, fa0 ; RV64V-NEXT: ret %head = insertelement undef, double %f, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -95,13 +95,13 @@ ; RV32V-LABEL: vsplat_zero_nxv8f64: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.i v16, 0 +; RV32V-NEXT: vmv.v.i v8, 0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_zero_nxv8f64: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV64V-NEXT: vmv.v.i v16, 0 +; RV64V-NEXT: vmv.v.i v8, 0 ; RV64V-NEXT: ret %head = insertelement undef, double zeroinitializer, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll @@ -8,13 +8,13 @@ ; RV32V-LABEL: vsplat_nxv8i64_1: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.i v16, -1 +; RV32V-NEXT: vmv.v.i v8, -1 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8i64_1: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV64V-NEXT: vmv.v.i v16, -1 +; RV64V-NEXT: vmv.v.i v8, -1 ; RV64V-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -25,13 +25,13 @@ ; RV32V-LABEL: vsplat_nxv8i64_2: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.i v16, 4 +; RV32V-NEXT: vmv.v.i v8, 4 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8i64_2: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV64V-NEXT: vmv.v.i v16, 4 +; RV64V-NEXT: vmv.v.i v8, 4 ; RV64V-NEXT: ret %head = insertelement undef, i64 4, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -43,14 +43,14 @@ ; RV32V: # %bb.0: ; RV32V-NEXT: addi a0, zero, 255 ; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.x v16, a0 +; RV32V-NEXT: vmv.v.x v8, a0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8i64_3: ; RV64V: # %bb.0: ; RV64V-NEXT: addi a0, zero, 255 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV64V-NEXT: vmv.v.x v16, a0 +; RV64V-NEXT: vmv.v.x v8, a0 ; RV64V-NEXT: ret %head = insertelement undef, i64 255, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -66,7 +66,7 @@ ; RV32V-NEXT: vmv.v.x v8, a0 ; RV32V-NEXT: addi a0, zero, 32 ; RV32V-NEXT: vsll.vx v8, v8, a0 -; RV32V-NEXT: vsrl.vx v16, v8, a0 +; RV32V-NEXT: vsrl.vx v8, v8, a0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8i64_4: @@ -75,7 +75,7 @@ ; RV64V-NEXT: slli a0, a0, 24 ; RV64V-NEXT: addi a0, a0, -1281 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV64V-NEXT: vmv.v.x v16, a0 +; RV64V-NEXT: vmv.v.x v8, a0 ; RV64V-NEXT: ret %head = insertelement undef, i64 4211079935, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -92,13 +92,13 @@ ; RV32V-NEXT: vmv.v.x v16, a0 ; RV32V-NEXT: vsll.vx v16, v16, a1 ; RV32V-NEXT: vsrl.vx v16, v16, a1 -; RV32V-NEXT: vor.vv v16, v16, v8 +; RV32V-NEXT: vor.vv v8, v16, v8 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vsplat_nxv8i64_5: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV64V-NEXT: vmv.v.x v16, a0 +; RV64V-NEXT: vmv.v.x v8, a0 ; RV64V-NEXT: ret %head = insertelement undef, i64 %a, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -109,13 +109,13 @@ ; RV32V-LABEL: vadd_vx_nxv8i64_6: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV32V-NEXT: vadd.vi v16, v16, 2 +; RV32V-NEXT: vadd.vi v8, v8, 2 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_6: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV64V-NEXT: vadd.vi v16, v16, 2 +; RV64V-NEXT: vadd.vi v8, v8, 2 ; RV64V-NEXT: ret %head = insertelement undef, i64 2, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -127,13 +127,13 @@ ; RV32V-LABEL: vadd_vx_nxv8i64_7: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV32V-NEXT: vadd.vi v16, v16, -1 +; RV32V-NEXT: vadd.vi v8, v8, -1 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_7: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV64V-NEXT: vadd.vi v16, v16, -1 +; RV64V-NEXT: vadd.vi v8, v8, -1 ; RV64V-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -146,14 +146,14 @@ ; RV32V: # %bb.0: ; RV32V-NEXT: addi a0, zero, 255 ; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV32V-NEXT: vadd.vx v16, v16, a0 +; RV32V-NEXT: vadd.vx v8, v8, a0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_8: ; RV64V: # %bb.0: ; RV64V-NEXT: addi a0, zero, 255 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV64V-NEXT: vadd.vx v16, v16, a0 +; RV64V-NEXT: vadd.vx v8, v8, a0 ; RV64V-NEXT: ret %head = insertelement undef, i64 255, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -167,7 +167,7 @@ ; RV32V-NEXT: lui a0, 503808 ; RV32V-NEXT: addi a0, a0, -1281 ; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV32V-NEXT: vadd.vx v16, v16, a0 +; RV32V-NEXT: vadd.vx v8, v8, a0 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_9: @@ -175,7 +175,7 @@ ; RV64V-NEXT: lui a0, 503808 ; RV64V-NEXT: addiw a0, a0, -1281 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV64V-NEXT: vadd.vx v16, v16, a0 +; RV64V-NEXT: vadd.vx v8, v8, a0 ; RV64V-NEXT: ret %head = insertelement undef, i64 2063596287, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -189,11 +189,11 @@ ; RV32V-NEXT: lui a0, 1028096 ; RV32V-NEXT: addi a0, a0, -1281 ; RV32V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.x v8, a0 +; RV32V-NEXT: vmv.v.x v16, a0 ; RV32V-NEXT: addi a0, zero, 32 -; RV32V-NEXT: vsll.vx v8, v8, a0 -; RV32V-NEXT: vsrl.vx v8, v8, a0 -; RV32V-NEXT: vadd.vv v16, v16, v8 +; RV32V-NEXT: vsll.vx v16, v16, a0 +; RV32V-NEXT: vsrl.vx v16, v16, a0 +; RV32V-NEXT: vadd.vv v8, v8, v16 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_10: @@ -202,7 +202,7 @@ ; RV64V-NEXT: slli a0, a0, 24 ; RV64V-NEXT: addi a0, a0, -1281 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV64V-NEXT: vadd.vx v16, v16, a0 +; RV64V-NEXT: vadd.vx v8, v8, a0 ; RV64V-NEXT: ret %head = insertelement undef, i64 4211079935, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,16 +214,16 @@ ; RV32V-LABEL: vadd_vx_nxv8i64_11: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.i v8, 1 +; RV32V-NEXT: vmv.v.i v16, 1 ; RV32V-NEXT: addi a0, zero, 32 -; RV32V-NEXT: vsll.vx v8, v8, a0 +; RV32V-NEXT: vsll.vx v16, v16, a0 ; RV32V-NEXT: lui a1, 1028096 ; RV32V-NEXT: addi a1, a1, -1281 ; RV32V-NEXT: vmv.v.x v24, a1 ; RV32V-NEXT: vsll.vx v24, v24, a0 ; RV32V-NEXT: vsrl.vx v24, v24, a0 -; RV32V-NEXT: vor.vv v8, v24, v8 -; RV32V-NEXT: vadd.vv v16, v16, v8 +; RV32V-NEXT: vor.vv v16, v24, v16 +; RV32V-NEXT: vadd.vv v8, v8, v16 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_11: @@ -232,7 +232,7 @@ ; RV64V-NEXT: slli a0, a0, 24 ; RV64V-NEXT: addi a0, a0, -1281 ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV64V-NEXT: vadd.vx v16, v16, a0 +; RV64V-NEXT: vadd.vx v8, v8, a0 ; RV64V-NEXT: ret %head = insertelement undef, i64 8506047231, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -244,20 +244,20 @@ ; RV32V-LABEL: vadd_vx_nxv8i64_12: ; RV32V: # %bb.0: ; RV32V-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; RV32V-NEXT: vmv.v.x v8, a1 +; RV32V-NEXT: vmv.v.x v16, a1 ; RV32V-NEXT: addi a1, zero, 32 -; RV32V-NEXT: vsll.vx v8, v8, a1 +; RV32V-NEXT: vsll.vx v16, v16, a1 ; RV32V-NEXT: vmv.v.x v24, a0 ; RV32V-NEXT: vsll.vx v24, v24, a1 ; RV32V-NEXT: vsrl.vx v24, v24, a1 -; RV32V-NEXT: vor.vv v8, v24, v8 -; RV32V-NEXT: vadd.vv v16, v16, v8 +; RV32V-NEXT: vor.vv v16, v24, v16 +; RV32V-NEXT: vadd.vv v8, v8, v16 ; RV32V-NEXT: ret ; ; RV64V-LABEL: vadd_vx_nxv8i64_12: ; RV64V: # %bb.0: ; RV64V-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; RV64V-NEXT: vadd.vx v16, v16, a0 +; RV64V-NEXT: vadd.vx v8, v8, a0 ; RV64V-NEXT: ret %head = insertelement undef, i64 %a, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsra.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vsra_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vsra_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vsra_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vsra_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vsra_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vsra_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vsra_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vsra_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vsra_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vsra_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vsra_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vsra_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vsra_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vsra_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vsra_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vsra_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vsra_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vsra_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vsra_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vsra_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vsra_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vsra_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vsra_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vsra_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vsra_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vsra_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vsra_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vsra_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vsra_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vsra_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vsra_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vsra_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vsra_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vsra_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vsra_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vsra_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vsra_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vsra_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vsra_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vsra_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vsra_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vsra_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vsra_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vsra_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vsra_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vsra_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vsra_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vsra_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vsra_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vsra_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vsra_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vsra_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vsra_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vsra_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vsra_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsra.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vsra_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vsra_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vsra_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vsra_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vsra_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vsra_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vsra_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vsra_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vsra_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vsra_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vsra_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vsra_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vsra_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vsra_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vsra_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vsra_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vsra_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vsra_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vsra_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vsra_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vsra_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vsra_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vsra_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vsra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vsra_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vsra_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vsra_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vsra_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vsra_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vsra_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vsra_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vsra_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vsra_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vsra_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vsra_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vsra_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vsra_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vsra_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vsra_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vsra_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vsra_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vsra_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vsra_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vsra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vsra_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vsra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vsra_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vsra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vsra_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsra_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsra.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vsra_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vsra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vsra_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vsra_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vsra_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vsra_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vsra_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vsra_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vsra_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vsra_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vsra_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vsra_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vsra_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vsra_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vsra_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vsra_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vsra_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vsra_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vsra_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vsra_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vsra_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vsra_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vsra_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vsra_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vsra_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vsra_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vsra_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsra_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsra.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vsra_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vsra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsra_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsra.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vsra_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vsra_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -27,7 +27,7 @@ ; CHECK-LABEL: vsra_vi_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -39,7 +39,7 @@ ; CHECK-LABEL: vsra_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -49,7 +49,7 @@ ; CHECK-LABEL: vsra_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -61,7 +61,7 @@ ; CHECK-LABEL: vsra_vi_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -73,7 +73,7 @@ ; CHECK-LABEL: vsra_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -83,7 +83,7 @@ ; CHECK-LABEL: vsra_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -95,7 +95,7 @@ ; CHECK-LABEL: vsra_vi_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -107,7 +107,7 @@ ; CHECK-LABEL: vsra_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -117,7 +117,7 @@ ; CHECK-LABEL: vsra_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -129,7 +129,7 @@ ; CHECK-LABEL: vsra_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -141,7 +141,7 @@ ; CHECK-LABEL: vsra_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v18 +; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -151,7 +151,7 @@ ; CHECK-LABEL: vsra_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -163,7 +163,7 @@ ; CHECK-LABEL: vsra_vi_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -175,7 +175,7 @@ ; CHECK-LABEL: vsra_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v20 +; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -185,7 +185,7 @@ ; CHECK-LABEL: vsra_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vsra_vi_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -208,9 +208,8 @@ define @vsra_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vsra_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsra.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -220,7 +219,7 @@ ; CHECK-LABEL: vsra_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,7 +231,7 @@ ; CHECK-LABEL: vsra_vi_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -244,7 +243,7 @@ ; CHECK-LABEL: vsra_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -254,7 +253,7 @@ ; CHECK-LABEL: vsra_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -266,7 +265,7 @@ ; CHECK-LABEL: vsra_vi_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -278,7 +277,7 @@ ; CHECK-LABEL: vsra_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -288,7 +287,7 @@ ; CHECK-LABEL: vsra_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +299,7 @@ ; CHECK-LABEL: vsra_vi_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -312,7 +311,7 @@ ; CHECK-LABEL: vsra_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -322,7 +321,7 @@ ; CHECK-LABEL: vsra_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,7 +333,7 @@ ; CHECK-LABEL: vsra_vi_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,7 +345,7 @@ ; CHECK-LABEL: vsra_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v18 +; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -356,7 +355,7 @@ ; CHECK-LABEL: vsra_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -368,7 +367,7 @@ ; CHECK-LABEL: vsra_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -380,7 +379,7 @@ ; CHECK-LABEL: vsra_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v20 +; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -390,7 +389,7 @@ ; CHECK-LABEL: vsra_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -402,7 +401,7 @@ ; CHECK-LABEL: vsra_vi_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,9 +412,8 @@ define @vsra_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vsra_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsra.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -425,7 +423,7 @@ ; CHECK-LABEL: vsra_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -437,7 +435,7 @@ ; CHECK-LABEL: vsra_vi_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +447,7 @@ ; CHECK-LABEL: vsra_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -459,7 +457,7 @@ ; CHECK-LABEL: vsra_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -471,7 +469,7 @@ ; CHECK-LABEL: vsra_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -483,7 +481,7 @@ ; CHECK-LABEL: vsra_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -493,7 +491,7 @@ ; CHECK-LABEL: vsra_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -505,7 +503,7 @@ ; CHECK-LABEL: vsra_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -517,7 +515,7 @@ ; CHECK-LABEL: vsra_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v18 +; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -527,7 +525,7 @@ ; CHECK-LABEL: vsra_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vsra_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -551,7 +549,7 @@ ; CHECK-LABEL: vsra_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v20 +; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -561,7 +559,7 @@ ; CHECK-LABEL: vsra_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -573,7 +571,7 @@ ; CHECK-LABEL: vsra_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -584,9 +582,8 @@ define @vsra_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vsra_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsra.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -596,7 +593,7 @@ ; CHECK-LABEL: vsra_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -608,7 +605,7 @@ ; CHECK-LABEL: vsra_vi_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -620,7 +617,7 @@ ; CHECK-LABEL: vsra_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -637,7 +634,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vsra.vv v16, v16, v25 +; CHECK-NEXT: vsra.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -649,7 +646,7 @@ ; CHECK-LABEL: vsra_vi_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -662,7 +659,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -674,7 +671,7 @@ ; CHECK-LABEL: vsra_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v18 +; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -691,7 +688,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vsra.vv v16, v16, v26 +; CHECK-NEXT: vsra.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -703,7 +700,7 @@ ; CHECK-LABEL: vsra_vi_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -716,7 +713,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -728,7 +725,7 @@ ; CHECK-LABEL: vsra_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v20 +; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -741,11 +738,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vsra.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vsra.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -757,7 +754,7 @@ ; CHECK-LABEL: vsra_vi_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -770,7 +767,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -781,9 +778,8 @@ define @vsra_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vsra_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsra.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -793,14 +789,14 @@ ; CHECK-LABEL: vsra_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vsra.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -812,7 +808,7 @@ ; CHECK-LABEL: vsra_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -825,7 +821,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vsra_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vsra_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -27,7 +27,7 @@ ; CHECK-LABEL: vsra_vi_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -39,7 +39,7 @@ ; CHECK-LABEL: vsra_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -49,7 +49,7 @@ ; CHECK-LABEL: vsra_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -61,7 +61,7 @@ ; CHECK-LABEL: vsra_vi_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -73,7 +73,7 @@ ; CHECK-LABEL: vsra_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -83,7 +83,7 @@ ; CHECK-LABEL: vsra_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -95,7 +95,7 @@ ; CHECK-LABEL: vsra_vi_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -107,7 +107,7 @@ ; CHECK-LABEL: vsra_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -117,7 +117,7 @@ ; CHECK-LABEL: vsra_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -129,7 +129,7 @@ ; CHECK-LABEL: vsra_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -141,7 +141,7 @@ ; CHECK-LABEL: vsra_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v18 +; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -151,7 +151,7 @@ ; CHECK-LABEL: vsra_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -163,7 +163,7 @@ ; CHECK-LABEL: vsra_vi_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -175,7 +175,7 @@ ; CHECK-LABEL: vsra_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v20 +; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -185,7 +185,7 @@ ; CHECK-LABEL: vsra_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vsra_vi_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -208,9 +208,8 @@ define @vsra_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vsra_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsra.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -220,7 +219,7 @@ ; CHECK-LABEL: vsra_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -232,7 +231,7 @@ ; CHECK-LABEL: vsra_vi_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -244,7 +243,7 @@ ; CHECK-LABEL: vsra_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -254,7 +253,7 @@ ; CHECK-LABEL: vsra_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -266,7 +265,7 @@ ; CHECK-LABEL: vsra_vi_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -278,7 +277,7 @@ ; CHECK-LABEL: vsra_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -288,7 +287,7 @@ ; CHECK-LABEL: vsra_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +299,7 @@ ; CHECK-LABEL: vsra_vi_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -312,7 +311,7 @@ ; CHECK-LABEL: vsra_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -322,7 +321,7 @@ ; CHECK-LABEL: vsra_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,7 +333,7 @@ ; CHECK-LABEL: vsra_vi_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -346,7 +345,7 @@ ; CHECK-LABEL: vsra_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v18 +; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -356,7 +355,7 @@ ; CHECK-LABEL: vsra_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -368,7 +367,7 @@ ; CHECK-LABEL: vsra_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -380,7 +379,7 @@ ; CHECK-LABEL: vsra_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v20 +; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -390,7 +389,7 @@ ; CHECK-LABEL: vsra_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -402,7 +401,7 @@ ; CHECK-LABEL: vsra_vi_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,9 +412,8 @@ define @vsra_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vsra_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsra.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -425,7 +423,7 @@ ; CHECK-LABEL: vsra_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -437,7 +435,7 @@ ; CHECK-LABEL: vsra_vi_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 6 +; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +447,7 @@ ; CHECK-LABEL: vsra_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -459,7 +457,7 @@ ; CHECK-LABEL: vsra_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -471,7 +469,7 @@ ; CHECK-LABEL: vsra_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -483,7 +481,7 @@ ; CHECK-LABEL: vsra_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -493,7 +491,7 @@ ; CHECK-LABEL: vsra_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -505,7 +503,7 @@ ; CHECK-LABEL: vsra_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -517,7 +515,7 @@ ; CHECK-LABEL: vsra_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v18 +; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -527,7 +525,7 @@ ; CHECK-LABEL: vsra_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -539,7 +537,7 @@ ; CHECK-LABEL: vsra_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -551,7 +549,7 @@ ; CHECK-LABEL: vsra_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v20 +; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -561,7 +559,7 @@ ; CHECK-LABEL: vsra_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -573,7 +571,7 @@ ; CHECK-LABEL: vsra_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -584,9 +582,8 @@ define @vsra_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vsra_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsra.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -596,7 +593,7 @@ ; CHECK-LABEL: vsra_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -608,7 +605,7 @@ ; CHECK-LABEL: vsra_vi_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -620,7 +617,7 @@ ; CHECK-LABEL: vsra_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v17 +; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -630,7 +627,7 @@ ; CHECK-LABEL: vsra_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -642,7 +639,7 @@ ; CHECK-LABEL: vsra_vi_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -655,7 +652,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -667,7 +664,7 @@ ; CHECK-LABEL: vsra_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v18 +; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -677,7 +674,7 @@ ; CHECK-LABEL: vsra_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -689,7 +686,7 @@ ; CHECK-LABEL: vsra_vi_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -702,7 +699,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -714,7 +711,7 @@ ; CHECK-LABEL: vsra_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsra.vv v16, v16, v20 +; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -724,7 +721,7 @@ ; CHECK-LABEL: vsra_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -736,7 +733,7 @@ ; CHECK-LABEL: vsra_vi_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -749,7 +746,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -760,9 +757,8 @@ define @vsra_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vsra_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsra.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = ashr %va, %vb ret %vc @@ -772,7 +768,7 @@ ; CHECK-LABEL: vsra_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -784,7 +780,7 @@ ; CHECK-LABEL: vsra_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsra.vi v16, v16, 31 +; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -797,7 +793,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsra.vx v16, v16, a0 +; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsrl.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vsrl_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vsrl_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vsrl_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vsrl_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vsrl_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vsrl_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vsrl_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vsrl_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vsrl_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vsrl_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vsrl_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vsrl_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vsrl_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vsrl_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vsrl_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vsrl_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vsrl_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vsrl_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsrl.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vsrl_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vsrl_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vsrl_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vsrl_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vsrl_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vsrl_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vsrl_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vsrl_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vsrl_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vsrl_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vsrl_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vsrl_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vsrl_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vsrl_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vsrl_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vsrl_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vsrl_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vsrl_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vsrl_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vsrl_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vsrl_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vsrl_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vsrl_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vsrl_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vsrl_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vsrl_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsrl.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vsrl_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vsrl_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vsrl_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vsrl_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vsrl_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vsrl_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vsrl_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vsrl_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vsrl.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vsrl_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vsrl.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -41,7 +41,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -53,7 +53,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -65,7 +65,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -77,7 +77,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -89,7 +89,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -101,7 +101,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -113,7 +113,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -125,7 +125,7 @@ ; CHECK-LABEL: vsrl_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -137,7 +137,7 @@ ; CHECK-LABEL: vsrl_vx_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -149,7 +149,7 @@ ; CHECK-LABEL: vsrl_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -161,7 +161,7 @@ ; CHECK-LABEL: vsrl_vx_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -173,7 +173,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -185,7 +185,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -209,7 +209,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -221,7 +221,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -233,7 +233,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +245,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,7 +257,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -269,7 +269,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +281,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -293,7 +293,7 @@ ; CHECK-LABEL: vsrl_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -305,7 +305,7 @@ ; CHECK-LABEL: vsrl_vx_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -317,7 +317,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -329,7 +329,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -341,7 +341,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -353,7 +353,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -365,7 +365,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -377,7 +377,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -389,7 +389,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -401,7 +401,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,7 +413,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,7 +425,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -444,7 +444,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vsrl.vv v16, v16, v25 +; CHECK-NEXT: vsrl.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -456,7 +456,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -469,7 +469,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -488,7 +488,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vsrl.vv v16, v16, v26 +; CHECK-NEXT: vsrl.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -500,7 +500,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -513,7 +513,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -528,11 +528,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vsrl.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vsrl.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -544,7 +544,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -557,7 +557,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -569,14 +569,14 @@ ; CHECK-LABEL: vsrl_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vsrl.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vsrl.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -588,7 +588,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,7 +601,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -17,7 +17,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -29,7 +29,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -41,7 +41,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -53,7 +53,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -65,7 +65,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -77,7 +77,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -89,7 +89,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -101,7 +101,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -113,7 +113,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -125,7 +125,7 @@ ; CHECK-LABEL: vsrl_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -137,7 +137,7 @@ ; CHECK-LABEL: vsrl_vx_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -149,7 +149,7 @@ ; CHECK-LABEL: vsrl_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -161,7 +161,7 @@ ; CHECK-LABEL: vsrl_vx_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i8 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -173,7 +173,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -185,7 +185,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -197,7 +197,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -209,7 +209,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -221,7 +221,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -233,7 +233,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -245,7 +245,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -257,7 +257,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -269,7 +269,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -281,7 +281,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -293,7 +293,7 @@ ; CHECK-LABEL: vsrl_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -305,7 +305,7 @@ ; CHECK-LABEL: vsrl_vx_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 6 +; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret %head = insertelement undef, i16 6, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -317,7 +317,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -329,7 +329,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -341,7 +341,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -353,7 +353,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -365,7 +365,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -377,7 +377,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -389,7 +389,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -401,7 +401,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -413,7 +413,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,7 +425,7 @@ ; CHECK-LABEL: vsrl_vx_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i32 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -437,7 +437,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -449,7 +449,7 @@ ; CHECK-LABEL: vsrl_vx_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +462,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -474,7 +474,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -486,7 +486,7 @@ ; CHECK-LABEL: vsrl_vx_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -499,7 +499,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -511,7 +511,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -523,7 +523,7 @@ ; CHECK-LABEL: vsrl_vx_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -536,7 +536,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -548,7 +548,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -560,7 +560,7 @@ ; CHECK-LABEL: vsrl_vx_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vsrl.vi v16, v16, 31 +; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret %head = insertelement undef, i64 31, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -573,7 +573,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 32 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsrl.vx v16, v16, a0 +; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 32, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare void @llvm.riscv.vsse.nxv1i32( @@ -7,10 +8,12 @@ i32); define void @intrinsic_vsse_v_nxv1i32_nxv1i32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1i32( %0, * %1, @@ -28,10 +31,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1i32( %0, * %1, @@ -49,10 +54,12 @@ i32); define void @intrinsic_vsse_v_nxv2i32_nxv2i32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2i32( %0, * %1, @@ -70,10 +77,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv2i32_nxv2i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2i32( %0, * %1, @@ -91,10 +100,12 @@ i32); define void @intrinsic_vsse_v_nxv4i32_nxv4i32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4i32( %0, * %1, @@ -112,10 +123,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv4i32_nxv4i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4i32( %0, * %1, @@ -133,10 +146,12 @@ i32); define void @intrinsic_vsse_v_nxv8i32_nxv8i32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8i32( %0, * %1, @@ -154,10 +169,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv8i32_nxv8i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8i32( %0, * %1, @@ -175,10 +192,12 @@ i32); define void @intrinsic_vsse_v_nxv16i32_nxv16i32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16i32( %0, * %1, @@ -196,10 +215,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv16i32_nxv16i32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16i32( %0, * %1, @@ -217,10 +238,12 @@ i32); define void @intrinsic_vsse_v_nxv1f32_nxv1f32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1f32( %0, * %1, @@ -238,10 +261,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv1f32_nxv1f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1f32( %0, * %1, @@ -259,10 +284,12 @@ i32); define void @intrinsic_vsse_v_nxv2f32_nxv2f32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2f32( %0, * %1, @@ -280,10 +307,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv2f32_nxv2f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2f32( %0, * %1, @@ -301,10 +330,12 @@ i32); define void @intrinsic_vsse_v_nxv4f32_nxv4f32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4f32( %0, * %1, @@ -322,10 +353,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv4f32_nxv4f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4f32( %0, * %1, @@ -343,10 +376,12 @@ i32); define void @intrinsic_vsse_v_nxv8f32_nxv8f32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8f32( %0, * %1, @@ -364,10 +399,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv8f32_nxv8f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8f32( %0, * %1, @@ -385,10 +422,12 @@ i32); define void @intrinsic_vsse_v_nxv16f32_nxv16f32( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16f32( %0, * %1, @@ -406,10 +445,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv16f32_nxv16f32( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16f32( %0, * %1, @@ -427,10 +468,12 @@ i32); define void @intrinsic_vsse_v_nxv1i16_nxv1i16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1i16( %0, * %1, @@ -448,10 +491,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv1i16_nxv1i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1i16( %0, * %1, @@ -469,10 +514,12 @@ i32); define void @intrinsic_vsse_v_nxv2i16_nxv2i16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2i16( %0, * %1, @@ -490,10 +537,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv2i16_nxv2i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2i16( %0, * %1, @@ -511,10 +560,12 @@ i32); define void @intrinsic_vsse_v_nxv4i16_nxv4i16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4i16( %0, * %1, @@ -532,10 +583,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv4i16_nxv4i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4i16( %0, * %1, @@ -553,10 +606,12 @@ i32); define void @intrinsic_vsse_v_nxv8i16_nxv8i16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8i16( %0, * %1, @@ -574,10 +629,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv8i16_nxv8i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8i16( %0, * %1, @@ -595,10 +652,12 @@ i32); define void @intrinsic_vsse_v_nxv16i16_nxv16i16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16i16( %0, * %1, @@ -616,10 +675,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv16i16_nxv16i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16i16( %0, * %1, @@ -637,10 +698,12 @@ i32); define void @intrinsic_vsse_v_nxv32i16_nxv32i16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv32i16( %0, * %1, @@ -658,10 +721,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv32i16_nxv32i16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv32i16( %0, * %1, @@ -679,10 +744,12 @@ i32); define void @intrinsic_vsse_v_nxv1f16_nxv1f16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1f16( %0, * %1, @@ -700,10 +767,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv1f16_nxv1f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1f16( %0, * %1, @@ -721,10 +790,12 @@ i32); define void @intrinsic_vsse_v_nxv2f16_nxv2f16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2f16( %0, * %1, @@ -742,10 +813,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv2f16_nxv2f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2f16( %0, * %1, @@ -763,10 +836,12 @@ i32); define void @intrinsic_vsse_v_nxv4f16_nxv4f16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4f16( %0, * %1, @@ -784,10 +859,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv4f16_nxv4f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4f16( %0, * %1, @@ -805,10 +882,12 @@ i32); define void @intrinsic_vsse_v_nxv8f16_nxv8f16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8f16( %0, * %1, @@ -826,10 +905,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv8f16_nxv8f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8f16( %0, * %1, @@ -847,10 +928,12 @@ i32); define void @intrinsic_vsse_v_nxv16f16_nxv16f16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16f16( %0, * %1, @@ -868,10 +951,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv16f16_nxv16f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16f16( %0, * %1, @@ -889,10 +974,12 @@ i32); define void @intrinsic_vsse_v_nxv32f16_nxv32f16( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv32f16( %0, * %1, @@ -910,10 +997,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv32f16_nxv32f16( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv32f16( %0, * %1, @@ -931,10 +1020,12 @@ i32); define void @intrinsic_vsse_v_nxv1i8_nxv1i8( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf8,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1i8( %0, * %1, @@ -952,10 +1043,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv1i8_nxv1i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf8,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1i8( %0, * %1, @@ -973,10 +1066,12 @@ i32); define void @intrinsic_vsse_v_nxv2i8_nxv2i8( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf4,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2i8( %0, * %1, @@ -994,10 +1089,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv2i8_nxv2i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf4,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2i8( %0, * %1, @@ -1015,10 +1112,12 @@ i32); define void @intrinsic_vsse_v_nxv4i8_nxv4i8( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf2,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4i8( %0, * %1, @@ -1036,10 +1135,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv4i8_nxv4i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf2,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4i8( %0, * %1, @@ -1057,10 +1158,12 @@ i32); define void @intrinsic_vsse_v_nxv8i8_nxv8i8( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a2, e8,m1,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8i8( %0, * %1, @@ -1078,10 +1181,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv8i8_nxv8i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a2, e8,m1,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8i8( %0, * %1, @@ -1099,10 +1204,12 @@ i32); define void @intrinsic_vsse_v_nxv16i8_nxv16i8( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a2, e8,m2,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16i8( %0, * %1, @@ -1120,10 +1227,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv16i8_nxv16i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a2, e8,m2,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16i8( %0, * %1, @@ -1141,10 +1250,12 @@ i32); define void @intrinsic_vsse_v_nxv32i8_nxv32i8( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a2, e8,m4,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv32i8( %0, * %1, @@ -1162,10 +1273,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv32i8_nxv32i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a2, e8,m4,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv32i8( %0, * %1, @@ -1183,10 +1296,12 @@ i32); define void @intrinsic_vsse_v_nxv64i8_nxv64i8( %0, * %1, i32 %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a2, e8,m8,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv64i8( %0, * %1, @@ -1204,10 +1319,12 @@ i32); define void @intrinsic_vsse_mask_v_nxv64i8_nxv64i8( %0, * %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a2, e8,m8,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv64i8( %0, * %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare void @llvm.riscv.vsse.nxv1i64( @@ -7,10 +8,12 @@ i64); define void @intrinsic_vsse_v_nxv1i64_nxv1i64( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, a2, e64,m1,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1i64( %0, * %1, @@ -28,10 +31,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv1i64_nxv1i64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, a2, e64,m1,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1i64( %0, * %1, @@ -49,10 +54,12 @@ i64); define void @intrinsic_vsse_v_nxv2i64_nxv2i64( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, a2, e64,m2,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2i64( %0, * %1, @@ -70,10 +77,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv2i64_nxv2i64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, a2, e64,m2,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2i64( %0, * %1, @@ -91,10 +100,12 @@ i64); define void @intrinsic_vsse_v_nxv4i64_nxv4i64( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, a2, e64,m4,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4i64( %0, * %1, @@ -112,10 +123,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv4i64_nxv4i64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, a2, e64,m4,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4i64( %0, * %1, @@ -133,10 +146,12 @@ i64); define void @intrinsic_vsse_v_nxv8i64_nxv8i64( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, a2, e64,m8,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8i64( %0, * %1, @@ -154,10 +169,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv8i64_nxv8i64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, a2, e64,m8,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8i64( %0, * %1, @@ -175,10 +192,12 @@ i64); define void @intrinsic_vsse_v_nxv1f64_nxv1f64( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, a2, e64,m1,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1f64( %0, * %1, @@ -196,10 +215,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv1f64_nxv1f64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f64_nxv1f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f64_nxv1f64 -; CHECK: vsetvli {{.*}}, a2, e64,m1,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1f64( %0, * %1, @@ -217,10 +238,12 @@ i64); define void @intrinsic_vsse_v_nxv2f64_nxv2f64( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, a2, e64,m2,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2f64( %0, * %1, @@ -238,10 +261,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv2f64_nxv2f64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f64_nxv2f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f64_nxv2f64 -; CHECK: vsetvli {{.*}}, a2, e64,m2,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2f64( %0, * %1, @@ -259,10 +284,12 @@ i64); define void @intrinsic_vsse_v_nxv4f64_nxv4f64( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, a2, e64,m4,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4f64( %0, * %1, @@ -280,10 +307,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv4f64_nxv4f64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f64_nxv4f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f64_nxv4f64 -; CHECK: vsetvli {{.*}}, a2, e64,m4,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4f64( %0, * %1, @@ -301,10 +330,12 @@ i64); define void @intrinsic_vsse_v_nxv8f64_nxv8f64( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, a2, e64,m8,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8f64( %0, * %1, @@ -322,10 +353,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv8f64_nxv8f64( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f64_nxv8f64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e64,m8,ta,mu +; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f64_nxv8f64 -; CHECK: vsetvli {{.*}}, a2, e64,m8,ta,mu -; CHECK: vsse64.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8f64( %0, * %1, @@ -343,10 +376,12 @@ i64); define void @intrinsic_vsse_v_nxv1i32_nxv1i32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1i32( %0, * %1, @@ -364,10 +399,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1i32( %0, * %1, @@ -385,10 +422,12 @@ i64); define void @intrinsic_vsse_v_nxv2i32_nxv2i32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2i32( %0, * %1, @@ -406,10 +445,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv2i32_nxv2i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2i32( %0, * %1, @@ -427,10 +468,12 @@ i64); define void @intrinsic_vsse_v_nxv4i32_nxv4i32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4i32( %0, * %1, @@ -448,10 +491,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv4i32_nxv4i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4i32( %0, * %1, @@ -469,10 +514,12 @@ i64); define void @intrinsic_vsse_v_nxv8i32_nxv8i32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8i32( %0, * %1, @@ -490,10 +537,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv8i32_nxv8i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8i32( %0, * %1, @@ -511,10 +560,12 @@ i64); define void @intrinsic_vsse_v_nxv16i32_nxv16i32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16i32( %0, * %1, @@ -532,10 +583,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv16i32_nxv16i32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16i32( %0, * %1, @@ -553,10 +606,12 @@ i64); define void @intrinsic_vsse_v_nxv1f32_nxv1f32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1f32( %0, * %1, @@ -574,10 +629,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv1f32_nxv1f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f32_nxv1f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f32_nxv1f32 -; CHECK: vsetvli {{.*}}, a2, e32,mf2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1f32( %0, * %1, @@ -595,10 +652,12 @@ i64); define void @intrinsic_vsse_v_nxv2f32_nxv2f32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2f32( %0, * %1, @@ -616,10 +675,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv2f32_nxv2f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f32_nxv2f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f32_nxv2f32 -; CHECK: vsetvli {{.*}}, a2, e32,m1,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2f32( %0, * %1, @@ -637,10 +698,12 @@ i64); define void @intrinsic_vsse_v_nxv4f32_nxv4f32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4f32( %0, * %1, @@ -658,10 +721,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv4f32_nxv4f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f32_nxv4f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f32_nxv4f32 -; CHECK: vsetvli {{.*}}, a2, e32,m2,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4f32( %0, * %1, @@ -679,10 +744,12 @@ i64); define void @intrinsic_vsse_v_nxv8f32_nxv8f32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8f32( %0, * %1, @@ -700,10 +767,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv8f32_nxv8f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f32_nxv8f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f32_nxv8f32 -; CHECK: vsetvli {{.*}}, a2, e32,m4,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8f32( %0, * %1, @@ -721,10 +790,12 @@ i64); define void @intrinsic_vsse_v_nxv16f32_nxv16f32( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16f32( %0, * %1, @@ -742,10 +813,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv16f32_nxv16f32( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f32_nxv16f32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e32,m8,ta,mu +; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f32_nxv16f32 -; CHECK: vsetvli {{.*}}, a2, e32,m8,ta,mu -; CHECK: vsse32.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16f32( %0, * %1, @@ -763,10 +836,12 @@ i64); define void @intrinsic_vsse_v_nxv1i16_nxv1i16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1i16( %0, * %1, @@ -784,10 +859,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv1i16_nxv1i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1i16( %0, * %1, @@ -805,10 +882,12 @@ i64); define void @intrinsic_vsse_v_nxv2i16_nxv2i16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2i16( %0, * %1, @@ -826,10 +905,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv2i16_nxv2i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2i16( %0, * %1, @@ -847,10 +928,12 @@ i64); define void @intrinsic_vsse_v_nxv4i16_nxv4i16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4i16( %0, * %1, @@ -868,10 +951,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv4i16_nxv4i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4i16( %0, * %1, @@ -889,10 +974,12 @@ i64); define void @intrinsic_vsse_v_nxv8i16_nxv8i16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8i16( %0, * %1, @@ -910,10 +997,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv8i16_nxv8i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8i16( %0, * %1, @@ -931,10 +1020,12 @@ i64); define void @intrinsic_vsse_v_nxv16i16_nxv16i16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16i16( %0, * %1, @@ -952,10 +1043,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv16i16_nxv16i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16i16( %0, * %1, @@ -973,10 +1066,12 @@ i64); define void @intrinsic_vsse_v_nxv32i16_nxv32i16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv32i16( %0, * %1, @@ -994,10 +1089,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv32i16_nxv32i16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv32i16( %0, * %1, @@ -1015,10 +1112,12 @@ i64); define void @intrinsic_vsse_v_nxv1f16_nxv1f16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1f16( %0, * %1, @@ -1036,10 +1135,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv1f16_nxv1f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f16_nxv1f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f16_nxv1f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1f16( %0, * %1, @@ -1057,10 +1158,12 @@ i64); define void @intrinsic_vsse_v_nxv2f16_nxv2f16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2f16( %0, * %1, @@ -1078,10 +1181,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv2f16_nxv2f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f16_nxv2f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f16_nxv2f16 -; CHECK: vsetvli {{.*}}, a2, e16,mf2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2f16( %0, * %1, @@ -1099,10 +1204,12 @@ i64); define void @intrinsic_vsse_v_nxv4f16_nxv4f16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4f16( %0, * %1, @@ -1120,10 +1227,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv4f16_nxv4f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f16_nxv4f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f16_nxv4f16 -; CHECK: vsetvli {{.*}}, a2, e16,m1,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4f16( %0, * %1, @@ -1141,10 +1250,12 @@ i64); define void @intrinsic_vsse_v_nxv8f16_nxv8f16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8f16( %0, * %1, @@ -1162,10 +1273,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv8f16_nxv8f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f16_nxv8f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f16_nxv8f16 -; CHECK: vsetvli {{.*}}, a2, e16,m2,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8f16( %0, * %1, @@ -1183,10 +1296,12 @@ i64); define void @intrinsic_vsse_v_nxv16f16_nxv16f16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16f16( %0, * %1, @@ -1204,10 +1319,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv16f16_nxv16f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f16_nxv16f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f16_nxv16f16 -; CHECK: vsetvli {{.*}}, a2, e16,m4,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16f16( %0, * %1, @@ -1225,10 +1342,12 @@ i64); define void @intrinsic_vsse_v_nxv32f16_nxv32f16( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv32f16( %0, * %1, @@ -1246,10 +1365,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv32f16_nxv32f16( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32f16_nxv32f16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e16,m8,ta,mu +; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32f16_nxv32f16 -; CHECK: vsetvli {{.*}}, a2, e16,m8,ta,mu -; CHECK: vsse16.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv32f16( %0, * %1, @@ -1267,10 +1388,12 @@ i64); define void @intrinsic_vsse_v_nxv1i8_nxv1i8( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf8,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv1i8( %0, * %1, @@ -1288,10 +1411,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv1i8_nxv1i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf8,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv1i8( %0, * %1, @@ -1309,10 +1434,12 @@ i64); define void @intrinsic_vsse_v_nxv2i8_nxv2i8( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf4,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv2i8( %0, * %1, @@ -1330,10 +1457,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv2i8_nxv2i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf4,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv2i8( %0, * %1, @@ -1351,10 +1480,12 @@ i64); define void @intrinsic_vsse_v_nxv4i8_nxv4i8( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf2,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv4i8( %0, * %1, @@ -1372,10 +1503,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv4i8_nxv4i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, a2, e8,mf2,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv4i8( %0, * %1, @@ -1393,10 +1526,12 @@ i64); define void @intrinsic_vsse_v_nxv8i8_nxv8i8( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a2, e8,m1,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv8i8( %0, * %1, @@ -1414,10 +1549,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv8i8_nxv8i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, a2, e8,m1,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv8i8( %0, * %1, @@ -1435,10 +1572,12 @@ i64); define void @intrinsic_vsse_v_nxv16i8_nxv16i8( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a2, e8,m2,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv16i8( %0, * %1, @@ -1456,10 +1595,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv16i8_nxv16i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, a2, e8,m2,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv16i8( %0, * %1, @@ -1477,10 +1618,12 @@ i64); define void @intrinsic_vsse_v_nxv32i8_nxv32i8( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a2, e8,m4,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv32i8( %0, * %1, @@ -1498,10 +1641,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv32i8_nxv32i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, a2, e8,m4,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv32i8( %0, * %1, @@ -1519,10 +1664,12 @@ i64); define void @intrinsic_vsse_v_nxv64i8_nxv64i8( %0, * %1, i64 %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vsse_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a2, e8,m8,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1 call void @llvm.riscv.vsse.nxv64i8( %0, * %1, @@ -1540,10 +1687,12 @@ i64); define void @intrinsic_vsse_mask_v_nxv64i8_nxv64i8( %0, * %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsse_mask_v_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu +; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsse_mask_v_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, a2, e8,m8,ta,mu -; CHECK: vsse8.v {{v[0-9]+}}, (a0), a1, v0.t call void @llvm.riscv.vsse.mask.nxv64i8( %0, * %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll @@ -8,10 +8,10 @@ define void @test_vsseg2_nxv16i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv16i16( %val, %val, i16* %base, i32 %vl) @@ -21,10 +21,10 @@ define void @test_vsseg2_mask_nxv16i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv16i16( %val, %val, i16* %base, %mask, i32 %vl) @@ -37,10 +37,10 @@ define void @test_vsseg2_nxv1i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1i8( %val, %val, i8* %base, i32 %vl) @@ -50,10 +50,10 @@ define void @test_vsseg2_mask_nxv1i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1i8( %val, %val, i8* %base, %mask, i32 %vl) @@ -66,11 +66,11 @@ define void @test_vsseg3_nxv1i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1i8( %val, %val, %val, i8* %base, i32 %vl) @@ -80,11 +80,11 @@ define void @test_vsseg3_mask_nxv1i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1i8( %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -97,12 +97,12 @@ define void @test_vsseg4_nxv1i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1i8( %val, %val, %val, %val, i8* %base, i32 %vl) @@ -112,12 +112,12 @@ define void @test_vsseg4_mask_nxv1i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1i8( %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -130,13 +130,13 @@ define void @test_vsseg5_nxv1i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0) +; CHECK-NEXT: vsseg5e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1i8( %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -146,13 +146,13 @@ define void @test_vsseg5_mask_nxv1i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1i8( %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -165,14 +165,14 @@ define void @test_vsseg6_nxv1i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0) +; CHECK-NEXT: vsseg6e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -182,14 +182,14 @@ define void @test_vsseg6_mask_nxv1i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1i8( %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -202,15 +202,15 @@ define void @test_vsseg7_nxv1i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0) +; CHECK-NEXT: vsseg7e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -220,15 +220,15 @@ define void @test_vsseg7_mask_nxv1i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -241,16 +241,16 @@ define void @test_vsseg8_nxv1i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0) +; CHECK-NEXT: vsseg8e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -260,16 +260,16 @@ define void @test_vsseg8_mask_nxv1i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -282,10 +282,10 @@ define void @test_vsseg2_nxv16i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv16i8( %val, %val, i8* %base, i32 %vl) @@ -295,10 +295,10 @@ define void @test_vsseg2_mask_nxv16i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv16i8( %val, %val, i8* %base, %mask, i32 %vl) @@ -311,11 +311,11 @@ define void @test_vsseg3_nxv16i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv16i8( %val, %val, %val, i8* %base, i32 %vl) @@ -325,11 +325,11 @@ define void @test_vsseg3_mask_nxv16i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv16i8( %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -342,12 +342,12 @@ define void @test_vsseg4_nxv16i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv16i8( %val, %val, %val, %val, i8* %base, i32 %vl) @@ -357,12 +357,12 @@ define void @test_vsseg4_mask_nxv16i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv16i8( %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -375,10 +375,10 @@ define void @test_vsseg2_nxv2i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2i32( %val, %val, i32* %base, i32 %vl) @@ -388,10 +388,10 @@ define void @test_vsseg2_mask_nxv2i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2i32( %val, %val, i32* %base, %mask, i32 %vl) @@ -404,11 +404,11 @@ define void @test_vsseg3_nxv2i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2i32( %val, %val, %val, i32* %base, i32 %vl) @@ -418,11 +418,11 @@ define void @test_vsseg3_mask_nxv2i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2i32( %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -435,12 +435,12 @@ define void @test_vsseg4_nxv2i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2i32( %val, %val, %val, %val, i32* %base, i32 %vl) @@ -450,12 +450,12 @@ define void @test_vsseg4_mask_nxv2i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2i32( %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -468,13 +468,13 @@ define void @test_vsseg5_nxv2i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0) +; CHECK-NEXT: vsseg5e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2i32( %val, %val, %val, %val, %val, i32* %base, i32 %vl) @@ -484,13 +484,13 @@ define void @test_vsseg5_mask_nxv2i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2i32( %val, %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -503,14 +503,14 @@ define void @test_vsseg6_nxv2i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0) +; CHECK-NEXT: vsseg6e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2i32( %val, %val, %val, %val, %val, %val, i32* %base, i32 %vl) @@ -520,14 +520,14 @@ define void @test_vsseg6_mask_nxv2i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2i32( %val, %val, %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -540,15 +540,15 @@ define void @test_vsseg7_nxv2i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0) +; CHECK-NEXT: vsseg7e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %vl) @@ -558,15 +558,15 @@ define void @test_vsseg7_mask_nxv2i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -579,16 +579,16 @@ define void @test_vsseg8_nxv2i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0) +; CHECK-NEXT: vsseg8e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %vl) @@ -598,16 +598,16 @@ define void @test_vsseg8_mask_nxv2i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -620,10 +620,10 @@ define void @test_vsseg2_nxv4i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4i16( %val, %val, i16* %base, i32 %vl) @@ -633,10 +633,10 @@ define void @test_vsseg2_mask_nxv4i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4i16( %val, %val, i16* %base, %mask, i32 %vl) @@ -649,11 +649,11 @@ define void @test_vsseg3_nxv4i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4i16( %val, %val, %val, i16* %base, i32 %vl) @@ -663,11 +663,11 @@ define void @test_vsseg3_mask_nxv4i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4i16( %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -680,12 +680,12 @@ define void @test_vsseg4_nxv4i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4i16( %val, %val, %val, %val, i16* %base, i32 %vl) @@ -695,12 +695,12 @@ define void @test_vsseg4_mask_nxv4i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4i16( %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -713,13 +713,13 @@ define void @test_vsseg5_nxv4i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv4i16( %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -729,13 +729,13 @@ define void @test_vsseg5_mask_nxv4i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv4i16( %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -748,14 +748,14 @@ define void @test_vsseg6_nxv4i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv4i16( %val, %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -765,14 +765,14 @@ define void @test_vsseg6_mask_nxv4i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv4i16( %val, %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -785,15 +785,15 @@ define void @test_vsseg7_nxv4i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv4i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -803,15 +803,15 @@ define void @test_vsseg7_mask_nxv4i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv4i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -824,16 +824,16 @@ define void @test_vsseg8_nxv4i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv4i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -843,16 +843,16 @@ define void @test_vsseg8_mask_nxv4i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv4i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -865,10 +865,10 @@ define void @test_vsseg2_nxv1i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1i32( %val, %val, i32* %base, i32 %vl) @@ -878,10 +878,10 @@ define void @test_vsseg2_mask_nxv1i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1i32( %val, %val, i32* %base, %mask, i32 %vl) @@ -894,11 +894,11 @@ define void @test_vsseg3_nxv1i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1i32( %val, %val, %val, i32* %base, i32 %vl) @@ -908,11 +908,11 @@ define void @test_vsseg3_mask_nxv1i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1i32( %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -925,12 +925,12 @@ define void @test_vsseg4_nxv1i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1i32( %val, %val, %val, %val, i32* %base, i32 %vl) @@ -940,12 +940,12 @@ define void @test_vsseg4_mask_nxv1i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1i32( %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -958,13 +958,13 @@ define void @test_vsseg5_nxv1i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0) +; CHECK-NEXT: vsseg5e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1i32( %val, %val, %val, %val, %val, i32* %base, i32 %vl) @@ -974,13 +974,13 @@ define void @test_vsseg5_mask_nxv1i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1i32( %val, %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -993,14 +993,14 @@ define void @test_vsseg6_nxv1i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0) +; CHECK-NEXT: vsseg6e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1i32( %val, %val, %val, %val, %val, %val, i32* %base, i32 %vl) @@ -1010,14 +1010,14 @@ define void @test_vsseg6_mask_nxv1i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1i32( %val, %val, %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -1030,15 +1030,15 @@ define void @test_vsseg7_nxv1i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0) +; CHECK-NEXT: vsseg7e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %vl) @@ -1048,15 +1048,15 @@ define void @test_vsseg7_mask_nxv1i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -1069,16 +1069,16 @@ define void @test_vsseg8_nxv1i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0) +; CHECK-NEXT: vsseg8e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %vl) @@ -1088,16 +1088,16 @@ define void @test_vsseg8_mask_nxv1i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -1110,10 +1110,10 @@ define void @test_vsseg2_nxv8i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8i16( %val, %val, i16* %base, i32 %vl) @@ -1123,10 +1123,10 @@ define void @test_vsseg2_mask_nxv8i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8i16( %val, %val, i16* %base, %mask, i32 %vl) @@ -1139,11 +1139,11 @@ define void @test_vsseg3_nxv8i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv8i16( %val, %val, %val, i16* %base, i32 %vl) @@ -1153,11 +1153,11 @@ define void @test_vsseg3_mask_nxv8i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv8i16( %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -1170,12 +1170,12 @@ define void @test_vsseg4_nxv8i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv8i16( %val, %val, %val, %val, i16* %base, i32 %vl) @@ -1185,12 +1185,12 @@ define void @test_vsseg4_mask_nxv8i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv8i16( %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -1203,10 +1203,10 @@ define void @test_vsseg2_nxv8i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8i8( %val, %val, i8* %base, i32 %vl) @@ -1216,10 +1216,10 @@ define void @test_vsseg2_mask_nxv8i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8i8( %val, %val, i8* %base, %mask, i32 %vl) @@ -1232,11 +1232,11 @@ define void @test_vsseg3_nxv8i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv8i8( %val, %val, %val, i8* %base, i32 %vl) @@ -1246,11 +1246,11 @@ define void @test_vsseg3_mask_nxv8i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv8i8( %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1263,12 +1263,12 @@ define void @test_vsseg4_nxv8i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv8i8( %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1278,12 +1278,12 @@ define void @test_vsseg4_mask_nxv8i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv8i8( %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1296,13 +1296,13 @@ define void @test_vsseg5_nxv8i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0) +; CHECK-NEXT: vsseg5e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv8i8( %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1312,13 +1312,13 @@ define void @test_vsseg5_mask_nxv8i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv8i8( %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1331,14 +1331,14 @@ define void @test_vsseg6_nxv8i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0) +; CHECK-NEXT: vsseg6e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv8i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1348,14 +1348,14 @@ define void @test_vsseg6_mask_nxv8i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv8i8( %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1368,15 +1368,15 @@ define void @test_vsseg7_nxv8i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0) +; CHECK-NEXT: vsseg7e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv8i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1386,15 +1386,15 @@ define void @test_vsseg7_mask_nxv8i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv8i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1407,16 +1407,16 @@ define void @test_vsseg8_nxv8i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0) +; CHECK-NEXT: vsseg8e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv8i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1426,16 +1426,16 @@ define void @test_vsseg8_mask_nxv8i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv8i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1448,10 +1448,10 @@ define void @test_vsseg2_nxv8i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8i32( %val, %val, i32* %base, i32 %vl) @@ -1461,10 +1461,10 @@ define void @test_vsseg2_mask_nxv8i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8i32( %val, %val, i32* %base, %mask, i32 %vl) @@ -1477,10 +1477,10 @@ define void @test_vsseg2_nxv4i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4i8( %val, %val, i8* %base, i32 %vl) @@ -1490,10 +1490,10 @@ define void @test_vsseg2_mask_nxv4i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4i8( %val, %val, i8* %base, %mask, i32 %vl) @@ -1506,11 +1506,11 @@ define void @test_vsseg3_nxv4i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4i8( %val, %val, %val, i8* %base, i32 %vl) @@ -1520,11 +1520,11 @@ define void @test_vsseg3_mask_nxv4i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4i8( %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1537,12 +1537,12 @@ define void @test_vsseg4_nxv4i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4i8( %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1552,12 +1552,12 @@ define void @test_vsseg4_mask_nxv4i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4i8( %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1570,13 +1570,13 @@ define void @test_vsseg5_nxv4i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0) +; CHECK-NEXT: vsseg5e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv4i8( %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1586,13 +1586,13 @@ define void @test_vsseg5_mask_nxv4i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv4i8( %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1605,14 +1605,14 @@ define void @test_vsseg6_nxv4i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0) +; CHECK-NEXT: vsseg6e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv4i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1622,14 +1622,14 @@ define void @test_vsseg6_mask_nxv4i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv4i8( %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1642,15 +1642,15 @@ define void @test_vsseg7_nxv4i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0) +; CHECK-NEXT: vsseg7e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv4i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1660,15 +1660,15 @@ define void @test_vsseg7_mask_nxv4i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv4i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1681,16 +1681,16 @@ define void @test_vsseg8_nxv4i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0) +; CHECK-NEXT: vsseg8e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv4i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -1700,16 +1700,16 @@ define void @test_vsseg8_mask_nxv4i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv4i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -1722,10 +1722,10 @@ define void @test_vsseg2_nxv1i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1i16( %val, %val, i16* %base, i32 %vl) @@ -1735,10 +1735,10 @@ define void @test_vsseg2_mask_nxv1i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1i16( %val, %val, i16* %base, %mask, i32 %vl) @@ -1751,11 +1751,11 @@ define void @test_vsseg3_nxv1i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1i16( %val, %val, %val, i16* %base, i32 %vl) @@ -1765,11 +1765,11 @@ define void @test_vsseg3_mask_nxv1i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1i16( %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -1782,12 +1782,12 @@ define void @test_vsseg4_nxv1i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1i16( %val, %val, %val, %val, i16* %base, i32 %vl) @@ -1797,12 +1797,12 @@ define void @test_vsseg4_mask_nxv1i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1i16( %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -1815,13 +1815,13 @@ define void @test_vsseg5_nxv1i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1i16( %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -1831,13 +1831,13 @@ define void @test_vsseg5_mask_nxv1i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1i16( %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -1850,14 +1850,14 @@ define void @test_vsseg6_nxv1i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1i16( %val, %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -1867,14 +1867,14 @@ define void @test_vsseg6_mask_nxv1i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1i16( %val, %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -1887,15 +1887,15 @@ define void @test_vsseg7_nxv1i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -1905,15 +1905,15 @@ define void @test_vsseg7_mask_nxv1i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -1926,16 +1926,16 @@ define void @test_vsseg8_nxv1i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -1945,16 +1945,16 @@ define void @test_vsseg8_mask_nxv1i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -1967,10 +1967,10 @@ define void @test_vsseg2_nxv32i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv32i8( %val, %val, i8* %base, i32 %vl) @@ -1980,10 +1980,10 @@ define void @test_vsseg2_mask_nxv32i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv32i8( %val, %val, i8* %base, %mask, i32 %vl) @@ -1996,10 +1996,10 @@ define void @test_vsseg2_nxv2i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2i8( %val, %val, i8* %base, i32 %vl) @@ -2009,10 +2009,10 @@ define void @test_vsseg2_mask_nxv2i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2i8( %val, %val, i8* %base, %mask, i32 %vl) @@ -2025,11 +2025,11 @@ define void @test_vsseg3_nxv2i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2i8( %val, %val, %val, i8* %base, i32 %vl) @@ -2039,11 +2039,11 @@ define void @test_vsseg3_mask_nxv2i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2i8( %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -2056,12 +2056,12 @@ define void @test_vsseg4_nxv2i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2i8( %val, %val, %val, %val, i8* %base, i32 %vl) @@ -2071,12 +2071,12 @@ define void @test_vsseg4_mask_nxv2i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2i8( %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -2089,13 +2089,13 @@ define void @test_vsseg5_nxv2i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0) +; CHECK-NEXT: vsseg5e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2i8( %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -2105,13 +2105,13 @@ define void @test_vsseg5_mask_nxv2i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2i8( %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -2124,14 +2124,14 @@ define void @test_vsseg6_nxv2i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0) +; CHECK-NEXT: vsseg6e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -2141,14 +2141,14 @@ define void @test_vsseg6_mask_nxv2i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2i8( %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -2161,15 +2161,15 @@ define void @test_vsseg7_nxv2i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0) +; CHECK-NEXT: vsseg7e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -2179,15 +2179,15 @@ define void @test_vsseg7_mask_nxv2i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -2200,16 +2200,16 @@ define void @test_vsseg8_nxv2i8( %val, i8* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0) +; CHECK-NEXT: vsseg8e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %vl) @@ -2219,16 +2219,16 @@ define void @test_vsseg8_mask_nxv2i8( %val, i8* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i32 %vl) @@ -2241,10 +2241,10 @@ define void @test_vsseg2_nxv2i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2i16( %val, %val, i16* %base, i32 %vl) @@ -2254,10 +2254,10 @@ define void @test_vsseg2_mask_nxv2i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2i16( %val, %val, i16* %base, %mask, i32 %vl) @@ -2270,11 +2270,11 @@ define void @test_vsseg3_nxv2i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2i16( %val, %val, %val, i16* %base, i32 %vl) @@ -2284,11 +2284,11 @@ define void @test_vsseg3_mask_nxv2i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2i16( %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -2301,12 +2301,12 @@ define void @test_vsseg4_nxv2i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2i16( %val, %val, %val, %val, i16* %base, i32 %vl) @@ -2316,12 +2316,12 @@ define void @test_vsseg4_mask_nxv2i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2i16( %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -2334,13 +2334,13 @@ define void @test_vsseg5_nxv2i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2i16( %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -2350,13 +2350,13 @@ define void @test_vsseg5_mask_nxv2i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2i16( %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -2369,14 +2369,14 @@ define void @test_vsseg6_nxv2i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2i16( %val, %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -2386,14 +2386,14 @@ define void @test_vsseg6_mask_nxv2i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2i16( %val, %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -2406,15 +2406,15 @@ define void @test_vsseg7_nxv2i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -2424,15 +2424,15 @@ define void @test_vsseg7_mask_nxv2i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -2445,16 +2445,16 @@ define void @test_vsseg8_nxv2i16( %val, i16* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %vl) @@ -2464,16 +2464,16 @@ define void @test_vsseg8_mask_nxv2i16( %val, i16* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i32 %vl) @@ -2486,10 +2486,10 @@ define void @test_vsseg2_nxv4i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4i32( %val, %val, i32* %base, i32 %vl) @@ -2499,10 +2499,10 @@ define void @test_vsseg2_mask_nxv4i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4i32( %val, %val, i32* %base, %mask, i32 %vl) @@ -2515,11 +2515,11 @@ define void @test_vsseg3_nxv4i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4i32( %val, %val, %val, i32* %base, i32 %vl) @@ -2529,11 +2529,11 @@ define void @test_vsseg3_mask_nxv4i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4i32( %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -2546,12 +2546,12 @@ define void @test_vsseg4_nxv4i32( %val, i32* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4i32( %val, %val, %val, %val, i32* %base, i32 %vl) @@ -2561,12 +2561,12 @@ define void @test_vsseg4_mask_nxv4i32( %val, i32* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4i32( %val, %val, %val, %val, i32* %base, %mask, i32 %vl) @@ -2579,10 +2579,10 @@ define void @test_vsseg2_nxv16f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv16f16( %val, %val, half* %base, i32 %vl) @@ -2592,10 +2592,10 @@ define void @test_vsseg2_mask_nxv16f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv16f16( %val, %val, half* %base, %mask, i32 %vl) @@ -2608,10 +2608,10 @@ define void @test_vsseg2_nxv4f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0) +; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4f64( %val, %val, double* %base, i32 %vl) @@ -2621,10 +2621,10 @@ define void @test_vsseg2_mask_nxv4f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4f64( %val, %val, double* %base, %mask, i32 %vl) @@ -2637,10 +2637,10 @@ define void @test_vsseg2_nxv1f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0) +; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1f64( %val, %val, double* %base, i32 %vl) @@ -2650,10 +2650,10 @@ define void @test_vsseg2_mask_nxv1f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1f64( %val, %val, double* %base, %mask, i32 %vl) @@ -2666,11 +2666,11 @@ define void @test_vsseg3_nxv1f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0) +; CHECK-NEXT: vsseg3e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1f64( %val, %val, %val, double* %base, i32 %vl) @@ -2680,11 +2680,11 @@ define void @test_vsseg3_mask_nxv1f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1f64( %val, %val, %val, double* %base, %mask, i32 %vl) @@ -2697,12 +2697,12 @@ define void @test_vsseg4_nxv1f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0) +; CHECK-NEXT: vsseg4e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1f64( %val, %val, %val, %val, double* %base, i32 %vl) @@ -2712,12 +2712,12 @@ define void @test_vsseg4_mask_nxv1f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1f64( %val, %val, %val, %val, double* %base, %mask, i32 %vl) @@ -2730,13 +2730,13 @@ define void @test_vsseg5_nxv1f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg5e64.v v16, (a0) +; CHECK-NEXT: vsseg5e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1f64( %val, %val, %val, %val, %val, double* %base, i32 %vl) @@ -2746,13 +2746,13 @@ define void @test_vsseg5_mask_nxv1f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg5e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1f64( %val, %val, %val, %val, %val, double* %base, %mask, i32 %vl) @@ -2765,14 +2765,14 @@ define void @test_vsseg6_nxv1f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg6e64.v v16, (a0) +; CHECK-NEXT: vsseg6e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1f64( %val, %val, %val, %val, %val, %val, double* %base, i32 %vl) @@ -2782,14 +2782,14 @@ define void @test_vsseg6_mask_nxv1f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg6e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1f64( %val, %val, %val, %val, %val, %val, double* %base, %mask, i32 %vl) @@ -2802,15 +2802,15 @@ define void @test_vsseg7_nxv1f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg7e64.v v16, (a0) +; CHECK-NEXT: vsseg7e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1f64( %val, %val, %val, %val, %val, %val, %val, double* %base, i32 %vl) @@ -2820,15 +2820,15 @@ define void @test_vsseg7_mask_nxv1f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg7e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1f64( %val, %val, %val, %val, %val, %val, %val, double* %base, %mask, i32 %vl) @@ -2841,16 +2841,16 @@ define void @test_vsseg8_nxv1f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg8e64.v v16, (a0) +; CHECK-NEXT: vsseg8e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1f64( %val, %val, %val, %val, %val, %val, %val, %val, double* %base, i32 %vl) @@ -2860,16 +2860,16 @@ define void @test_vsseg8_mask_nxv1f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg8e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1f64( %val, %val, %val, %val, %val, %val, %val, %val, double* %base, %mask, i32 %vl) @@ -2882,10 +2882,10 @@ define void @test_vsseg2_nxv2f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2f32( %val, %val, float* %base, i32 %vl) @@ -2895,10 +2895,10 @@ define void @test_vsseg2_mask_nxv2f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2f32( %val, %val, float* %base, %mask, i32 %vl) @@ -2911,11 +2911,11 @@ define void @test_vsseg3_nxv2f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2f32( %val, %val, %val, float* %base, i32 %vl) @@ -2925,11 +2925,11 @@ define void @test_vsseg3_mask_nxv2f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2f32( %val, %val, %val, float* %base, %mask, i32 %vl) @@ -2942,12 +2942,12 @@ define void @test_vsseg4_nxv2f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2f32( %val, %val, %val, %val, float* %base, i32 %vl) @@ -2957,12 +2957,12 @@ define void @test_vsseg4_mask_nxv2f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2f32( %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -2975,13 +2975,13 @@ define void @test_vsseg5_nxv2f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0) +; CHECK-NEXT: vsseg5e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2f32( %val, %val, %val, %val, %val, float* %base, i32 %vl) @@ -2991,13 +2991,13 @@ define void @test_vsseg5_mask_nxv2f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2f32( %val, %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3010,14 +3010,14 @@ define void @test_vsseg6_nxv2f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0) +; CHECK-NEXT: vsseg6e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2f32( %val, %val, %val, %val, %val, %val, float* %base, i32 %vl) @@ -3027,14 +3027,14 @@ define void @test_vsseg6_mask_nxv2f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2f32( %val, %val, %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3047,15 +3047,15 @@ define void @test_vsseg7_nxv2f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0) +; CHECK-NEXT: vsseg7e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %vl) @@ -3065,15 +3065,15 @@ define void @test_vsseg7_mask_nxv2f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2f32( %val, %val, %val, %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3086,16 +3086,16 @@ define void @test_vsseg8_nxv2f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0) +; CHECK-NEXT: vsseg8e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %vl) @@ -3105,16 +3105,16 @@ define void @test_vsseg8_mask_nxv2f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3127,10 +3127,10 @@ define void @test_vsseg2_nxv1f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1f16( %val, %val, half* %base, i32 %vl) @@ -3140,10 +3140,10 @@ define void @test_vsseg2_mask_nxv1f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1f16( %val, %val, half* %base, %mask, i32 %vl) @@ -3156,11 +3156,11 @@ define void @test_vsseg3_nxv1f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1f16( %val, %val, %val, half* %base, i32 %vl) @@ -3170,11 +3170,11 @@ define void @test_vsseg3_mask_nxv1f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1f16( %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3187,12 +3187,12 @@ define void @test_vsseg4_nxv1f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1f16( %val, %val, %val, %val, half* %base, i32 %vl) @@ -3202,12 +3202,12 @@ define void @test_vsseg4_mask_nxv1f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1f16( %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3220,13 +3220,13 @@ define void @test_vsseg5_nxv1f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1f16( %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -3236,13 +3236,13 @@ define void @test_vsseg5_mask_nxv1f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1f16( %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3255,14 +3255,14 @@ define void @test_vsseg6_nxv1f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1f16( %val, %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -3272,14 +3272,14 @@ define void @test_vsseg6_mask_nxv1f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1f16( %val, %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3292,15 +3292,15 @@ define void @test_vsseg7_nxv1f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -3310,15 +3310,15 @@ define void @test_vsseg7_mask_nxv1f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1f16( %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3331,16 +3331,16 @@ define void @test_vsseg8_nxv1f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -3350,16 +3350,16 @@ define void @test_vsseg8_mask_nxv1f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3372,10 +3372,10 @@ define void @test_vsseg2_nxv1f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1f32( %val, %val, float* %base, i32 %vl) @@ -3385,10 +3385,10 @@ define void @test_vsseg2_mask_nxv1f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1f32( %val, %val, float* %base, %mask, i32 %vl) @@ -3401,11 +3401,11 @@ define void @test_vsseg3_nxv1f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1f32( %val, %val, %val, float* %base, i32 %vl) @@ -3415,11 +3415,11 @@ define void @test_vsseg3_mask_nxv1f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1f32( %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3432,12 +3432,12 @@ define void @test_vsseg4_nxv1f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1f32( %val, %val, %val, %val, float* %base, i32 %vl) @@ -3447,12 +3447,12 @@ define void @test_vsseg4_mask_nxv1f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1f32( %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3465,13 +3465,13 @@ define void @test_vsseg5_nxv1f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0) +; CHECK-NEXT: vsseg5e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1f32( %val, %val, %val, %val, %val, float* %base, i32 %vl) @@ -3481,13 +3481,13 @@ define void @test_vsseg5_mask_nxv1f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1f32( %val, %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3500,14 +3500,14 @@ define void @test_vsseg6_nxv1f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0) +; CHECK-NEXT: vsseg6e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1f32( %val, %val, %val, %val, %val, %val, float* %base, i32 %vl) @@ -3517,14 +3517,14 @@ define void @test_vsseg6_mask_nxv1f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1f32( %val, %val, %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3537,15 +3537,15 @@ define void @test_vsseg7_nxv1f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0) +; CHECK-NEXT: vsseg7e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %vl) @@ -3555,15 +3555,15 @@ define void @test_vsseg7_mask_nxv1f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1f32( %val, %val, %val, %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3576,16 +3576,16 @@ define void @test_vsseg8_nxv1f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0) +; CHECK-NEXT: vsseg8e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %vl) @@ -3595,16 +3595,16 @@ define void @test_vsseg8_mask_nxv1f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, %mask, i32 %vl) @@ -3617,10 +3617,10 @@ define void @test_vsseg2_nxv8f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8f16( %val, %val, half* %base, i32 %vl) @@ -3630,10 +3630,10 @@ define void @test_vsseg2_mask_nxv8f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8f16( %val, %val, half* %base, %mask, i32 %vl) @@ -3646,11 +3646,11 @@ define void @test_vsseg3_nxv8f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv8f16( %val, %val, %val, half* %base, i32 %vl) @@ -3660,11 +3660,11 @@ define void @test_vsseg3_mask_nxv8f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv8f16( %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3677,12 +3677,12 @@ define void @test_vsseg4_nxv8f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv8f16( %val, %val, %val, %val, half* %base, i32 %vl) @@ -3692,12 +3692,12 @@ define void @test_vsseg4_mask_nxv8f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv8f16( %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3710,10 +3710,10 @@ define void @test_vsseg2_nxv8f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8f32( %val, %val, float* %base, i32 %vl) @@ -3723,10 +3723,10 @@ define void @test_vsseg2_mask_nxv8f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8f32( %val, %val, float* %base, %mask, i32 %vl) @@ -3739,10 +3739,10 @@ define void @test_vsseg2_nxv2f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0) +; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2f64( %val, %val, double* %base, i32 %vl) @@ -3752,10 +3752,10 @@ define void @test_vsseg2_mask_nxv2f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2f64( %val, %val, double* %base, %mask, i32 %vl) @@ -3768,11 +3768,11 @@ define void @test_vsseg3_nxv2f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0) +; CHECK-NEXT: vsseg3e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2f64( %val, %val, %val, double* %base, i32 %vl) @@ -3782,11 +3782,11 @@ define void @test_vsseg3_mask_nxv2f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2f64( %val, %val, %val, double* %base, %mask, i32 %vl) @@ -3799,12 +3799,12 @@ define void @test_vsseg4_nxv2f64( %val, double* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0) +; CHECK-NEXT: vsseg4e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2f64( %val, %val, %val, %val, double* %base, i32 %vl) @@ -3814,12 +3814,12 @@ define void @test_vsseg4_mask_nxv2f64( %val, double* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2f64( %val, %val, %val, %val, double* %base, %mask, i32 %vl) @@ -3832,10 +3832,10 @@ define void @test_vsseg2_nxv4f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4f16( %val, %val, half* %base, i32 %vl) @@ -3845,10 +3845,10 @@ define void @test_vsseg2_mask_nxv4f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4f16( %val, %val, half* %base, %mask, i32 %vl) @@ -3861,11 +3861,11 @@ define void @test_vsseg3_nxv4f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4f16( %val, %val, %val, half* %base, i32 %vl) @@ -3875,11 +3875,11 @@ define void @test_vsseg3_mask_nxv4f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4f16( %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3892,12 +3892,12 @@ define void @test_vsseg4_nxv4f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4f16( %val, %val, %val, %val, half* %base, i32 %vl) @@ -3907,12 +3907,12 @@ define void @test_vsseg4_mask_nxv4f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4f16( %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3925,13 +3925,13 @@ define void @test_vsseg5_nxv4f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv4f16( %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -3941,13 +3941,13 @@ define void @test_vsseg5_mask_nxv4f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv4f16( %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3960,14 +3960,14 @@ define void @test_vsseg6_nxv4f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv4f16( %val, %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -3977,14 +3977,14 @@ define void @test_vsseg6_mask_nxv4f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv4f16( %val, %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -3997,15 +3997,15 @@ define void @test_vsseg7_nxv4f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv4f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -4015,15 +4015,15 @@ define void @test_vsseg7_mask_nxv4f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv4f16( %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -4036,16 +4036,16 @@ define void @test_vsseg8_nxv4f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv4f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -4055,16 +4055,16 @@ define void @test_vsseg8_mask_nxv4f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv4f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -4077,10 +4077,10 @@ define void @test_vsseg2_nxv2f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2f16( %val, %val, half* %base, i32 %vl) @@ -4090,10 +4090,10 @@ define void @test_vsseg2_mask_nxv2f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2f16( %val, %val, half* %base, %mask, i32 %vl) @@ -4106,11 +4106,11 @@ define void @test_vsseg3_nxv2f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2f16( %val, %val, %val, half* %base, i32 %vl) @@ -4120,11 +4120,11 @@ define void @test_vsseg3_mask_nxv2f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2f16( %val, %val, %val, half* %base, %mask, i32 %vl) @@ -4137,12 +4137,12 @@ define void @test_vsseg4_nxv2f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2f16( %val, %val, %val, %val, half* %base, i32 %vl) @@ -4152,12 +4152,12 @@ define void @test_vsseg4_mask_nxv2f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2f16( %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -4170,13 +4170,13 @@ define void @test_vsseg5_nxv2f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2f16( %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -4186,13 +4186,13 @@ define void @test_vsseg5_mask_nxv2f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2f16( %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -4205,14 +4205,14 @@ define void @test_vsseg6_nxv2f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2f16( %val, %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -4222,14 +4222,14 @@ define void @test_vsseg6_mask_nxv2f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2f16( %val, %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -4242,15 +4242,15 @@ define void @test_vsseg7_nxv2f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -4260,15 +4260,15 @@ define void @test_vsseg7_mask_nxv2f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2f16( %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -4281,16 +4281,16 @@ define void @test_vsseg8_nxv2f16( %val, half* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %vl) @@ -4300,16 +4300,16 @@ define void @test_vsseg8_mask_nxv2f16( %val, half* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i32 %vl) @@ -4322,10 +4322,10 @@ define void @test_vsseg2_nxv4f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4f32( %val, %val, float* %base, i32 %vl) @@ -4335,10 +4335,10 @@ define void @test_vsseg2_mask_nxv4f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4f32( %val, %val, float* %base, %mask, i32 %vl) @@ -4351,11 +4351,11 @@ define void @test_vsseg3_nxv4f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4f32( %val, %val, %val, float* %base, i32 %vl) @@ -4365,11 +4365,11 @@ define void @test_vsseg3_mask_nxv4f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4f32( %val, %val, %val, float* %base, %mask, i32 %vl) @@ -4382,12 +4382,12 @@ define void @test_vsseg4_nxv4f32( %val, float* %base, i32 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4f32( %val, %val, %val, %val, float* %base, i32 %vl) @@ -4397,12 +4397,12 @@ define void @test_vsseg4_mask_nxv4f32( %val, float* %base, %mask, i32 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4f32( %val, %val, %val, %val, float* %base, %mask, i32 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll @@ -8,10 +8,10 @@ define void @test_vsseg2_nxv16i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv16i16( %val, %val, i16* %base, i64 %vl) @@ -21,10 +21,10 @@ define void @test_vsseg2_mask_nxv16i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv16i16( %val, %val, i16* %base, %mask, i64 %vl) @@ -37,10 +37,10 @@ define void @test_vsseg2_nxv4i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4i32( %val, %val, i32* %base, i64 %vl) @@ -50,10 +50,10 @@ define void @test_vsseg2_mask_nxv4i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4i32( %val, %val, i32* %base, %mask, i64 %vl) @@ -66,11 +66,11 @@ define void @test_vsseg3_nxv4i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4i32( %val, %val, %val, i32* %base, i64 %vl) @@ -80,11 +80,11 @@ define void @test_vsseg3_mask_nxv4i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4i32( %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -97,12 +97,12 @@ define void @test_vsseg4_nxv4i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4i32( %val, %val, %val, %val, i32* %base, i64 %vl) @@ -112,12 +112,12 @@ define void @test_vsseg4_mask_nxv4i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4i32( %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -130,10 +130,10 @@ define void @test_vsseg2_nxv16i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv16i8( %val, %val, i8* %base, i64 %vl) @@ -143,10 +143,10 @@ define void @test_vsseg2_mask_nxv16i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv16i8( %val, %val, i8* %base, %mask, i64 %vl) @@ -159,11 +159,11 @@ define void @test_vsseg3_nxv16i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv16i8( %val, %val, %val, i8* %base, i64 %vl) @@ -173,11 +173,11 @@ define void @test_vsseg3_mask_nxv16i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv16i8( %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -190,12 +190,12 @@ define void @test_vsseg4_nxv16i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv16i8( %val, %val, %val, %val, i8* %base, i64 %vl) @@ -205,12 +205,12 @@ define void @test_vsseg4_mask_nxv16i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv16i8( %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -223,10 +223,10 @@ define void @test_vsseg2_nxv1i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0) +; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1i64( %val, %val, i64* %base, i64 %vl) @@ -236,10 +236,10 @@ define void @test_vsseg2_mask_nxv1i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1i64( %val, %val, i64* %base, %mask, i64 %vl) @@ -252,11 +252,11 @@ define void @test_vsseg3_nxv1i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0) +; CHECK-NEXT: vsseg3e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1i64( %val, %val, %val, i64* %base, i64 %vl) @@ -266,11 +266,11 @@ define void @test_vsseg3_mask_nxv1i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1i64( %val, %val, %val, i64* %base, %mask, i64 %vl) @@ -283,12 +283,12 @@ define void @test_vsseg4_nxv1i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0) +; CHECK-NEXT: vsseg4e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1i64( %val, %val, %val, %val, i64* %base, i64 %vl) @@ -298,12 +298,12 @@ define void @test_vsseg4_mask_nxv1i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1i64( %val, %val, %val, %val, i64* %base, %mask, i64 %vl) @@ -316,13 +316,13 @@ define void @test_vsseg5_nxv1i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg5e64.v v16, (a0) +; CHECK-NEXT: vsseg5e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1i64( %val, %val, %val, %val, %val, i64* %base, i64 %vl) @@ -332,13 +332,13 @@ define void @test_vsseg5_mask_nxv1i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg5e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1i64( %val, %val, %val, %val, %val, i64* %base, %mask, i64 %vl) @@ -351,14 +351,14 @@ define void @test_vsseg6_nxv1i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg6e64.v v16, (a0) +; CHECK-NEXT: vsseg6e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1i64( %val, %val, %val, %val, %val, %val, i64* %base, i64 %vl) @@ -368,14 +368,14 @@ define void @test_vsseg6_mask_nxv1i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg6e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1i64( %val, %val, %val, %val, %val, %val, i64* %base, %mask, i64 %vl) @@ -388,15 +388,15 @@ define void @test_vsseg7_nxv1i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg7e64.v v16, (a0) +; CHECK-NEXT: vsseg7e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1i64( %val, %val, %val, %val, %val, %val, %val, i64* %base, i64 %vl) @@ -406,15 +406,15 @@ define void @test_vsseg7_mask_nxv1i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg7e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1i64( %val, %val, %val, %val, %val, %val, %val, i64* %base, %mask, i64 %vl) @@ -427,16 +427,16 @@ define void @test_vsseg8_nxv1i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg8e64.v v16, (a0) +; CHECK-NEXT: vsseg8e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1i64( %val, %val, %val, %val, %val, %val, %val, %val, i64* %base, i64 %vl) @@ -446,16 +446,16 @@ define void @test_vsseg8_mask_nxv1i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg8e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1i64( %val, %val, %val, %val, %val, %val, %val, %val, i64* %base, %mask, i64 %vl) @@ -468,10 +468,10 @@ define void @test_vsseg2_nxv1i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1i32( %val, %val, i32* %base, i64 %vl) @@ -481,10 +481,10 @@ define void @test_vsseg2_mask_nxv1i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1i32( %val, %val, i32* %base, %mask, i64 %vl) @@ -497,11 +497,11 @@ define void @test_vsseg3_nxv1i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1i32( %val, %val, %val, i32* %base, i64 %vl) @@ -511,11 +511,11 @@ define void @test_vsseg3_mask_nxv1i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1i32( %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -528,12 +528,12 @@ define void @test_vsseg4_nxv1i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1i32( %val, %val, %val, %val, i32* %base, i64 %vl) @@ -543,12 +543,12 @@ define void @test_vsseg4_mask_nxv1i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1i32( %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -561,13 +561,13 @@ define void @test_vsseg5_nxv1i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0) +; CHECK-NEXT: vsseg5e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1i32( %val, %val, %val, %val, %val, i32* %base, i64 %vl) @@ -577,13 +577,13 @@ define void @test_vsseg5_mask_nxv1i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1i32( %val, %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -596,14 +596,14 @@ define void @test_vsseg6_nxv1i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0) +; CHECK-NEXT: vsseg6e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1i32( %val, %val, %val, %val, %val, %val, i32* %base, i64 %vl) @@ -613,14 +613,14 @@ define void @test_vsseg6_mask_nxv1i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1i32( %val, %val, %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -633,15 +633,15 @@ define void @test_vsseg7_nxv1i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0) +; CHECK-NEXT: vsseg7e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %vl) @@ -651,15 +651,15 @@ define void @test_vsseg7_mask_nxv1i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -672,16 +672,16 @@ define void @test_vsseg8_nxv1i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0) +; CHECK-NEXT: vsseg8e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %vl) @@ -691,16 +691,16 @@ define void @test_vsseg8_mask_nxv1i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -713,10 +713,10 @@ define void @test_vsseg2_nxv8i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8i16( %val, %val, i16* %base, i64 %vl) @@ -726,10 +726,10 @@ define void @test_vsseg2_mask_nxv8i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8i16( %val, %val, i16* %base, %mask, i64 %vl) @@ -742,11 +742,11 @@ define void @test_vsseg3_nxv8i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv8i16( %val, %val, %val, i16* %base, i64 %vl) @@ -756,11 +756,11 @@ define void @test_vsseg3_mask_nxv8i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv8i16( %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -773,12 +773,12 @@ define void @test_vsseg4_nxv8i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv8i16( %val, %val, %val, %val, i16* %base, i64 %vl) @@ -788,12 +788,12 @@ define void @test_vsseg4_mask_nxv8i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv8i16( %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -806,10 +806,10 @@ define void @test_vsseg2_nxv4i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4i8( %val, %val, i8* %base, i64 %vl) @@ -819,10 +819,10 @@ define void @test_vsseg2_mask_nxv4i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4i8( %val, %val, i8* %base, %mask, i64 %vl) @@ -835,11 +835,11 @@ define void @test_vsseg3_nxv4i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4i8( %val, %val, %val, i8* %base, i64 %vl) @@ -849,11 +849,11 @@ define void @test_vsseg3_mask_nxv4i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4i8( %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -866,12 +866,12 @@ define void @test_vsseg4_nxv4i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4i8( %val, %val, %val, %val, i8* %base, i64 %vl) @@ -881,12 +881,12 @@ define void @test_vsseg4_mask_nxv4i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4i8( %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -899,13 +899,13 @@ define void @test_vsseg5_nxv4i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0) +; CHECK-NEXT: vsseg5e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv4i8( %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -915,13 +915,13 @@ define void @test_vsseg5_mask_nxv4i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv4i8( %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -934,14 +934,14 @@ define void @test_vsseg6_nxv4i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0) +; CHECK-NEXT: vsseg6e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv4i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -951,14 +951,14 @@ define void @test_vsseg6_mask_nxv4i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv4i8( %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -971,15 +971,15 @@ define void @test_vsseg7_nxv4i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0) +; CHECK-NEXT: vsseg7e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv4i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -989,15 +989,15 @@ define void @test_vsseg7_mask_nxv4i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv4i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -1010,16 +1010,16 @@ define void @test_vsseg8_nxv4i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0) +; CHECK-NEXT: vsseg8e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv4i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -1029,16 +1029,16 @@ define void @test_vsseg8_mask_nxv4i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv4i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -1051,10 +1051,10 @@ define void @test_vsseg2_nxv1i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1i16( %val, %val, i16* %base, i64 %vl) @@ -1064,10 +1064,10 @@ define void @test_vsseg2_mask_nxv1i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1i16( %val, %val, i16* %base, %mask, i64 %vl) @@ -1080,11 +1080,11 @@ define void @test_vsseg3_nxv1i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1i16( %val, %val, %val, i16* %base, i64 %vl) @@ -1094,11 +1094,11 @@ define void @test_vsseg3_mask_nxv1i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1i16( %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1111,12 +1111,12 @@ define void @test_vsseg4_nxv1i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1i16( %val, %val, %val, %val, i16* %base, i64 %vl) @@ -1126,12 +1126,12 @@ define void @test_vsseg4_mask_nxv1i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1i16( %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1144,13 +1144,13 @@ define void @test_vsseg5_nxv1i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1i16( %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -1160,13 +1160,13 @@ define void @test_vsseg5_mask_nxv1i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1i16( %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1179,14 +1179,14 @@ define void @test_vsseg6_nxv1i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1i16( %val, %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -1196,14 +1196,14 @@ define void @test_vsseg6_mask_nxv1i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1i16( %val, %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1216,15 +1216,15 @@ define void @test_vsseg7_nxv1i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -1234,15 +1234,15 @@ define void @test_vsseg7_mask_nxv1i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1255,16 +1255,16 @@ define void @test_vsseg8_nxv1i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -1274,16 +1274,16 @@ define void @test_vsseg8_mask_nxv1i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1296,10 +1296,10 @@ define void @test_vsseg2_nxv2i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2i32( %val, %val, i32* %base, i64 %vl) @@ -1309,10 +1309,10 @@ define void @test_vsseg2_mask_nxv2i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2i32( %val, %val, i32* %base, %mask, i64 %vl) @@ -1325,11 +1325,11 @@ define void @test_vsseg3_nxv2i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2i32( %val, %val, %val, i32* %base, i64 %vl) @@ -1339,11 +1339,11 @@ define void @test_vsseg3_mask_nxv2i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2i32( %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -1356,12 +1356,12 @@ define void @test_vsseg4_nxv2i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2i32( %val, %val, %val, %val, i32* %base, i64 %vl) @@ -1371,12 +1371,12 @@ define void @test_vsseg4_mask_nxv2i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2i32( %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -1389,13 +1389,13 @@ define void @test_vsseg5_nxv2i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0) +; CHECK-NEXT: vsseg5e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2i32( %val, %val, %val, %val, %val, i32* %base, i64 %vl) @@ -1405,13 +1405,13 @@ define void @test_vsseg5_mask_nxv2i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2i32( %val, %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -1424,14 +1424,14 @@ define void @test_vsseg6_nxv2i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0) +; CHECK-NEXT: vsseg6e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2i32( %val, %val, %val, %val, %val, %val, i32* %base, i64 %vl) @@ -1441,14 +1441,14 @@ define void @test_vsseg6_mask_nxv2i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2i32( %val, %val, %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -1461,15 +1461,15 @@ define void @test_vsseg7_nxv2i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0) +; CHECK-NEXT: vsseg7e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %vl) @@ -1479,15 +1479,15 @@ define void @test_vsseg7_mask_nxv2i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -1500,16 +1500,16 @@ define void @test_vsseg8_nxv2i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0) +; CHECK-NEXT: vsseg8e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %vl) @@ -1519,16 +1519,16 @@ define void @test_vsseg8_mask_nxv2i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, %mask, i64 %vl) @@ -1541,10 +1541,10 @@ define void @test_vsseg2_nxv8i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8i8( %val, %val, i8* %base, i64 %vl) @@ -1554,10 +1554,10 @@ define void @test_vsseg2_mask_nxv8i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8i8( %val, %val, i8* %base, %mask, i64 %vl) @@ -1570,11 +1570,11 @@ define void @test_vsseg3_nxv8i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv8i8( %val, %val, %val, i8* %base, i64 %vl) @@ -1584,11 +1584,11 @@ define void @test_vsseg3_mask_nxv8i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv8i8( %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -1601,12 +1601,12 @@ define void @test_vsseg4_nxv8i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv8i8( %val, %val, %val, %val, i8* %base, i64 %vl) @@ -1616,12 +1616,12 @@ define void @test_vsseg4_mask_nxv8i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv8i8( %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -1634,13 +1634,13 @@ define void @test_vsseg5_nxv8i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0) +; CHECK-NEXT: vsseg5e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv8i8( %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -1650,13 +1650,13 @@ define void @test_vsseg5_mask_nxv8i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv8i8( %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -1669,14 +1669,14 @@ define void @test_vsseg6_nxv8i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0) +; CHECK-NEXT: vsseg6e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv8i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -1686,14 +1686,14 @@ define void @test_vsseg6_mask_nxv8i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv8i8( %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -1706,15 +1706,15 @@ define void @test_vsseg7_nxv8i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0) +; CHECK-NEXT: vsseg7e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv8i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -1724,15 +1724,15 @@ define void @test_vsseg7_mask_nxv8i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv8i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -1745,16 +1745,16 @@ define void @test_vsseg8_nxv8i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0) +; CHECK-NEXT: vsseg8e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv8i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -1764,16 +1764,16 @@ define void @test_vsseg8_mask_nxv8i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv8i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -1786,10 +1786,10 @@ define void @test_vsseg2_nxv4i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0) +; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4i64( %val, %val, i64* %base, i64 %vl) @@ -1799,10 +1799,10 @@ define void @test_vsseg2_mask_nxv4i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4i64( %val, %val, i64* %base, %mask, i64 %vl) @@ -1815,10 +1815,10 @@ define void @test_vsseg2_nxv4i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4i16( %val, %val, i16* %base, i64 %vl) @@ -1828,10 +1828,10 @@ define void @test_vsseg2_mask_nxv4i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4i16( %val, %val, i16* %base, %mask, i64 %vl) @@ -1844,11 +1844,11 @@ define void @test_vsseg3_nxv4i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4i16( %val, %val, %val, i16* %base, i64 %vl) @@ -1858,11 +1858,11 @@ define void @test_vsseg3_mask_nxv4i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4i16( %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1875,12 +1875,12 @@ define void @test_vsseg4_nxv4i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4i16( %val, %val, %val, %val, i16* %base, i64 %vl) @@ -1890,12 +1890,12 @@ define void @test_vsseg4_mask_nxv4i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4i16( %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1908,13 +1908,13 @@ define void @test_vsseg5_nxv4i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv4i16( %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -1924,13 +1924,13 @@ define void @test_vsseg5_mask_nxv4i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv4i16( %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1943,14 +1943,14 @@ define void @test_vsseg6_nxv4i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv4i16( %val, %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -1960,14 +1960,14 @@ define void @test_vsseg6_mask_nxv4i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv4i16( %val, %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -1980,15 +1980,15 @@ define void @test_vsseg7_nxv4i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv4i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -1998,15 +1998,15 @@ define void @test_vsseg7_mask_nxv4i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv4i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -2019,16 +2019,16 @@ define void @test_vsseg8_nxv4i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv4i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -2038,16 +2038,16 @@ define void @test_vsseg8_mask_nxv4i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv4i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -2060,10 +2060,10 @@ define void @test_vsseg2_nxv1i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1i8( %val, %val, i8* %base, i64 %vl) @@ -2073,10 +2073,10 @@ define void @test_vsseg2_mask_nxv1i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1i8( %val, %val, i8* %base, %mask, i64 %vl) @@ -2089,11 +2089,11 @@ define void @test_vsseg3_nxv1i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1i8( %val, %val, %val, i8* %base, i64 %vl) @@ -2103,11 +2103,11 @@ define void @test_vsseg3_mask_nxv1i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1i8( %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2120,12 +2120,12 @@ define void @test_vsseg4_nxv1i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1i8( %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2135,12 +2135,12 @@ define void @test_vsseg4_mask_nxv1i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1i8( %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2153,13 +2153,13 @@ define void @test_vsseg5_nxv1i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0) +; CHECK-NEXT: vsseg5e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1i8( %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2169,13 +2169,13 @@ define void @test_vsseg5_mask_nxv1i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1i8( %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2188,14 +2188,14 @@ define void @test_vsseg6_nxv1i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0) +; CHECK-NEXT: vsseg6e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2205,14 +2205,14 @@ define void @test_vsseg6_mask_nxv1i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1i8( %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2225,15 +2225,15 @@ define void @test_vsseg7_nxv1i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0) +; CHECK-NEXT: vsseg7e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2243,15 +2243,15 @@ define void @test_vsseg7_mask_nxv1i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2264,16 +2264,16 @@ define void @test_vsseg8_nxv1i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0) +; CHECK-NEXT: vsseg8e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2283,16 +2283,16 @@ define void @test_vsseg8_mask_nxv1i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2305,10 +2305,10 @@ define void @test_vsseg2_nxv2i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2i8( %val, %val, i8* %base, i64 %vl) @@ -2318,10 +2318,10 @@ define void @test_vsseg2_mask_nxv2i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2i8( %val, %val, i8* %base, %mask, i64 %vl) @@ -2334,11 +2334,11 @@ define void @test_vsseg3_nxv2i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0) +; CHECK-NEXT: vsseg3e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2i8( %val, %val, %val, i8* %base, i64 %vl) @@ -2348,11 +2348,11 @@ define void @test_vsseg3_mask_nxv2i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg3e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2i8( %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2365,12 +2365,12 @@ define void @test_vsseg4_nxv2i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0) +; CHECK-NEXT: vsseg4e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2i8( %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2380,12 +2380,12 @@ define void @test_vsseg4_mask_nxv2i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg4e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2i8( %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2398,13 +2398,13 @@ define void @test_vsseg5_nxv2i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0) +; CHECK-NEXT: vsseg5e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2i8( %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2414,13 +2414,13 @@ define void @test_vsseg5_mask_nxv2i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg5e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2i8( %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2433,14 +2433,14 @@ define void @test_vsseg6_nxv2i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0) +; CHECK-NEXT: vsseg6e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2450,14 +2450,14 @@ define void @test_vsseg6_mask_nxv2i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg6e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2i8( %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2470,15 +2470,15 @@ define void @test_vsseg7_nxv2i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0) +; CHECK-NEXT: vsseg7e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2488,15 +2488,15 @@ define void @test_vsseg7_mask_nxv2i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg7e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2509,16 +2509,16 @@ define void @test_vsseg8_nxv2i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0) +; CHECK-NEXT: vsseg8e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %vl) @@ -2528,16 +2528,16 @@ define void @test_vsseg8_mask_nxv2i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsseg8e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, %mask, i64 %vl) @@ -2550,10 +2550,10 @@ define void @test_vsseg2_nxv8i32( %val, i32* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8i32( %val, %val, i32* %base, i64 %vl) @@ -2563,10 +2563,10 @@ define void @test_vsseg2_mask_nxv8i32( %val, i32* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8i32( %val, %val, i32* %base, %mask, i64 %vl) @@ -2579,10 +2579,10 @@ define void @test_vsseg2_nxv32i8( %val, i8* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0) +; CHECK-NEXT: vsseg2e8.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv32i8( %val, %val, i8* %base, i64 %vl) @@ -2592,10 +2592,10 @@ define void @test_vsseg2_mask_nxv32i8( %val, i8* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsseg2e8.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e8.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv32i8( %val, %val, i8* %base, %mask, i64 %vl) @@ -2608,10 +2608,10 @@ define void @test_vsseg2_nxv2i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2i16( %val, %val, i16* %base, i64 %vl) @@ -2621,10 +2621,10 @@ define void @test_vsseg2_mask_nxv2i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2i16( %val, %val, i16* %base, %mask, i64 %vl) @@ -2637,11 +2637,11 @@ define void @test_vsseg3_nxv2i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2i16( %val, %val, %val, i16* %base, i64 %vl) @@ -2651,11 +2651,11 @@ define void @test_vsseg3_mask_nxv2i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2i16( %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -2668,12 +2668,12 @@ define void @test_vsseg4_nxv2i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2i16( %val, %val, %val, %val, i16* %base, i64 %vl) @@ -2683,12 +2683,12 @@ define void @test_vsseg4_mask_nxv2i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2i16( %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -2701,13 +2701,13 @@ define void @test_vsseg5_nxv2i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2i16( %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -2717,13 +2717,13 @@ define void @test_vsseg5_mask_nxv2i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2i16( %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -2736,14 +2736,14 @@ define void @test_vsseg6_nxv2i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2i16( %val, %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -2753,14 +2753,14 @@ define void @test_vsseg6_mask_nxv2i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2i16( %val, %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -2773,15 +2773,15 @@ define void @test_vsseg7_nxv2i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -2791,15 +2791,15 @@ define void @test_vsseg7_mask_nxv2i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -2812,16 +2812,16 @@ define void @test_vsseg8_nxv2i16( %val, i16* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %vl) @@ -2831,16 +2831,16 @@ define void @test_vsseg8_mask_nxv2i16( %val, i16* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, %mask, i64 %vl) @@ -2853,10 +2853,10 @@ define void @test_vsseg2_nxv2i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0) +; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2i64( %val, %val, i64* %base, i64 %vl) @@ -2866,10 +2866,10 @@ define void @test_vsseg2_mask_nxv2i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2i64( %val, %val, i64* %base, %mask, i64 %vl) @@ -2882,11 +2882,11 @@ define void @test_vsseg3_nxv2i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0) +; CHECK-NEXT: vsseg3e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2i64( %val, %val, %val, i64* %base, i64 %vl) @@ -2896,11 +2896,11 @@ define void @test_vsseg3_mask_nxv2i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2i64( %val, %val, %val, i64* %base, %mask, i64 %vl) @@ -2913,12 +2913,12 @@ define void @test_vsseg4_nxv2i64( %val, i64* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0) +; CHECK-NEXT: vsseg4e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2i64( %val, %val, %val, %val, i64* %base, i64 %vl) @@ -2928,12 +2928,12 @@ define void @test_vsseg4_mask_nxv2i64( %val, i64* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2i64( %val, %val, %val, %val, i64* %base, %mask, i64 %vl) @@ -2946,10 +2946,10 @@ define void @test_vsseg2_nxv16f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv16f16( %val, %val, half* %base, i64 %vl) @@ -2959,10 +2959,10 @@ define void @test_vsseg2_mask_nxv16f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv16f16( %val, %val, half* %base, %mask, i64 %vl) @@ -2975,10 +2975,10 @@ define void @test_vsseg2_nxv4f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0) +; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4f64( %val, %val, double* %base, i64 %vl) @@ -2988,10 +2988,10 @@ define void @test_vsseg2_mask_nxv4f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4f64( %val, %val, double* %base, %mask, i64 %vl) @@ -3004,10 +3004,10 @@ define void @test_vsseg2_nxv1f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0) +; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1f64( %val, %val, double* %base, i64 %vl) @@ -3017,10 +3017,10 @@ define void @test_vsseg2_mask_nxv1f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1f64( %val, %val, double* %base, %mask, i64 %vl) @@ -3033,11 +3033,11 @@ define void @test_vsseg3_nxv1f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0) +; CHECK-NEXT: vsseg3e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1f64( %val, %val, %val, double* %base, i64 %vl) @@ -3047,11 +3047,11 @@ define void @test_vsseg3_mask_nxv1f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1f64( %val, %val, %val, double* %base, %mask, i64 %vl) @@ -3064,12 +3064,12 @@ define void @test_vsseg4_nxv1f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0) +; CHECK-NEXT: vsseg4e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1f64( %val, %val, %val, %val, double* %base, i64 %vl) @@ -3079,12 +3079,12 @@ define void @test_vsseg4_mask_nxv1f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1f64( %val, %val, %val, %val, double* %base, %mask, i64 %vl) @@ -3097,13 +3097,13 @@ define void @test_vsseg5_nxv1f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg5e64.v v16, (a0) +; CHECK-NEXT: vsseg5e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1f64( %val, %val, %val, %val, %val, double* %base, i64 %vl) @@ -3113,13 +3113,13 @@ define void @test_vsseg5_mask_nxv1f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg5e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1f64( %val, %val, %val, %val, %val, double* %base, %mask, i64 %vl) @@ -3132,14 +3132,14 @@ define void @test_vsseg6_nxv1f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg6e64.v v16, (a0) +; CHECK-NEXT: vsseg6e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1f64( %val, %val, %val, %val, %val, %val, double* %base, i64 %vl) @@ -3149,14 +3149,14 @@ define void @test_vsseg6_mask_nxv1f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg6e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1f64( %val, %val, %val, %val, %val, %val, double* %base, %mask, i64 %vl) @@ -3169,15 +3169,15 @@ define void @test_vsseg7_nxv1f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg7e64.v v16, (a0) +; CHECK-NEXT: vsseg7e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1f64( %val, %val, %val, %val, %val, %val, %val, double* %base, i64 %vl) @@ -3187,15 +3187,15 @@ define void @test_vsseg7_mask_nxv1f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg7e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1f64( %val, %val, %val, %val, %val, %val, %val, double* %base, %mask, i64 %vl) @@ -3208,16 +3208,16 @@ define void @test_vsseg8_nxv1f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg8e64.v v16, (a0) +; CHECK-NEXT: vsseg8e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1f64( %val, %val, %val, %val, %val, %val, %val, %val, double* %base, i64 %vl) @@ -3227,16 +3227,16 @@ define void @test_vsseg8_mask_nxv1f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsseg8e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1f64( %val, %val, %val, %val, %val, %val, %val, %val, double* %base, %mask, i64 %vl) @@ -3249,10 +3249,10 @@ define void @test_vsseg2_nxv2f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2f32( %val, %val, float* %base, i64 %vl) @@ -3262,10 +3262,10 @@ define void @test_vsseg2_mask_nxv2f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2f32( %val, %val, float* %base, %mask, i64 %vl) @@ -3278,11 +3278,11 @@ define void @test_vsseg3_nxv2f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2f32( %val, %val, %val, float* %base, i64 %vl) @@ -3292,11 +3292,11 @@ define void @test_vsseg3_mask_nxv2f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2f32( %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3309,12 +3309,12 @@ define void @test_vsseg4_nxv2f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2f32( %val, %val, %val, %val, float* %base, i64 %vl) @@ -3324,12 +3324,12 @@ define void @test_vsseg4_mask_nxv2f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2f32( %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3342,13 +3342,13 @@ define void @test_vsseg5_nxv2f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0) +; CHECK-NEXT: vsseg5e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2f32( %val, %val, %val, %val, %val, float* %base, i64 %vl) @@ -3358,13 +3358,13 @@ define void @test_vsseg5_mask_nxv2f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2f32( %val, %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3377,14 +3377,14 @@ define void @test_vsseg6_nxv2f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0) +; CHECK-NEXT: vsseg6e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2f32( %val, %val, %val, %val, %val, %val, float* %base, i64 %vl) @@ -3394,14 +3394,14 @@ define void @test_vsseg6_mask_nxv2f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2f32( %val, %val, %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3414,15 +3414,15 @@ define void @test_vsseg7_nxv2f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0) +; CHECK-NEXT: vsseg7e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %vl) @@ -3432,15 +3432,15 @@ define void @test_vsseg7_mask_nxv2f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2f32( %val, %val, %val, %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3453,16 +3453,16 @@ define void @test_vsseg8_nxv2f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0) +; CHECK-NEXT: vsseg8e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %vl) @@ -3472,16 +3472,16 @@ define void @test_vsseg8_mask_nxv2f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3494,10 +3494,10 @@ define void @test_vsseg2_nxv1f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1f16( %val, %val, half* %base, i64 %vl) @@ -3507,10 +3507,10 @@ define void @test_vsseg2_mask_nxv1f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1f16( %val, %val, half* %base, %mask, i64 %vl) @@ -3523,11 +3523,11 @@ define void @test_vsseg3_nxv1f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1f16( %val, %val, %val, half* %base, i64 %vl) @@ -3537,11 +3537,11 @@ define void @test_vsseg3_mask_nxv1f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1f16( %val, %val, %val, half* %base, %mask, i64 %vl) @@ -3554,12 +3554,12 @@ define void @test_vsseg4_nxv1f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1f16( %val, %val, %val, %val, half* %base, i64 %vl) @@ -3569,12 +3569,12 @@ define void @test_vsseg4_mask_nxv1f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1f16( %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -3587,13 +3587,13 @@ define void @test_vsseg5_nxv1f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1f16( %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -3603,13 +3603,13 @@ define void @test_vsseg5_mask_nxv1f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1f16( %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -3622,14 +3622,14 @@ define void @test_vsseg6_nxv1f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1f16( %val, %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -3639,14 +3639,14 @@ define void @test_vsseg6_mask_nxv1f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1f16( %val, %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -3659,15 +3659,15 @@ define void @test_vsseg7_nxv1f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -3677,15 +3677,15 @@ define void @test_vsseg7_mask_nxv1f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1f16( %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -3698,16 +3698,16 @@ define void @test_vsseg8_nxv1f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -3717,16 +3717,16 @@ define void @test_vsseg8_mask_nxv1f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -3739,10 +3739,10 @@ define void @test_vsseg2_nxv1f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv1f32( %val, %val, float* %base, i64 %vl) @@ -3752,10 +3752,10 @@ define void @test_vsseg2_mask_nxv1f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv1f32( %val, %val, float* %base, %mask, i64 %vl) @@ -3768,11 +3768,11 @@ define void @test_vsseg3_nxv1f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv1f32( %val, %val, %val, float* %base, i64 %vl) @@ -3782,11 +3782,11 @@ define void @test_vsseg3_mask_nxv1f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv1f32( %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3799,12 +3799,12 @@ define void @test_vsseg4_nxv1f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv1f32( %val, %val, %val, %val, float* %base, i64 %vl) @@ -3814,12 +3814,12 @@ define void @test_vsseg4_mask_nxv1f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv1f32( %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3832,13 +3832,13 @@ define void @test_vsseg5_nxv1f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0) +; CHECK-NEXT: vsseg5e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv1f32( %val, %val, %val, %val, %val, float* %base, i64 %vl) @@ -3848,13 +3848,13 @@ define void @test_vsseg5_mask_nxv1f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg5e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv1f32( %val, %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3867,14 +3867,14 @@ define void @test_vsseg6_nxv1f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0) +; CHECK-NEXT: vsseg6e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv1f32( %val, %val, %val, %val, %val, %val, float* %base, i64 %vl) @@ -3884,14 +3884,14 @@ define void @test_vsseg6_mask_nxv1f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg6e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv1f32( %val, %val, %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3904,15 +3904,15 @@ define void @test_vsseg7_nxv1f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0) +; CHECK-NEXT: vsseg7e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv1f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %vl) @@ -3922,15 +3922,15 @@ define void @test_vsseg7_mask_nxv1f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg7e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv1f32( %val, %val, %val, %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3943,16 +3943,16 @@ define void @test_vsseg8_nxv1f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0) +; CHECK-NEXT: vsseg8e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv1f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %vl) @@ -3962,16 +3962,16 @@ define void @test_vsseg8_mask_nxv1f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsseg8e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv1f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, %mask, i64 %vl) @@ -3984,10 +3984,10 @@ define void @test_vsseg2_nxv8f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8f16( %val, %val, half* %base, i64 %vl) @@ -3997,10 +3997,10 @@ define void @test_vsseg2_mask_nxv8f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8f16( %val, %val, half* %base, %mask, i64 %vl) @@ -4013,11 +4013,11 @@ define void @test_vsseg3_nxv8f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv8f16( %val, %val, %val, half* %base, i64 %vl) @@ -4027,11 +4027,11 @@ define void @test_vsseg3_mask_nxv8f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv8f16( %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4044,12 +4044,12 @@ define void @test_vsseg4_nxv8f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv8f16( %val, %val, %val, %val, half* %base, i64 %vl) @@ -4059,12 +4059,12 @@ define void @test_vsseg4_mask_nxv8f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv8f16( %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4077,10 +4077,10 @@ define void @test_vsseg2_nxv8f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv8f32( %val, %val, float* %base, i64 %vl) @@ -4090,10 +4090,10 @@ define void @test_vsseg2_mask_nxv8f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv8f32( %val, %val, float* %base, %mask, i64 %vl) @@ -4106,10 +4106,10 @@ define void @test_vsseg2_nxv2f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0) +; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2f64( %val, %val, double* %base, i64 %vl) @@ -4119,10 +4119,10 @@ define void @test_vsseg2_mask_nxv2f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg2e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2f64( %val, %val, double* %base, %mask, i64 %vl) @@ -4135,11 +4135,11 @@ define void @test_vsseg3_nxv2f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0) +; CHECK-NEXT: vsseg3e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2f64( %val, %val, %val, double* %base, i64 %vl) @@ -4149,11 +4149,11 @@ define void @test_vsseg3_mask_nxv2f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg3e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2f64( %val, %val, %val, double* %base, %mask, i64 %vl) @@ -4166,12 +4166,12 @@ define void @test_vsseg4_nxv2f64( %val, double* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0) +; CHECK-NEXT: vsseg4e64.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2f64( %val, %val, %val, %val, double* %base, i64 %vl) @@ -4181,12 +4181,12 @@ define void @test_vsseg4_mask_nxv2f64( %val, double* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsseg4e64.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e64.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2f64( %val, %val, %val, %val, double* %base, %mask, i64 %vl) @@ -4199,10 +4199,10 @@ define void @test_vsseg2_nxv4f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4f16( %val, %val, half* %base, i64 %vl) @@ -4212,10 +4212,10 @@ define void @test_vsseg2_mask_nxv4f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4f16( %val, %val, half* %base, %mask, i64 %vl) @@ -4228,11 +4228,11 @@ define void @test_vsseg3_nxv4f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4f16( %val, %val, %val, half* %base, i64 %vl) @@ -4242,11 +4242,11 @@ define void @test_vsseg3_mask_nxv4f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4f16( %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4259,12 +4259,12 @@ define void @test_vsseg4_nxv4f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4f16( %val, %val, %val, %val, half* %base, i64 %vl) @@ -4274,12 +4274,12 @@ define void @test_vsseg4_mask_nxv4f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4f16( %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4292,13 +4292,13 @@ define void @test_vsseg5_nxv4f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv4f16( %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -4308,13 +4308,13 @@ define void @test_vsseg5_mask_nxv4f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv4f16( %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4327,14 +4327,14 @@ define void @test_vsseg6_nxv4f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv4f16( %val, %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -4344,14 +4344,14 @@ define void @test_vsseg6_mask_nxv4f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv4f16( %val, %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4364,15 +4364,15 @@ define void @test_vsseg7_nxv4f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv4f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -4382,15 +4382,15 @@ define void @test_vsseg7_mask_nxv4f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv4f16( %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4403,16 +4403,16 @@ define void @test_vsseg8_nxv4f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv4f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -4422,16 +4422,16 @@ define void @test_vsseg8_mask_nxv4f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv4f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4444,10 +4444,10 @@ define void @test_vsseg2_nxv2f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0) +; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv2f16( %val, %val, half* %base, i64 %vl) @@ -4457,10 +4457,10 @@ define void @test_vsseg2_mask_nxv2f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg2e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv2f16( %val, %val, half* %base, %mask, i64 %vl) @@ -4473,11 +4473,11 @@ define void @test_vsseg3_nxv2f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0) +; CHECK-NEXT: vsseg3e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv2f16( %val, %val, %val, half* %base, i64 %vl) @@ -4487,11 +4487,11 @@ define void @test_vsseg3_mask_nxv2f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg3e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv2f16( %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4504,12 +4504,12 @@ define void @test_vsseg4_nxv2f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0) +; CHECK-NEXT: vsseg4e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv2f16( %val, %val, %val, %val, half* %base, i64 %vl) @@ -4519,12 +4519,12 @@ define void @test_vsseg4_mask_nxv2f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg4e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv2f16( %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4537,13 +4537,13 @@ define void @test_vsseg5_nxv2f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg5_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0) +; CHECK-NEXT: vsseg5e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.nxv2f16( %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -4553,13 +4553,13 @@ define void @test_vsseg5_mask_nxv2f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg5_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg5e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg5e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg5.mask.nxv2f16( %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4572,14 +4572,14 @@ define void @test_vsseg6_nxv2f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg6_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0) +; CHECK-NEXT: vsseg6e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.nxv2f16( %val, %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -4589,14 +4589,14 @@ define void @test_vsseg6_mask_nxv2f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg6_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg6e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg6e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg6.mask.nxv2f16( %val, %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4609,15 +4609,15 @@ define void @test_vsseg7_nxv2f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg7_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0) +; CHECK-NEXT: vsseg7e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.nxv2f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -4627,15 +4627,15 @@ define void @test_vsseg7_mask_nxv2f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg7_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg7e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg7e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg7.mask.nxv2f16( %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4648,16 +4648,16 @@ define void @test_vsseg8_nxv2f16( %val, half* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg8_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0) +; CHECK-NEXT: vsseg8e16.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.nxv2f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %vl) @@ -4667,16 +4667,16 @@ define void @test_vsseg8_mask_nxv2f16( %val, half* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg8_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsseg8e16.v v16, (a0), v0.t +; CHECK-NEXT: vsseg8e16.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg8.mask.nxv2f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, %mask, i64 %vl) @@ -4689,10 +4689,10 @@ define void @test_vsseg2_nxv4f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg2_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0) +; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.nxv4f32( %val, %val, float* %base, i64 %vl) @@ -4702,10 +4702,10 @@ define void @test_vsseg2_mask_nxv4f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg2_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg2e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg2e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg2.mask.nxv4f32( %val, %val, float* %base, %mask, i64 %vl) @@ -4718,11 +4718,11 @@ define void @test_vsseg3_nxv4f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg3_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0) +; CHECK-NEXT: vsseg3e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.nxv4f32( %val, %val, %val, float* %base, i64 %vl) @@ -4732,11 +4732,11 @@ define void @test_vsseg3_mask_nxv4f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg3_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg3e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg3e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg3.mask.nxv4f32( %val, %val, %val, float* %base, %mask, i64 %vl) @@ -4749,12 +4749,12 @@ define void @test_vsseg4_nxv4f32( %val, float* %base, i64 %vl) { ; CHECK-LABEL: test_vsseg4_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0) +; CHECK-NEXT: vsseg4e32.v v8, (a0) ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.nxv4f32( %val, %val, %val, %val, float* %base, i64 %vl) @@ -4764,12 +4764,12 @@ define void @test_vsseg4_mask_nxv4f32( %val, float* %base, %mask, i64 %vl) { ; CHECK-LABEL: test_vsseg4_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsseg4e32.v v16, (a0), v0.t +; CHECK-NEXT: vsseg4e32.v v8, (a0), v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vsseg4.mask.nxv4f32( %val, %val, %val, %val, float* %base, %mask, i64 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vssra.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vssra_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vssra_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vssra_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vssra_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vssra_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vssra_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vssra_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vssra_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vssra_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vssra_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vssra_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vssra_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vssra_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vssra_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vssra_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vssra_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vssra_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vssra_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vssra_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vssra_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vssra_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vssra_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vssra_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vssra_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vssra_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vssra_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vssra_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vssra_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vssra_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vssra_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vssra_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vssra_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vssra_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vssra_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vssra_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vssra_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vssra_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vssra_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vssra_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vssra_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vssra_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vssra_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vssra_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vssra_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vssra_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vssra_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vssra_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vssra_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vssra_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vssra_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vssra_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vssra_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vssra_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vssra_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vssra.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vssra_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vssra_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vssra_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vssra_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vssra_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vssra_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vssra_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vssra_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vssra_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vssra_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vssra_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vssra_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vssra_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vssra_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vssra_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vssra_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vssra_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vssra_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssra.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vssra_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssra.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vssra_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vssra_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssra.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vssra_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssra.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vssra.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssra.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vssra_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vssra_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vssra_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vssra_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vssra_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vssra_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vssra_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vssra_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vssra_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vssra_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vssra_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vssra_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vssra_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vssra_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vssra_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vssra_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vssra_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vssra_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vssra_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vssra.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vssra_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vssra.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vssra_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vssra.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vssra_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssra_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vssra.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssra.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vssra_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vssra.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssra.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vssra_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vssra_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vssra_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vssra_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vssra_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vssra_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vssra_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vssra_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vssra_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vssra_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vssra_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vssra_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vssra_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vssra_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vssra_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vssra_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vssra_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vssra_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vssra_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssra.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vssra_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssra.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vssra_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssra.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vssra_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssra_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssra.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssra.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vssra.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssra_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssra.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssra.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vssrl.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vssrl_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vssrl_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vssrl_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vssrl_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vssrl_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vssrl_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vssrl_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vssrl_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vssrl_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vssrl_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vssrl_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vssrl_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vssrl_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vssrl_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vssrl_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vssrl_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vssrl_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vssrl_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vssrl.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vssrl_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vssrl_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vssrl_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vssrl_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vssrl_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vssrl_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vssrl_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vssrl_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vssrl_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vssrl_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vssrl_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vssrl_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vssrl_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vssrl_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vssrl_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vssrl_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vssrl_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vssrl_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vssrl_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssrl.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vssrl_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vssrl_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssrl.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vssrl_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssrl.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vssrl.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssrl.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vssrl_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vssrl.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vssrl_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vssrl.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vssrl_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vssrl.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vssrl_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vssrl.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssrl.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vssrl.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssrl.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssrl.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssrl.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssrl.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssrl.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vssrl.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vssrl.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssrl_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssrl.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vssrl.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll @@ -8,10 +8,10 @@ define void @test_vssseg2_nxv16i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv16i16( %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -21,10 +21,10 @@ define void @test_vssseg2_mask_nxv16i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv16i16( %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -37,10 +37,10 @@ define void @test_vssseg2_nxv1i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1i8( %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -50,10 +50,10 @@ define void @test_vssseg2_mask_nxv1i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1i8( %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -66,11 +66,11 @@ define void @test_vssseg3_nxv1i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1i8( %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -80,11 +80,11 @@ define void @test_vssseg3_mask_nxv1i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1i8( %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -97,12 +97,12 @@ define void @test_vssseg4_nxv1i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1i8( %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -112,12 +112,12 @@ define void @test_vssseg4_mask_nxv1i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1i8( %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -130,13 +130,13 @@ define void @test_vssseg5_nxv1i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1i8( %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -146,13 +146,13 @@ define void @test_vssseg5_mask_nxv1i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1i8( %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -165,14 +165,14 @@ define void @test_vssseg6_nxv1i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -182,14 +182,14 @@ define void @test_vssseg6_mask_nxv1i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -202,15 +202,15 @@ define void @test_vssseg7_nxv1i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -220,15 +220,15 @@ define void @test_vssseg7_mask_nxv1i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -241,16 +241,16 @@ define void @test_vssseg8_nxv1i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -260,16 +260,16 @@ define void @test_vssseg8_mask_nxv1i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -282,10 +282,10 @@ define void @test_vssseg2_nxv16i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv16i8( %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -295,10 +295,10 @@ define void @test_vssseg2_mask_nxv16i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv16i8( %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -311,11 +311,11 @@ define void @test_vssseg3_nxv16i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv16i8( %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -325,11 +325,11 @@ define void @test_vssseg3_mask_nxv16i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv16i8( %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -342,12 +342,12 @@ define void @test_vssseg4_nxv16i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv16i8( %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -357,12 +357,12 @@ define void @test_vssseg4_mask_nxv16i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv16i8( %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -375,10 +375,10 @@ define void @test_vssseg2_nxv2i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2i32( %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -388,10 +388,10 @@ define void @test_vssseg2_mask_nxv2i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2i32( %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -404,11 +404,11 @@ define void @test_vssseg3_nxv2i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2i32( %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -418,11 +418,11 @@ define void @test_vssseg3_mask_nxv2i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2i32( %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -435,12 +435,12 @@ define void @test_vssseg4_nxv2i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2i32( %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -450,12 +450,12 @@ define void @test_vssseg4_mask_nxv2i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2i32( %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -468,13 +468,13 @@ define void @test_vssseg5_nxv2i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2i32( %val, %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -484,13 +484,13 @@ define void @test_vssseg5_mask_nxv2i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2i32( %val, %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -503,14 +503,14 @@ define void @test_vssseg6_nxv2i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2i32( %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -520,14 +520,14 @@ define void @test_vssseg6_mask_nxv2i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2i32( %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -540,15 +540,15 @@ define void @test_vssseg7_nxv2i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -558,15 +558,15 @@ define void @test_vssseg7_mask_nxv2i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -579,16 +579,16 @@ define void @test_vssseg8_nxv2i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -598,16 +598,16 @@ define void @test_vssseg8_mask_nxv2i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -620,10 +620,10 @@ define void @test_vssseg2_nxv4i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4i16( %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -633,10 +633,10 @@ define void @test_vssseg2_mask_nxv4i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4i16( %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -649,11 +649,11 @@ define void @test_vssseg3_nxv4i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4i16( %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -663,11 +663,11 @@ define void @test_vssseg3_mask_nxv4i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4i16( %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -680,12 +680,12 @@ define void @test_vssseg4_nxv4i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4i16( %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -695,12 +695,12 @@ define void @test_vssseg4_mask_nxv4i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4i16( %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -713,13 +713,13 @@ define void @test_vssseg5_nxv4i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv4i16( %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -729,13 +729,13 @@ define void @test_vssseg5_mask_nxv4i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv4i16( %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -748,14 +748,14 @@ define void @test_vssseg6_nxv4i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv4i16( %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -765,14 +765,14 @@ define void @test_vssseg6_mask_nxv4i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv4i16( %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -785,15 +785,15 @@ define void @test_vssseg7_nxv4i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv4i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -803,15 +803,15 @@ define void @test_vssseg7_mask_nxv4i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv4i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -824,16 +824,16 @@ define void @test_vssseg8_nxv4i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv4i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -843,16 +843,16 @@ define void @test_vssseg8_mask_nxv4i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv4i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -865,10 +865,10 @@ define void @test_vssseg2_nxv1i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1i32( %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -878,10 +878,10 @@ define void @test_vssseg2_mask_nxv1i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1i32( %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -894,11 +894,11 @@ define void @test_vssseg3_nxv1i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1i32( %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -908,11 +908,11 @@ define void @test_vssseg3_mask_nxv1i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1i32( %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -925,12 +925,12 @@ define void @test_vssseg4_nxv1i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1i32( %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -940,12 +940,12 @@ define void @test_vssseg4_mask_nxv1i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1i32( %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -958,13 +958,13 @@ define void @test_vssseg5_nxv1i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1i32( %val, %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -974,13 +974,13 @@ define void @test_vssseg5_mask_nxv1i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1i32( %val, %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -993,14 +993,14 @@ define void @test_vssseg6_nxv1i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1i32( %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -1010,14 +1010,14 @@ define void @test_vssseg6_mask_nxv1i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1i32( %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -1030,15 +1030,15 @@ define void @test_vssseg7_nxv1i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -1048,15 +1048,15 @@ define void @test_vssseg7_mask_nxv1i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -1069,16 +1069,16 @@ define void @test_vssseg8_nxv1i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -1088,16 +1088,16 @@ define void @test_vssseg8_mask_nxv1i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -1110,10 +1110,10 @@ define void @test_vssseg2_nxv8i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8i16( %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1123,10 +1123,10 @@ define void @test_vssseg2_mask_nxv8i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8i16( %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1139,11 +1139,11 @@ define void @test_vssseg3_nxv8i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv8i16( %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1153,11 +1153,11 @@ define void @test_vssseg3_mask_nxv8i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv8i16( %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1170,12 +1170,12 @@ define void @test_vssseg4_nxv8i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv8i16( %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1185,12 +1185,12 @@ define void @test_vssseg4_mask_nxv8i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv8i16( %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1203,10 +1203,10 @@ define void @test_vssseg2_nxv8i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8i8( %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1216,10 +1216,10 @@ define void @test_vssseg2_mask_nxv8i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8i8( %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1232,11 +1232,11 @@ define void @test_vssseg3_nxv8i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv8i8( %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1246,11 +1246,11 @@ define void @test_vssseg3_mask_nxv8i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv8i8( %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1263,12 +1263,12 @@ define void @test_vssseg4_nxv8i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv8i8( %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1278,12 +1278,12 @@ define void @test_vssseg4_mask_nxv8i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv8i8( %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1296,13 +1296,13 @@ define void @test_vssseg5_nxv8i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv8i8( %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1312,13 +1312,13 @@ define void @test_vssseg5_mask_nxv8i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv8i8( %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1331,14 +1331,14 @@ define void @test_vssseg6_nxv8i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv8i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1348,14 +1348,14 @@ define void @test_vssseg6_mask_nxv8i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv8i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1368,15 +1368,15 @@ define void @test_vssseg7_nxv8i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv8i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1386,15 +1386,15 @@ define void @test_vssseg7_mask_nxv8i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv8i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1407,16 +1407,16 @@ define void @test_vssseg8_nxv8i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv8i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1426,16 +1426,16 @@ define void @test_vssseg8_mask_nxv8i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv8i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1448,10 +1448,10 @@ define void @test_vssseg2_nxv8i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8i32( %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -1461,10 +1461,10 @@ define void @test_vssseg2_mask_nxv8i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8i32( %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -1477,10 +1477,10 @@ define void @test_vssseg2_nxv4i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4i8( %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1490,10 +1490,10 @@ define void @test_vssseg2_mask_nxv4i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4i8( %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1506,11 +1506,11 @@ define void @test_vssseg3_nxv4i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4i8( %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1520,11 +1520,11 @@ define void @test_vssseg3_mask_nxv4i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4i8( %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1537,12 +1537,12 @@ define void @test_vssseg4_nxv4i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4i8( %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1552,12 +1552,12 @@ define void @test_vssseg4_mask_nxv4i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4i8( %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1570,13 +1570,13 @@ define void @test_vssseg5_nxv4i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv4i8( %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1586,13 +1586,13 @@ define void @test_vssseg5_mask_nxv4i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv4i8( %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1605,14 +1605,14 @@ define void @test_vssseg6_nxv4i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv4i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1622,14 +1622,14 @@ define void @test_vssseg6_mask_nxv4i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv4i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1642,15 +1642,15 @@ define void @test_vssseg7_nxv4i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv4i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1660,15 +1660,15 @@ define void @test_vssseg7_mask_nxv4i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv4i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1681,16 +1681,16 @@ define void @test_vssseg8_nxv4i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv4i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1700,16 +1700,16 @@ define void @test_vssseg8_mask_nxv4i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv4i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1722,10 +1722,10 @@ define void @test_vssseg2_nxv1i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1i16( %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1735,10 +1735,10 @@ define void @test_vssseg2_mask_nxv1i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1i16( %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1751,11 +1751,11 @@ define void @test_vssseg3_nxv1i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1i16( %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1765,11 +1765,11 @@ define void @test_vssseg3_mask_nxv1i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1i16( %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1782,12 +1782,12 @@ define void @test_vssseg4_nxv1i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1i16( %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1797,12 +1797,12 @@ define void @test_vssseg4_mask_nxv1i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1i16( %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1815,13 +1815,13 @@ define void @test_vssseg5_nxv1i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1i16( %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1831,13 +1831,13 @@ define void @test_vssseg5_mask_nxv1i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1i16( %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1850,14 +1850,14 @@ define void @test_vssseg6_nxv1i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1i16( %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1867,14 +1867,14 @@ define void @test_vssseg6_mask_nxv1i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1i16( %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1887,15 +1887,15 @@ define void @test_vssseg7_nxv1i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1905,15 +1905,15 @@ define void @test_vssseg7_mask_nxv1i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1926,16 +1926,16 @@ define void @test_vssseg8_nxv1i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -1945,16 +1945,16 @@ define void @test_vssseg8_mask_nxv1i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -1967,10 +1967,10 @@ define void @test_vssseg2_nxv32i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv32i8( %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -1980,10 +1980,10 @@ define void @test_vssseg2_mask_nxv32i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv32i8( %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -1996,10 +1996,10 @@ define void @test_vssseg2_nxv2i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2i8( %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -2009,10 +2009,10 @@ define void @test_vssseg2_mask_nxv2i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2i8( %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -2025,11 +2025,11 @@ define void @test_vssseg3_nxv2i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2i8( %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -2039,11 +2039,11 @@ define void @test_vssseg3_mask_nxv2i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2i8( %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -2056,12 +2056,12 @@ define void @test_vssseg4_nxv2i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2i8( %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -2071,12 +2071,12 @@ define void @test_vssseg4_mask_nxv2i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2i8( %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -2089,13 +2089,13 @@ define void @test_vssseg5_nxv2i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2i8( %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -2105,13 +2105,13 @@ define void @test_vssseg5_mask_nxv2i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2i8( %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -2124,14 +2124,14 @@ define void @test_vssseg6_nxv2i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -2141,14 +2141,14 @@ define void @test_vssseg6_mask_nxv2i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2i8( %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -2161,15 +2161,15 @@ define void @test_vssseg7_nxv2i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -2179,15 +2179,15 @@ define void @test_vssseg7_mask_nxv2i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -2200,16 +2200,16 @@ define void @test_vssseg8_nxv2i8( %val, i8* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, i32 %vl) @@ -2219,16 +2219,16 @@ define void @test_vssseg8_mask_nxv2i8( %val, i8* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i32 %offset, %mask, i32 %vl) @@ -2241,10 +2241,10 @@ define void @test_vssseg2_nxv2i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2i16( %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -2254,10 +2254,10 @@ define void @test_vssseg2_mask_nxv2i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2i16( %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -2270,11 +2270,11 @@ define void @test_vssseg3_nxv2i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2i16( %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -2284,11 +2284,11 @@ define void @test_vssseg3_mask_nxv2i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2i16( %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -2301,12 +2301,12 @@ define void @test_vssseg4_nxv2i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2i16( %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -2316,12 +2316,12 @@ define void @test_vssseg4_mask_nxv2i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2i16( %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -2334,13 +2334,13 @@ define void @test_vssseg5_nxv2i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2i16( %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -2350,13 +2350,13 @@ define void @test_vssseg5_mask_nxv2i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2i16( %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -2369,14 +2369,14 @@ define void @test_vssseg6_nxv2i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2i16( %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -2386,14 +2386,14 @@ define void @test_vssseg6_mask_nxv2i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2i16( %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -2406,15 +2406,15 @@ define void @test_vssseg7_nxv2i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -2424,15 +2424,15 @@ define void @test_vssseg7_mask_nxv2i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -2445,16 +2445,16 @@ define void @test_vssseg8_nxv2i16( %val, i16* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, i32 %vl) @@ -2464,16 +2464,16 @@ define void @test_vssseg8_mask_nxv2i16( %val, i16* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i32 %offset, %mask, i32 %vl) @@ -2486,10 +2486,10 @@ define void @test_vssseg2_nxv4i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4i32( %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -2499,10 +2499,10 @@ define void @test_vssseg2_mask_nxv4i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4i32( %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -2515,11 +2515,11 @@ define void @test_vssseg3_nxv4i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4i32( %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -2529,11 +2529,11 @@ define void @test_vssseg3_mask_nxv4i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4i32( %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -2546,12 +2546,12 @@ define void @test_vssseg4_nxv4i32( %val, i32* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4i32( %val, %val, %val, %val, i32* %base, i32 %offset, i32 %vl) @@ -2561,12 +2561,12 @@ define void @test_vssseg4_mask_nxv4i32( %val, i32* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4i32( %val, %val, %val, %val, i32* %base, i32 %offset, %mask, i32 %vl) @@ -2579,10 +2579,10 @@ define void @test_vssseg2_nxv16f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv16f16( %val, %val, half* %base, i32 %offset, i32 %vl) @@ -2592,10 +2592,10 @@ define void @test_vssseg2_mask_nxv16f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv16f16( %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -2608,10 +2608,10 @@ define void @test_vssseg2_nxv4f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4f64( %val, %val, double* %base, i32 %offset, i32 %vl) @@ -2621,10 +2621,10 @@ define void @test_vssseg2_mask_nxv4f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4f64( %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -2637,10 +2637,10 @@ define void @test_vssseg2_nxv1f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1f64( %val, %val, double* %base, i32 %offset, i32 %vl) @@ -2650,10 +2650,10 @@ define void @test_vssseg2_mask_nxv1f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1f64( %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -2666,11 +2666,11 @@ define void @test_vssseg3_nxv1f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1f64( %val, %val, %val, double* %base, i32 %offset, i32 %vl) @@ -2680,11 +2680,11 @@ define void @test_vssseg3_mask_nxv1f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1f64( %val, %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -2697,12 +2697,12 @@ define void @test_vssseg4_nxv1f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1f64( %val, %val, %val, %val, double* %base, i32 %offset, i32 %vl) @@ -2712,12 +2712,12 @@ define void @test_vssseg4_mask_nxv1f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1f64( %val, %val, %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -2730,13 +2730,13 @@ define void @test_vssseg5_nxv1f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg5e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1f64( %val, %val, %val, %val, %val, double* %base, i32 %offset, i32 %vl) @@ -2746,13 +2746,13 @@ define void @test_vssseg5_mask_nxv1f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg5e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1f64( %val, %val, %val, %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -2765,14 +2765,14 @@ define void @test_vssseg6_nxv1f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg6e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1f64( %val, %val, %val, %val, %val, %val, double* %base, i32 %offset, i32 %vl) @@ -2782,14 +2782,14 @@ define void @test_vssseg6_mask_nxv1f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg6e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1f64( %val, %val, %val, %val, %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -2802,15 +2802,15 @@ define void @test_vssseg7_nxv1f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg7e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1f64( %val, %val, %val, %val, %val, %val, %val, double* %base, i32 %offset, i32 %vl) @@ -2820,15 +2820,15 @@ define void @test_vssseg7_mask_nxv1f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg7e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1f64( %val, %val, %val, %val, %val, %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -2841,16 +2841,16 @@ define void @test_vssseg8_nxv1f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg8e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1f64( %val, %val, %val, %val, %val, %val, %val, %val, double* %base, i32 %offset, i32 %vl) @@ -2860,16 +2860,16 @@ define void @test_vssseg8_mask_nxv1f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg8e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1f64( %val, %val, %val, %val, %val, %val, %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -2882,10 +2882,10 @@ define void @test_vssseg2_nxv2f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2f32( %val, %val, float* %base, i32 %offset, i32 %vl) @@ -2895,10 +2895,10 @@ define void @test_vssseg2_mask_nxv2f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2f32( %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -2911,11 +2911,11 @@ define void @test_vssseg3_nxv2f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2f32( %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -2925,11 +2925,11 @@ define void @test_vssseg3_mask_nxv2f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2f32( %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -2942,12 +2942,12 @@ define void @test_vssseg4_nxv2f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2f32( %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -2957,12 +2957,12 @@ define void @test_vssseg4_mask_nxv2f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2f32( %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -2975,13 +2975,13 @@ define void @test_vssseg5_nxv2f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2f32( %val, %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -2991,13 +2991,13 @@ define void @test_vssseg5_mask_nxv2f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2f32( %val, %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3010,14 +3010,14 @@ define void @test_vssseg6_nxv2f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2f32( %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3027,14 +3027,14 @@ define void @test_vssseg6_mask_nxv2f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2f32( %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3047,15 +3047,15 @@ define void @test_vssseg7_nxv2f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3065,15 +3065,15 @@ define void @test_vssseg7_mask_nxv2f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3086,16 +3086,16 @@ define void @test_vssseg8_nxv2f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3105,16 +3105,16 @@ define void @test_vssseg8_mask_nxv2f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3127,10 +3127,10 @@ define void @test_vssseg2_nxv1f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1f16( %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3140,10 +3140,10 @@ define void @test_vssseg2_mask_nxv1f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1f16( %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3156,11 +3156,11 @@ define void @test_vssseg3_nxv1f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1f16( %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3170,11 +3170,11 @@ define void @test_vssseg3_mask_nxv1f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1f16( %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3187,12 +3187,12 @@ define void @test_vssseg4_nxv1f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1f16( %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3202,12 +3202,12 @@ define void @test_vssseg4_mask_nxv1f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1f16( %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3220,13 +3220,13 @@ define void @test_vssseg5_nxv1f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1f16( %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3236,13 +3236,13 @@ define void @test_vssseg5_mask_nxv1f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1f16( %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3255,14 +3255,14 @@ define void @test_vssseg6_nxv1f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1f16( %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3272,14 +3272,14 @@ define void @test_vssseg6_mask_nxv1f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1f16( %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3292,15 +3292,15 @@ define void @test_vssseg7_nxv1f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3310,15 +3310,15 @@ define void @test_vssseg7_mask_nxv1f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3331,16 +3331,16 @@ define void @test_vssseg8_nxv1f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3350,16 +3350,16 @@ define void @test_vssseg8_mask_nxv1f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3372,10 +3372,10 @@ define void @test_vssseg2_nxv1f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1f32( %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3385,10 +3385,10 @@ define void @test_vssseg2_mask_nxv1f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1f32( %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3401,11 +3401,11 @@ define void @test_vssseg3_nxv1f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1f32( %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3415,11 +3415,11 @@ define void @test_vssseg3_mask_nxv1f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1f32( %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3432,12 +3432,12 @@ define void @test_vssseg4_nxv1f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1f32( %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3447,12 +3447,12 @@ define void @test_vssseg4_mask_nxv1f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1f32( %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3465,13 +3465,13 @@ define void @test_vssseg5_nxv1f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1f32( %val, %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3481,13 +3481,13 @@ define void @test_vssseg5_mask_nxv1f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1f32( %val, %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3500,14 +3500,14 @@ define void @test_vssseg6_nxv1f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1f32( %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3517,14 +3517,14 @@ define void @test_vssseg6_mask_nxv1f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1f32( %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3537,15 +3537,15 @@ define void @test_vssseg7_nxv1f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3555,15 +3555,15 @@ define void @test_vssseg7_mask_nxv1f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3576,16 +3576,16 @@ define void @test_vssseg8_nxv1f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3595,16 +3595,16 @@ define void @test_vssseg8_mask_nxv1f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3617,10 +3617,10 @@ define void @test_vssseg2_nxv8f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8f16( %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3630,10 +3630,10 @@ define void @test_vssseg2_mask_nxv8f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8f16( %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3646,11 +3646,11 @@ define void @test_vssseg3_nxv8f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv8f16( %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3660,11 +3660,11 @@ define void @test_vssseg3_mask_nxv8f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv8f16( %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3677,12 +3677,12 @@ define void @test_vssseg4_nxv8f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv8f16( %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3692,12 +3692,12 @@ define void @test_vssseg4_mask_nxv8f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv8f16( %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3710,10 +3710,10 @@ define void @test_vssseg2_nxv8f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8f32( %val, %val, float* %base, i32 %offset, i32 %vl) @@ -3723,10 +3723,10 @@ define void @test_vssseg2_mask_nxv8f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8f32( %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -3739,10 +3739,10 @@ define void @test_vssseg2_nxv2f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2f64( %val, %val, double* %base, i32 %offset, i32 %vl) @@ -3752,10 +3752,10 @@ define void @test_vssseg2_mask_nxv2f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2f64( %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -3768,11 +3768,11 @@ define void @test_vssseg3_nxv2f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2f64( %val, %val, %val, double* %base, i32 %offset, i32 %vl) @@ -3782,11 +3782,11 @@ define void @test_vssseg3_mask_nxv2f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2f64( %val, %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -3799,12 +3799,12 @@ define void @test_vssseg4_nxv2f64( %val, double* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2f64( %val, %val, %val, %val, double* %base, i32 %offset, i32 %vl) @@ -3814,12 +3814,12 @@ define void @test_vssseg4_mask_nxv2f64( %val, double* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2f64( %val, %val, %val, %val, double* %base, i32 %offset, %mask, i32 %vl) @@ -3832,10 +3832,10 @@ define void @test_vssseg2_nxv4f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4f16( %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3845,10 +3845,10 @@ define void @test_vssseg2_mask_nxv4f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4f16( %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3861,11 +3861,11 @@ define void @test_vssseg3_nxv4f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4f16( %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3875,11 +3875,11 @@ define void @test_vssseg3_mask_nxv4f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4f16( %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3892,12 +3892,12 @@ define void @test_vssseg4_nxv4f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4f16( %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3907,12 +3907,12 @@ define void @test_vssseg4_mask_nxv4f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4f16( %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3925,13 +3925,13 @@ define void @test_vssseg5_nxv4f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv4f16( %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3941,13 +3941,13 @@ define void @test_vssseg5_mask_nxv4f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv4f16( %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3960,14 +3960,14 @@ define void @test_vssseg6_nxv4f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv4f16( %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -3977,14 +3977,14 @@ define void @test_vssseg6_mask_nxv4f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv4f16( %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -3997,15 +3997,15 @@ define void @test_vssseg7_nxv4f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv4f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -4015,15 +4015,15 @@ define void @test_vssseg7_mask_nxv4f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv4f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -4036,16 +4036,16 @@ define void @test_vssseg8_nxv4f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv4f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -4055,16 +4055,16 @@ define void @test_vssseg8_mask_nxv4f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv4f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -4077,10 +4077,10 @@ define void @test_vssseg2_nxv2f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2f16( %val, %val, half* %base, i32 %offset, i32 %vl) @@ -4090,10 +4090,10 @@ define void @test_vssseg2_mask_nxv2f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2f16( %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -4106,11 +4106,11 @@ define void @test_vssseg3_nxv2f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2f16( %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -4120,11 +4120,11 @@ define void @test_vssseg3_mask_nxv2f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2f16( %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -4137,12 +4137,12 @@ define void @test_vssseg4_nxv2f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2f16( %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -4152,12 +4152,12 @@ define void @test_vssseg4_mask_nxv2f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2f16( %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -4170,13 +4170,13 @@ define void @test_vssseg5_nxv2f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2f16( %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -4186,13 +4186,13 @@ define void @test_vssseg5_mask_nxv2f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2f16( %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -4205,14 +4205,14 @@ define void @test_vssseg6_nxv2f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2f16( %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -4222,14 +4222,14 @@ define void @test_vssseg6_mask_nxv2f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2f16( %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -4242,15 +4242,15 @@ define void @test_vssseg7_nxv2f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -4260,15 +4260,15 @@ define void @test_vssseg7_mask_nxv2f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -4281,16 +4281,16 @@ define void @test_vssseg8_nxv2f16( %val, half* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, i32 %vl) @@ -4300,16 +4300,16 @@ define void @test_vssseg8_mask_nxv2f16( %val, half* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i32 %offset, %mask, i32 %vl) @@ -4322,10 +4322,10 @@ define void @test_vssseg2_nxv4f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4f32( %val, %val, float* %base, i32 %offset, i32 %vl) @@ -4335,10 +4335,10 @@ define void @test_vssseg2_mask_nxv4f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4f32( %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -4351,11 +4351,11 @@ define void @test_vssseg3_nxv4f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4f32( %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -4365,11 +4365,11 @@ define void @test_vssseg3_mask_nxv4f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4f32( %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) @@ -4382,12 +4382,12 @@ define void @test_vssseg4_nxv4f32( %val, float* %base, i32 %offset, i32 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4f32( %val, %val, %val, %val, float* %base, i32 %offset, i32 %vl) @@ -4397,12 +4397,12 @@ define void @test_vssseg4_mask_nxv4f32( %val, float* %base, i32 %offset, %mask, i32 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4f32( %val, %val, %val, %val, float* %base, i32 %offset, %mask, i32 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll @@ -8,10 +8,10 @@ define void @test_vssseg2_nxv16i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv16i16( %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -21,10 +21,10 @@ define void @test_vssseg2_mask_nxv16i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv16i16( %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -37,10 +37,10 @@ define void @test_vssseg2_nxv4i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4i32( %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -50,10 +50,10 @@ define void @test_vssseg2_mask_nxv4i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4i32( %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -66,11 +66,11 @@ define void @test_vssseg3_nxv4i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4i32( %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -80,11 +80,11 @@ define void @test_vssseg3_mask_nxv4i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4i32( %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -97,12 +97,12 @@ define void @test_vssseg4_nxv4i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4i32( %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -112,12 +112,12 @@ define void @test_vssseg4_mask_nxv4i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4i32( %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -130,10 +130,10 @@ define void @test_vssseg2_nxv16i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv16i8( %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -143,10 +143,10 @@ define void @test_vssseg2_mask_nxv16i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv16i8( %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -159,11 +159,11 @@ define void @test_vssseg3_nxv16i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv16i8( %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -173,11 +173,11 @@ define void @test_vssseg3_mask_nxv16i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv16i8( %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -190,12 +190,12 @@ define void @test_vssseg4_nxv16i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv16i8( %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -205,12 +205,12 @@ define void @test_vssseg4_mask_nxv16i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv16i8( %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -223,10 +223,10 @@ define void @test_vssseg2_nxv1i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1i64( %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -236,10 +236,10 @@ define void @test_vssseg2_mask_nxv1i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1i64( %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -252,11 +252,11 @@ define void @test_vssseg3_nxv1i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1i64( %val, %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -266,11 +266,11 @@ define void @test_vssseg3_mask_nxv1i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1i64( %val, %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -283,12 +283,12 @@ define void @test_vssseg4_nxv1i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1i64( %val, %val, %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -298,12 +298,12 @@ define void @test_vssseg4_mask_nxv1i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1i64( %val, %val, %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -316,13 +316,13 @@ define void @test_vssseg5_nxv1i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg5e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1i64( %val, %val, %val, %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -332,13 +332,13 @@ define void @test_vssseg5_mask_nxv1i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg5e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1i64( %val, %val, %val, %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -351,14 +351,14 @@ define void @test_vssseg6_nxv1i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg6e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1i64( %val, %val, %val, %val, %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -368,14 +368,14 @@ define void @test_vssseg6_mask_nxv1i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg6e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1i64( %val, %val, %val, %val, %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -388,15 +388,15 @@ define void @test_vssseg7_nxv1i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg7e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1i64( %val, %val, %val, %val, %val, %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -406,15 +406,15 @@ define void @test_vssseg7_mask_nxv1i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg7e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1i64( %val, %val, %val, %val, %val, %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -427,16 +427,16 @@ define void @test_vssseg8_nxv1i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg8e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1i64( %val, %val, %val, %val, %val, %val, %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -446,16 +446,16 @@ define void @test_vssseg8_mask_nxv1i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg8e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1i64( %val, %val, %val, %val, %val, %val, %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -468,10 +468,10 @@ define void @test_vssseg2_nxv1i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1i32( %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -481,10 +481,10 @@ define void @test_vssseg2_mask_nxv1i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1i32( %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -497,11 +497,11 @@ define void @test_vssseg3_nxv1i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1i32( %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -511,11 +511,11 @@ define void @test_vssseg3_mask_nxv1i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1i32( %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -528,12 +528,12 @@ define void @test_vssseg4_nxv1i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1i32( %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -543,12 +543,12 @@ define void @test_vssseg4_mask_nxv1i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1i32( %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -561,13 +561,13 @@ define void @test_vssseg5_nxv1i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1i32( %val, %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -577,13 +577,13 @@ define void @test_vssseg5_mask_nxv1i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1i32( %val, %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -596,14 +596,14 @@ define void @test_vssseg6_nxv1i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1i32( %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -613,14 +613,14 @@ define void @test_vssseg6_mask_nxv1i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1i32( %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -633,15 +633,15 @@ define void @test_vssseg7_nxv1i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -651,15 +651,15 @@ define void @test_vssseg7_mask_nxv1i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -672,16 +672,16 @@ define void @test_vssseg8_nxv1i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -691,16 +691,16 @@ define void @test_vssseg8_mask_nxv1i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -713,10 +713,10 @@ define void @test_vssseg2_nxv8i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8i16( %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -726,10 +726,10 @@ define void @test_vssseg2_mask_nxv8i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8i16( %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -742,11 +742,11 @@ define void @test_vssseg3_nxv8i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv8i16( %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -756,11 +756,11 @@ define void @test_vssseg3_mask_nxv8i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv8i16( %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -773,12 +773,12 @@ define void @test_vssseg4_nxv8i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv8i16( %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -788,12 +788,12 @@ define void @test_vssseg4_mask_nxv8i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv8i16( %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -806,10 +806,10 @@ define void @test_vssseg2_nxv4i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4i8( %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -819,10 +819,10 @@ define void @test_vssseg2_mask_nxv4i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4i8( %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -835,11 +835,11 @@ define void @test_vssseg3_nxv4i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4i8( %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -849,11 +849,11 @@ define void @test_vssseg3_mask_nxv4i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4i8( %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -866,12 +866,12 @@ define void @test_vssseg4_nxv4i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4i8( %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -881,12 +881,12 @@ define void @test_vssseg4_mask_nxv4i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4i8( %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -899,13 +899,13 @@ define void @test_vssseg5_nxv4i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv4i8( %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -915,13 +915,13 @@ define void @test_vssseg5_mask_nxv4i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv4i8( %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -934,14 +934,14 @@ define void @test_vssseg6_nxv4i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv4i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -951,14 +951,14 @@ define void @test_vssseg6_mask_nxv4i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv4i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -971,15 +971,15 @@ define void @test_vssseg7_nxv4i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv4i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -989,15 +989,15 @@ define void @test_vssseg7_mask_nxv4i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv4i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -1010,16 +1010,16 @@ define void @test_vssseg8_nxv4i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv4i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -1029,16 +1029,16 @@ define void @test_vssseg8_mask_nxv4i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf2,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv4i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -1051,10 +1051,10 @@ define void @test_vssseg2_nxv1i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1i16( %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1064,10 +1064,10 @@ define void @test_vssseg2_mask_nxv1i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1i16( %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1080,11 +1080,11 @@ define void @test_vssseg3_nxv1i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1i16( %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1094,11 +1094,11 @@ define void @test_vssseg3_mask_nxv1i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1i16( %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1111,12 +1111,12 @@ define void @test_vssseg4_nxv1i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1i16( %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1126,12 +1126,12 @@ define void @test_vssseg4_mask_nxv1i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1i16( %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1144,13 +1144,13 @@ define void @test_vssseg5_nxv1i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1i16( %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1160,13 +1160,13 @@ define void @test_vssseg5_mask_nxv1i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1i16( %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1179,14 +1179,14 @@ define void @test_vssseg6_nxv1i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1i16( %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1196,14 +1196,14 @@ define void @test_vssseg6_mask_nxv1i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1i16( %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1216,15 +1216,15 @@ define void @test_vssseg7_nxv1i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1234,15 +1234,15 @@ define void @test_vssseg7_mask_nxv1i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1255,16 +1255,16 @@ define void @test_vssseg8_nxv1i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1274,16 +1274,16 @@ define void @test_vssseg8_mask_nxv1i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1296,10 +1296,10 @@ define void @test_vssseg2_nxv2i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2i32( %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -1309,10 +1309,10 @@ define void @test_vssseg2_mask_nxv2i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2i32( %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -1325,11 +1325,11 @@ define void @test_vssseg3_nxv2i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2i32( %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -1339,11 +1339,11 @@ define void @test_vssseg3_mask_nxv2i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2i32( %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -1356,12 +1356,12 @@ define void @test_vssseg4_nxv2i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2i32( %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -1371,12 +1371,12 @@ define void @test_vssseg4_mask_nxv2i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2i32( %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -1389,13 +1389,13 @@ define void @test_vssseg5_nxv2i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2i32( %val, %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -1405,13 +1405,13 @@ define void @test_vssseg5_mask_nxv2i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2i32( %val, %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -1424,14 +1424,14 @@ define void @test_vssseg6_nxv2i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2i32( %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -1441,14 +1441,14 @@ define void @test_vssseg6_mask_nxv2i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2i32( %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -1461,15 +1461,15 @@ define void @test_vssseg7_nxv2i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -1479,15 +1479,15 @@ define void @test_vssseg7_mask_nxv2i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2i32( %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -1500,16 +1500,16 @@ define void @test_vssseg8_nxv2i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -1519,16 +1519,16 @@ define void @test_vssseg8_mask_nxv2i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2i32( %val, %val, %val, %val, %val, %val, %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -1541,10 +1541,10 @@ define void @test_vssseg2_nxv8i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8i8( %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -1554,10 +1554,10 @@ define void @test_vssseg2_mask_nxv8i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8i8( %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -1570,11 +1570,11 @@ define void @test_vssseg3_nxv8i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv8i8( %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -1584,11 +1584,11 @@ define void @test_vssseg3_mask_nxv8i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv8i8( %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -1601,12 +1601,12 @@ define void @test_vssseg4_nxv8i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv8i8( %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -1616,12 +1616,12 @@ define void @test_vssseg4_mask_nxv8i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv8i8( %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -1634,13 +1634,13 @@ define void @test_vssseg5_nxv8i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv8i8( %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -1650,13 +1650,13 @@ define void @test_vssseg5_mask_nxv8i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv8i8( %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -1669,14 +1669,14 @@ define void @test_vssseg6_nxv8i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv8i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -1686,14 +1686,14 @@ define void @test_vssseg6_mask_nxv8i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv8i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -1706,15 +1706,15 @@ define void @test_vssseg7_nxv8i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv8i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -1724,15 +1724,15 @@ define void @test_vssseg7_mask_nxv8i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv8i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -1745,16 +1745,16 @@ define void @test_vssseg8_nxv8i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv8i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -1764,16 +1764,16 @@ define void @test_vssseg8_mask_nxv8i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv8i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -1786,10 +1786,10 @@ define void @test_vssseg2_nxv4i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4i64( %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -1799,10 +1799,10 @@ define void @test_vssseg2_mask_nxv4i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4i64( %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -1815,10 +1815,10 @@ define void @test_vssseg2_nxv4i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4i16( %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1828,10 +1828,10 @@ define void @test_vssseg2_mask_nxv4i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4i16( %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1844,11 +1844,11 @@ define void @test_vssseg3_nxv4i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4i16( %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1858,11 +1858,11 @@ define void @test_vssseg3_mask_nxv4i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4i16( %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1875,12 +1875,12 @@ define void @test_vssseg4_nxv4i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4i16( %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1890,12 +1890,12 @@ define void @test_vssseg4_mask_nxv4i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4i16( %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1908,13 +1908,13 @@ define void @test_vssseg5_nxv4i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv4i16( %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1924,13 +1924,13 @@ define void @test_vssseg5_mask_nxv4i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv4i16( %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1943,14 +1943,14 @@ define void @test_vssseg6_nxv4i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv4i16( %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1960,14 +1960,14 @@ define void @test_vssseg6_mask_nxv4i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv4i16( %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -1980,15 +1980,15 @@ define void @test_vssseg7_nxv4i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv4i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -1998,15 +1998,15 @@ define void @test_vssseg7_mask_nxv4i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv4i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -2019,16 +2019,16 @@ define void @test_vssseg8_nxv4i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv4i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -2038,16 +2038,16 @@ define void @test_vssseg8_mask_nxv4i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv4i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -2060,10 +2060,10 @@ define void @test_vssseg2_nxv1i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1i8( %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2073,10 +2073,10 @@ define void @test_vssseg2_mask_nxv1i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1i8( %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2089,11 +2089,11 @@ define void @test_vssseg3_nxv1i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1i8( %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2103,11 +2103,11 @@ define void @test_vssseg3_mask_nxv1i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1i8( %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2120,12 +2120,12 @@ define void @test_vssseg4_nxv1i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1i8( %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2135,12 +2135,12 @@ define void @test_vssseg4_mask_nxv1i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1i8( %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2153,13 +2153,13 @@ define void @test_vssseg5_nxv1i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1i8( %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2169,13 +2169,13 @@ define void @test_vssseg5_mask_nxv1i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1i8( %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2188,14 +2188,14 @@ define void @test_vssseg6_nxv1i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2205,14 +2205,14 @@ define void @test_vssseg6_mask_nxv1i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2225,15 +2225,15 @@ define void @test_vssseg7_nxv1i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2243,15 +2243,15 @@ define void @test_vssseg7_mask_nxv1i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2264,16 +2264,16 @@ define void @test_vssseg8_nxv1i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2283,16 +2283,16 @@ define void @test_vssseg8_mask_nxv1i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf8,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2305,10 +2305,10 @@ define void @test_vssseg2_nxv2i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2i8( %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2318,10 +2318,10 @@ define void @test_vssseg2_mask_nxv2i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2i8( %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2334,11 +2334,11 @@ define void @test_vssseg3_nxv2i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2i8( %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2348,11 +2348,11 @@ define void @test_vssseg3_mask_nxv2i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg3e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2i8( %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2365,12 +2365,12 @@ define void @test_vssseg4_nxv2i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2i8( %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2380,12 +2380,12 @@ define void @test_vssseg4_mask_nxv2i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg4e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2i8( %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2398,13 +2398,13 @@ define void @test_vssseg5_nxv2i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2i8( %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2414,13 +2414,13 @@ define void @test_vssseg5_mask_nxv2i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg5e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2i8( %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2433,14 +2433,14 @@ define void @test_vssseg6_nxv2i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2450,14 +2450,14 @@ define void @test_vssseg6_mask_nxv2i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg6e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2i8( %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2470,15 +2470,15 @@ define void @test_vssseg7_nxv2i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2488,15 +2488,15 @@ define void @test_vssseg7_mask_nxv2i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg7e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2i8( %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2509,16 +2509,16 @@ define void @test_vssseg8_nxv2i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2528,16 +2528,16 @@ define void @test_vssseg8_mask_nxv2i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,mf4,ta,mu -; CHECK-NEXT: vssseg8e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2i8( %val, %val, %val, %val, %val, %val, %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2550,10 +2550,10 @@ define void @test_vssseg2_nxv8i32( %val, i32* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8i32( %val, %val, i32* %base, i64 %offset, i64 %vl) @@ -2563,10 +2563,10 @@ define void @test_vssseg2_mask_nxv8i32( %val, i32* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8i32( %val, %val, i32* %base, i64 %offset, %mask, i64 %vl) @@ -2579,10 +2579,10 @@ define void @test_vssseg2_nxv32i8( %val, i8* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv32i8( %val, %val, i8* %base, i64 %offset, i64 %vl) @@ -2592,10 +2592,10 @@ define void @test_vssseg2_mask_nxv32i8( %val, i8* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu -; CHECK-NEXT: vssseg2e8.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e8.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv32i8( %val, %val, i8* %base, i64 %offset, %mask, i64 %vl) @@ -2608,10 +2608,10 @@ define void @test_vssseg2_nxv2i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2i16( %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -2621,10 +2621,10 @@ define void @test_vssseg2_mask_nxv2i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2i16( %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -2637,11 +2637,11 @@ define void @test_vssseg3_nxv2i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2i16( %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -2651,11 +2651,11 @@ define void @test_vssseg3_mask_nxv2i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2i16( %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -2668,12 +2668,12 @@ define void @test_vssseg4_nxv2i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2i16( %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -2683,12 +2683,12 @@ define void @test_vssseg4_mask_nxv2i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2i16( %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -2701,13 +2701,13 @@ define void @test_vssseg5_nxv2i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2i16( %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -2717,13 +2717,13 @@ define void @test_vssseg5_mask_nxv2i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2i16( %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -2736,14 +2736,14 @@ define void @test_vssseg6_nxv2i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2i16( %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -2753,14 +2753,14 @@ define void @test_vssseg6_mask_nxv2i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2i16( %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -2773,15 +2773,15 @@ define void @test_vssseg7_nxv2i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -2791,15 +2791,15 @@ define void @test_vssseg7_mask_nxv2i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2i16( %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -2812,16 +2812,16 @@ define void @test_vssseg8_nxv2i16( %val, i16* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, i64 %vl) @@ -2831,16 +2831,16 @@ define void @test_vssseg8_mask_nxv2i16( %val, i16* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2i16( %val, %val, %val, %val, %val, %val, %val, %val, i16* %base, i64 %offset, %mask, i64 %vl) @@ -2853,10 +2853,10 @@ define void @test_vssseg2_nxv2i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2i64( %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -2866,10 +2866,10 @@ define void @test_vssseg2_mask_nxv2i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2i64( %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -2882,11 +2882,11 @@ define void @test_vssseg3_nxv2i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2i64( %val, %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -2896,11 +2896,11 @@ define void @test_vssseg3_mask_nxv2i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2i64( %val, %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -2913,12 +2913,12 @@ define void @test_vssseg4_nxv2i64( %val, i64* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2i64( %val, %val, %val, %val, i64* %base, i64 %offset, i64 %vl) @@ -2928,12 +2928,12 @@ define void @test_vssseg4_mask_nxv2i64( %val, i64* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2i64( %val, %val, %val, %val, i64* %base, i64 %offset, %mask, i64 %vl) @@ -2946,10 +2946,10 @@ define void @test_vssseg2_nxv16f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv16f16( %val, %val, half* %base, i64 %offset, i64 %vl) @@ -2959,10 +2959,10 @@ define void @test_vssseg2_mask_nxv16f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv16f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv16f16( %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -2975,10 +2975,10 @@ define void @test_vssseg2_nxv4f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4f64( %val, %val, double* %base, i64 %offset, i64 %vl) @@ -2988,10 +2988,10 @@ define void @test_vssseg2_mask_nxv4f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m4,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4f64( %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -3004,10 +3004,10 @@ define void @test_vssseg2_nxv1f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1f64( %val, %val, double* %base, i64 %offset, i64 %vl) @@ -3017,10 +3017,10 @@ define void @test_vssseg2_mask_nxv1f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1f64( %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -3033,11 +3033,11 @@ define void @test_vssseg3_nxv1f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1f64( %val, %val, %val, double* %base, i64 %offset, i64 %vl) @@ -3047,11 +3047,11 @@ define void @test_vssseg3_mask_nxv1f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1f64( %val, %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -3064,12 +3064,12 @@ define void @test_vssseg4_nxv1f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1f64( %val, %val, %val, %val, double* %base, i64 %offset, i64 %vl) @@ -3079,12 +3079,12 @@ define void @test_vssseg4_mask_nxv1f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1f64( %val, %val, %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -3097,13 +3097,13 @@ define void @test_vssseg5_nxv1f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg5e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1f64( %val, %val, %val, %val, %val, double* %base, i64 %offset, i64 %vl) @@ -3113,13 +3113,13 @@ define void @test_vssseg5_mask_nxv1f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg5e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1f64( %val, %val, %val, %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -3132,14 +3132,14 @@ define void @test_vssseg6_nxv1f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg6e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1f64( %val, %val, %val, %val, %val, %val, double* %base, i64 %offset, i64 %vl) @@ -3149,14 +3149,14 @@ define void @test_vssseg6_mask_nxv1f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg6e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1f64( %val, %val, %val, %val, %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -3169,15 +3169,15 @@ define void @test_vssseg7_nxv1f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg7e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1f64( %val, %val, %val, %val, %val, %val, %val, double* %base, i64 %offset, i64 %vl) @@ -3187,15 +3187,15 @@ define void @test_vssseg7_mask_nxv1f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg7e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1f64( %val, %val, %val, %val, %val, %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -3208,16 +3208,16 @@ define void @test_vssseg8_nxv1f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg8e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1f64( %val, %val, %val, %val, %val, %val, %val, %val, double* %base, i64 %offset, i64 %vl) @@ -3227,16 +3227,16 @@ define void @test_vssseg8_mask_nxv1f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m1,ta,mu -; CHECK-NEXT: vssseg8e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1f64( %val, %val, %val, %val, %val, %val, %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -3249,10 +3249,10 @@ define void @test_vssseg2_nxv2f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2f32( %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3262,10 +3262,10 @@ define void @test_vssseg2_mask_nxv2f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2f32( %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3278,11 +3278,11 @@ define void @test_vssseg3_nxv2f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2f32( %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3292,11 +3292,11 @@ define void @test_vssseg3_mask_nxv2f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2f32( %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3309,12 +3309,12 @@ define void @test_vssseg4_nxv2f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2f32( %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3324,12 +3324,12 @@ define void @test_vssseg4_mask_nxv2f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2f32( %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3342,13 +3342,13 @@ define void @test_vssseg5_nxv2f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2f32( %val, %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3358,13 +3358,13 @@ define void @test_vssseg5_mask_nxv2f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2f32( %val, %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3377,14 +3377,14 @@ define void @test_vssseg6_nxv2f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2f32( %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3394,14 +3394,14 @@ define void @test_vssseg6_mask_nxv2f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2f32( %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3414,15 +3414,15 @@ define void @test_vssseg7_nxv2f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3432,15 +3432,15 @@ define void @test_vssseg7_mask_nxv2f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3453,16 +3453,16 @@ define void @test_vssseg8_nxv2f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3472,16 +3472,16 @@ define void @test_vssseg8_mask_nxv2f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m1,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3494,10 +3494,10 @@ define void @test_vssseg2_nxv1f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1f16( %val, %val, half* %base, i64 %offset, i64 %vl) @@ -3507,10 +3507,10 @@ define void @test_vssseg2_mask_nxv1f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1f16( %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -3523,11 +3523,11 @@ define void @test_vssseg3_nxv1f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1f16( %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -3537,11 +3537,11 @@ define void @test_vssseg3_mask_nxv1f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1f16( %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -3554,12 +3554,12 @@ define void @test_vssseg4_nxv1f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1f16( %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -3569,12 +3569,12 @@ define void @test_vssseg4_mask_nxv1f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1f16( %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -3587,13 +3587,13 @@ define void @test_vssseg5_nxv1f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1f16( %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -3603,13 +3603,13 @@ define void @test_vssseg5_mask_nxv1f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1f16( %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -3622,14 +3622,14 @@ define void @test_vssseg6_nxv1f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1f16( %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -3639,14 +3639,14 @@ define void @test_vssseg6_mask_nxv1f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1f16( %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -3659,15 +3659,15 @@ define void @test_vssseg7_nxv1f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -3677,15 +3677,15 @@ define void @test_vssseg7_mask_nxv1f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -3698,16 +3698,16 @@ define void @test_vssseg8_nxv1f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -3717,16 +3717,16 @@ define void @test_vssseg8_mask_nxv1f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf4,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -3739,10 +3739,10 @@ define void @test_vssseg2_nxv1f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv1f32( %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3752,10 +3752,10 @@ define void @test_vssseg2_mask_nxv1f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv1f32( %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3768,11 +3768,11 @@ define void @test_vssseg3_nxv1f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv1f32( %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3782,11 +3782,11 @@ define void @test_vssseg3_mask_nxv1f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv1f32( %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3799,12 +3799,12 @@ define void @test_vssseg4_nxv1f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv1f32( %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3814,12 +3814,12 @@ define void @test_vssseg4_mask_nxv1f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv1f32( %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3832,13 +3832,13 @@ define void @test_vssseg5_nxv1f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv1f32( %val, %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3848,13 +3848,13 @@ define void @test_vssseg5_mask_nxv1f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg5e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv1f32( %val, %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3867,14 +3867,14 @@ define void @test_vssseg6_nxv1f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv1f32( %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3884,14 +3884,14 @@ define void @test_vssseg6_mask_nxv1f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg6e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv1f32( %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3904,15 +3904,15 @@ define void @test_vssseg7_nxv1f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv1f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3922,15 +3922,15 @@ define void @test_vssseg7_mask_nxv1f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg7e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv1f32( %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3943,16 +3943,16 @@ define void @test_vssseg8_nxv1f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv1f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -3962,16 +3962,16 @@ define void @test_vssseg8_mask_nxv1f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,mf2,ta,mu -; CHECK-NEXT: vssseg8e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv1f32( %val, %val, %val, %val, %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -3984,10 +3984,10 @@ define void @test_vssseg2_nxv8f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8f16( %val, %val, half* %base, i64 %offset, i64 %vl) @@ -3997,10 +3997,10 @@ define void @test_vssseg2_mask_nxv8f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8f16( %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4013,11 +4013,11 @@ define void @test_vssseg3_nxv8f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv8f16( %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4027,11 +4027,11 @@ define void @test_vssseg3_mask_nxv8f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv8f16( %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4044,12 +4044,12 @@ define void @test_vssseg4_nxv8f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv8f16( %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4059,12 +4059,12 @@ define void @test_vssseg4_mask_nxv8f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv8f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv8f16( %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4077,10 +4077,10 @@ define void @test_vssseg2_nxv8f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv8f32( %val, %val, float* %base, i64 %offset, i64 %vl) @@ -4090,10 +4090,10 @@ define void @test_vssseg2_mask_nxv8f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv8f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4 -; CHECK-NEXT: vmv4r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4 +; CHECK-NEXT: vmv4r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m4,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv8f32( %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -4106,10 +4106,10 @@ define void @test_vssseg2_nxv2f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2f64( %val, %val, double* %base, i64 %offset, i64 %vl) @@ -4119,10 +4119,10 @@ define void @test_vssseg2_mask_nxv2f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg2e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2f64( %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -4135,11 +4135,11 @@ define void @test_vssseg3_nxv2f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2f64( %val, %val, %val, double* %base, i64 %offset, i64 %vl) @@ -4149,11 +4149,11 @@ define void @test_vssseg3_mask_nxv2f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg3e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2f64( %val, %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -4166,12 +4166,12 @@ define void @test_vssseg4_nxv2f64( %val, double* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2f64( %val, %val, %val, %val, double* %base, i64 %offset, i64 %vl) @@ -4181,12 +4181,12 @@ define void @test_vssseg4_mask_nxv2f64( %val, double* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e64,m2,ta,mu -; CHECK-NEXT: vssseg4e64.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e64.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2f64( %val, %val, %val, %val, double* %base, i64 %offset, %mask, i64 %vl) @@ -4199,10 +4199,10 @@ define void @test_vssseg2_nxv4f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4f16( %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4212,10 +4212,10 @@ define void @test_vssseg2_mask_nxv4f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4f16( %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4228,11 +4228,11 @@ define void @test_vssseg3_nxv4f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4f16( %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4242,11 +4242,11 @@ define void @test_vssseg3_mask_nxv4f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4f16( %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4259,12 +4259,12 @@ define void @test_vssseg4_nxv4f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4f16( %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4274,12 +4274,12 @@ define void @test_vssseg4_mask_nxv4f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4f16( %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4292,13 +4292,13 @@ define void @test_vssseg5_nxv4f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv4f16( %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4308,13 +4308,13 @@ define void @test_vssseg5_mask_nxv4f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv4f16( %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4327,14 +4327,14 @@ define void @test_vssseg6_nxv4f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv4f16( %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4344,14 +4344,14 @@ define void @test_vssseg6_mask_nxv4f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv4f16( %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4364,15 +4364,15 @@ define void @test_vssseg7_nxv4f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv4f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4382,15 +4382,15 @@ define void @test_vssseg7_mask_nxv4f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv4f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4403,16 +4403,16 @@ define void @test_vssseg8_nxv4f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv4f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4422,16 +4422,16 @@ define void @test_vssseg8_mask_nxv4f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,m1,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv4f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4444,10 +4444,10 @@ define void @test_vssseg2_nxv2f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv2f16( %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4457,10 +4457,10 @@ define void @test_vssseg2_mask_nxv2f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17 -; CHECK-NEXT: vmv1r.v v17, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9 +; CHECK-NEXT: vmv1r.v v9, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg2e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv2f16( %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4473,11 +4473,11 @@ define void @test_vssseg3_nxv2f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv2f16( %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4487,11 +4487,11 @@ define void @test_vssseg3_mask_nxv2f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg3e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv2f16( %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4504,12 +4504,12 @@ define void @test_vssseg4_nxv2f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv2f16( %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4519,12 +4519,12 @@ define void @test_vssseg4_mask_nxv2f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg4e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv2f16( %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4537,13 +4537,13 @@ define void @test_vssseg5_nxv2f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg5_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.nxv2f16( %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4553,13 +4553,13 @@ define void @test_vssseg5_mask_nxv2f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg5_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg5e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg5e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg5.mask.nxv2f16( %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4572,14 +4572,14 @@ define void @test_vssseg6_nxv2f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg6_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.nxv2f16( %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4589,14 +4589,14 @@ define void @test_vssseg6_mask_nxv2f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg6_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg6e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg6e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg6.mask.nxv2f16( %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4609,15 +4609,15 @@ define void @test_vssseg7_nxv2f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg7_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.nxv2f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4627,15 +4627,15 @@ define void @test_vssseg7_mask_nxv2f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg7_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg7e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg7e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg7.mask.nxv2f16( %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4648,16 +4648,16 @@ define void @test_vssseg8_nxv2f16( %val, half* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg8_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1 +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.nxv2f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, i64 %vl) @@ -4667,16 +4667,16 @@ define void @test_vssseg8_mask_nxv2f16( %val, half* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg8_mask_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23 -; CHECK-NEXT: vmv1r.v v17, v16 -; CHECK-NEXT: vmv1r.v v18, v16 -; CHECK-NEXT: vmv1r.v v19, v16 -; CHECK-NEXT: vmv1r.v v20, v16 -; CHECK-NEXT: vmv1r.v v21, v16 -; CHECK-NEXT: vmv1r.v v22, v16 -; CHECK-NEXT: vmv1r.v v23, v16 +; CHECK-NEXT: # kill: def $v8 killed $v8 def $v8_v9_v10_v11_v12_v13_v14_v15 +; CHECK-NEXT: vmv1r.v v9, v8 +; CHECK-NEXT: vmv1r.v v10, v8 +; CHECK-NEXT: vmv1r.v v11, v8 +; CHECK-NEXT: vmv1r.v v12, v8 +; CHECK-NEXT: vmv1r.v v13, v8 +; CHECK-NEXT: vmv1r.v v14, v8 +; CHECK-NEXT: vmv1r.v v15, v8 ; CHECK-NEXT: vsetvli a2, a2, e16,mf2,ta,mu -; CHECK-NEXT: vssseg8e16.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg8e16.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg8.mask.nxv2f16( %val, %val, %val, %val, %val, %val, %val, %val, half* %base, i64 %offset, %mask, i64 %vl) @@ -4689,10 +4689,10 @@ define void @test_vssseg2_nxv4f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg2_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.nxv4f32( %val, %val, float* %base, i64 %offset, i64 %vl) @@ -4702,10 +4702,10 @@ define void @test_vssseg2_mask_nxv4f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg2_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2 -; CHECK-NEXT: vmv2r.v v18, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2 +; CHECK-NEXT: vmv2r.v v10, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg2e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg2e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg2.mask.nxv4f32( %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -4718,11 +4718,11 @@ define void @test_vssseg3_nxv4f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg3_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.nxv4f32( %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -4732,11 +4732,11 @@ define void @test_vssseg3_mask_nxv4f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg3_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg3e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg3e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg3.mask.nxv4f32( %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) @@ -4749,12 +4749,12 @@ define void @test_vssseg4_nxv4f32( %val, float* %base, i64 %offset, i64 %vl) { ; CHECK-LABEL: test_vssseg4_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1 +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1 ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.nxv4f32( %val, %val, %val, %val, float* %base, i64 %offset, i64 %vl) @@ -4764,12 +4764,12 @@ define void @test_vssseg4_mask_nxv4f32( %val, float* %base, i64 %offset, %mask, i64 %vl) { ; CHECK-LABEL: test_vssseg4_mask_nxv4f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2 -; CHECK-NEXT: vmv2r.v v18, v16 -; CHECK-NEXT: vmv2r.v v20, v16 -; CHECK-NEXT: vmv2r.v v22, v16 +; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2_v14m2 +; CHECK-NEXT: vmv2r.v v10, v8 +; CHECK-NEXT: vmv2r.v v12, v8 +; CHECK-NEXT: vmv2r.v v14, v8 ; CHECK-NEXT: vsetvli a2, a2, e32,m2,ta,mu -; CHECK-NEXT: vssseg4e32.v v16, (a0), a1, v0.t +; CHECK-NEXT: vssseg4e32.v v8, (a0), a1, v0.t ; CHECK-NEXT: ret entry: tail call void @llvm.riscv.vssseg4.mask.nxv4f32( %val, %val, %val, %val, float* %base, i64 %offset, %mask, i64 %vl) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vssub.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vssub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vssub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vssub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vssub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vssub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vssub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vssub_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vssub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vssub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vssub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vssub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vssub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vssub_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vssub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vssub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vssub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vssub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vssub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vssub_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vssub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vssub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vssub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vssub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vssub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vssub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vssub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vssub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vssub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vssub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vssub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vssub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vssub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vssub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vssub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vssub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vssub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vssub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vssub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vssub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vssub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vssub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vssub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vssub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vssub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vssub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vssub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vssub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vssub.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vssub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vssub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vssub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vssub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vssub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vssub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vssub_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vssub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vssub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vssub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vssub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vssub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vssub_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vssub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vssub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vssub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vssub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vssub_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vssub_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vssub_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vssub_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vssub_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vssub_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vssub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vssub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vssub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vssub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vssub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vssub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vssub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vssub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vssub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vssub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vssub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vssub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vssub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vssub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vssub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vssub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vssub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vssub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vssub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vssub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vssub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vssub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vssub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vssub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vssub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vssub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vssub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vssub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vssub_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vssub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vssub_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vssub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vssub_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vssub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vssub_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssub_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vssub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssub.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vssub_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vssub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssub_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssub.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vssubu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vssubu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vssubu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vssubu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vssubu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vssubu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vssubu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vssubu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vssubu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vssubu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vssubu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vssubu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vssubu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vssubu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vssubu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vssubu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vssubu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vssubu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vssubu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vssubu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vssubu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vssubu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vssubu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vssubu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vssubu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vssubu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vssubu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vssubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vssubu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vssubu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vssubu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vssubu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vssubu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vssubu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vssubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vssubu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vssubu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vssubu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vssubu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vssubu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vssubu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vssubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vssubu.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vssubu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vssubu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vssubu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vssubu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vssubu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vssubu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vssubu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vssubu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vssubu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vssubu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vssubu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vssubu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vssubu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vssubu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vssubu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vssubu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vssubu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vssubu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vssubu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vssubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vssubu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vssubu.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vssubu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vssubu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vssubu.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vssubu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vssubu.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vssubu.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vssubu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vssubu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vssubu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vssubu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vssubu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vssubu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vssubu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vssubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vssubu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vssubu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vssubu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vssubu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vssubu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vssubu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vssubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vssubu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vssubu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vssubu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vssubu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vssubu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vssubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vssubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vssubu_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vssubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vssubu_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vssubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vssubu_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vssubu.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vssubu.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vssubu_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vssubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vssubu_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vssubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vssubu.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsub.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vsub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vsub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vsub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vsub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vsub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vsub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vsub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vsub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vsub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vsub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vsub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vsub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vsub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vsub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vsub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vsub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vsub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vsub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vsub.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vsub.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vsub.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vsub.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vsub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vsub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vsub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vsub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vsub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vsub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vsub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vsub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vsub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vsub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vsub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vsub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vsub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vsub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vsub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vsub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vsub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vsub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vsub_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsub.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vsub.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vsub.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vsub_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vsub_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vsub_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vsub_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vsub_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vsub_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vsub_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vsub_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vsub_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v18 +; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vsub_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vsub_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v20 +; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vsub_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vsub_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vsub_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vsub_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vsub_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vsub_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vsub_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vsub_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vsub_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vsub_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vsub_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v18 +; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vsub_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vsub_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v20 +; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vsub_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vsub_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vsub_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vsub_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vsub_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vsub_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vsub_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vsub_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vsub_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v18 +; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vsub_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vsub_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v20 +; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vsub_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vsub_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vsub_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vsub_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vsub_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -655,7 +652,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vsub.vv v16, v16, v25 +; CHECK-NEXT: vsub.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -668,7 +665,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -680,7 +677,7 @@ ; CHECK-LABEL: vsub_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v18 +; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -697,7 +694,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vsub.vv v16, v16, v26 +; CHECK-NEXT: vsub.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -710,7 +707,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -722,7 +719,7 @@ ; CHECK-LABEL: vsub_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v20 +; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -735,11 +732,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vsub.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vsub.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -752,7 +749,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -763,9 +760,8 @@ define @vsub_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vsub_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -775,14 +771,14 @@ ; CHECK-LABEL: vsub_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vsub.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -795,7 +791,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vsub_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vsub_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -28,7 +28,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -40,7 +40,7 @@ ; CHECK-LABEL: vsub_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -50,7 +50,7 @@ ; CHECK-LABEL: vsub_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -63,7 +63,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -75,7 +75,7 @@ ; CHECK-LABEL: vsub_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -85,7 +85,7 @@ ; CHECK-LABEL: vsub_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -110,7 +110,7 @@ ; CHECK-LABEL: vsub_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -120,7 +120,7 @@ ; CHECK-LABEL: vsub_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -133,7 +133,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vsub_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v18 +; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -155,7 +155,7 @@ ; CHECK-LABEL: vsub_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -168,7 +168,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -180,7 +180,7 @@ ; CHECK-LABEL: vsub_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v20 +; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -190,7 +190,7 @@ ; CHECK-LABEL: vsub_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -203,7 +203,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -214,9 +214,8 @@ define @vsub_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vsub_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -226,7 +225,7 @@ ; CHECK-LABEL: vsub_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -239,7 +238,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -251,7 +250,7 @@ ; CHECK-LABEL: vsub_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -261,7 +260,7 @@ ; CHECK-LABEL: vsub_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -274,7 +273,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -286,7 +285,7 @@ ; CHECK-LABEL: vsub_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -296,7 +295,7 @@ ; CHECK-LABEL: vsub_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -309,7 +308,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -321,7 +320,7 @@ ; CHECK-LABEL: vsub_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -331,7 +330,7 @@ ; CHECK-LABEL: vsub_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -344,7 +343,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -356,7 +355,7 @@ ; CHECK-LABEL: vsub_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v18 +; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -366,7 +365,7 @@ ; CHECK-LABEL: vsub_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -379,7 +378,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -391,7 +390,7 @@ ; CHECK-LABEL: vsub_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v20 +; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -401,7 +400,7 @@ ; CHECK-LABEL: vsub_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -414,7 +413,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -425,9 +424,8 @@ define @vsub_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vsub_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -437,7 +435,7 @@ ; CHECK-LABEL: vsub_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -450,7 +448,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -462,7 +460,7 @@ ; CHECK-LABEL: vsub_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -472,7 +470,7 @@ ; CHECK-LABEL: vsub_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -485,7 +483,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -497,7 +495,7 @@ ; CHECK-LABEL: vsub_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -507,7 +505,7 @@ ; CHECK-LABEL: vsub_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -520,7 +518,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -532,7 +530,7 @@ ; CHECK-LABEL: vsub_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v18 +; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -542,7 +540,7 @@ ; CHECK-LABEL: vsub_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -555,7 +553,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -567,7 +565,7 @@ ; CHECK-LABEL: vsub_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v20 +; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -577,7 +575,7 @@ ; CHECK-LABEL: vsub_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -590,7 +588,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -601,9 +599,8 @@ define @vsub_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vsub_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -613,7 +610,7 @@ ; CHECK-LABEL: vsub_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -626,7 +623,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -638,7 +635,7 @@ ; CHECK-LABEL: vsub_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v17 +; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -648,7 +645,7 @@ ; CHECK-LABEL: vsub_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -661,7 +658,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -673,7 +670,7 @@ ; CHECK-LABEL: vsub_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v18 +; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -683,7 +680,7 @@ ; CHECK-LABEL: vsub_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -696,7 +693,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -708,7 +705,7 @@ ; CHECK-LABEL: vsub_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vsub.vv v16, v16, v20 +; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -718,7 +715,7 @@ ; CHECK-LABEL: vsub_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -731,7 +728,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -742,9 +739,8 @@ define @vsub_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vsub_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsub.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = sub %va, %vb ret %vc @@ -754,7 +750,7 @@ ; CHECK-LABEL: vsub_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -767,7 +763,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 1 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vsub.vx v16, v16, a0 +; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 1, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i32( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i32( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i8.nxv2i32( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i32( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i8.nxv4i32( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i32( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i8.nxv8i32( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i32( @@ -194,10 +194,8 @@ define void @intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i8.nxv16i32( @@ -219,10 +217,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i8.nxv16i32( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i16.nxv1i32( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i32( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i16.nxv2i32( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i32( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i16.nxv4i32( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i32( @@ -383,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i16.nxv8i32( @@ -406,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i32( @@ -428,10 +424,8 @@ define void @intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i16.nxv16i32( @@ -453,10 +447,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i16.nxv16i32( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i32.nxv1i32( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i32( @@ -525,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i32.nxv2i32( @@ -548,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i32( @@ -571,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i32.nxv4i32( @@ -594,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i32( @@ -617,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i32.nxv8i32( @@ -640,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i32( @@ -662,10 +654,8 @@ define void @intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i32.nxv16i32( @@ -687,10 +677,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i32.nxv16i32( @@ -713,7 +701,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f16.nxv1i32( @@ -736,7 +724,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i32( @@ -759,7 +747,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f16.nxv2i32( @@ -782,7 +770,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i32( @@ -805,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f16.nxv4i32( @@ -828,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i32( @@ -851,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f16.nxv8i32( @@ -874,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i32( @@ -896,10 +884,8 @@ define void @intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f16.nxv16i32( @@ -921,10 +907,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f16.nxv16i32( @@ -947,7 +931,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f32.nxv1i32( @@ -970,7 +954,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i32( @@ -993,7 +977,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f32.nxv2i32( @@ -1016,7 +1000,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i32( @@ -1039,7 +1023,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f32.nxv4i32( @@ -1062,7 +1046,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i32( @@ -1085,7 +1069,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f32.nxv8i32( @@ -1108,7 +1092,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i32( @@ -1130,10 +1114,8 @@ define void @intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f32.nxv16i32( @@ -1155,10 +1137,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f32.nxv16i32( @@ -1181,7 +1161,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f64.nxv1i32( @@ -1204,7 +1184,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i32( @@ -1227,7 +1207,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f64.nxv2i32( @@ -1250,7 +1230,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i32( @@ -1273,7 +1253,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f64.nxv4i32( @@ -1296,7 +1276,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i32( @@ -1318,10 +1298,8 @@ define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f64.nxv8i32( @@ -1343,10 +1321,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i32( @@ -1369,7 +1345,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i16( @@ -1392,7 +1368,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i16( @@ -1415,7 +1391,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i8.nxv2i16( @@ -1438,7 +1414,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i16( @@ -1461,7 +1437,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i8.nxv4i16( @@ -1484,7 +1460,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i16( @@ -1507,7 +1483,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i8.nxv8i16( @@ -1530,7 +1506,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i16( @@ -1553,7 +1529,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i8.nxv16i16( @@ -1576,7 +1552,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i8.nxv16i16( @@ -1598,10 +1574,8 @@ define void @intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32i8.nxv32i16( @@ -1623,10 +1597,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32i8.nxv32i16( @@ -1649,7 +1621,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i16.nxv1i16( @@ -1672,7 +1644,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i16( @@ -1695,7 +1667,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i16.nxv2i16( @@ -1718,7 +1690,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i16( @@ -1741,7 +1713,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i16.nxv4i16( @@ -1764,7 +1736,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i16( @@ -1787,7 +1759,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i16.nxv8i16( @@ -1810,7 +1782,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i16( @@ -1833,7 +1805,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i16.nxv16i16( @@ -1856,7 +1828,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i16.nxv16i16( @@ -1878,10 +1850,8 @@ define void @intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32i16.nxv32i16( @@ -1903,10 +1873,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32i16.nxv32i16( @@ -1929,7 +1897,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i32.nxv1i16( @@ -1952,7 +1920,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16( @@ -1975,7 +1943,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i32.nxv2i16( @@ -1998,7 +1966,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i16( @@ -2021,7 +1989,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i32.nxv4i16( @@ -2044,7 +2012,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i16( @@ -2067,7 +2035,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i32.nxv8i16( @@ -2090,7 +2058,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i16( @@ -2112,10 +2080,8 @@ define void @intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i32.nxv16i16( @@ -2137,10 +2103,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i32.nxv16i16( @@ -2163,7 +2127,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f16.nxv1i16( @@ -2186,7 +2150,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i16( @@ -2209,7 +2173,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f16.nxv2i16( @@ -2232,7 +2196,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i16( @@ -2255,7 +2219,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f16.nxv4i16( @@ -2278,7 +2242,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i16( @@ -2301,7 +2265,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f16.nxv8i16( @@ -2324,7 +2288,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i16( @@ -2347,7 +2311,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f16.nxv16i16( @@ -2370,7 +2334,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f16.nxv16i16( @@ -2392,10 +2356,8 @@ define void @intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32f16.nxv32i16( @@ -2417,10 +2379,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32f16.nxv32i16( @@ -2443,7 +2403,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f32.nxv1i16( @@ -2466,7 +2426,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i16( @@ -2489,7 +2449,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f32.nxv2i16( @@ -2512,7 +2472,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i16( @@ -2535,7 +2495,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f32.nxv4i16( @@ -2558,7 +2518,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i16( @@ -2581,7 +2541,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f32.nxv8i16( @@ -2604,7 +2564,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i16( @@ -2626,10 +2586,8 @@ define void @intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f32.nxv16i16( @@ -2651,10 +2609,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f32.nxv16i16( @@ -2677,7 +2633,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f64.nxv1i16( @@ -2700,7 +2656,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i16( @@ -2723,7 +2679,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f64.nxv2i16( @@ -2746,7 +2702,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i16( @@ -2769,7 +2725,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f64.nxv4i16( @@ -2792,7 +2748,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i16( @@ -2814,10 +2770,8 @@ define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f64.nxv8i16( @@ -2839,10 +2793,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i16( @@ -2865,7 +2817,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i8( @@ -2888,7 +2840,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i8( @@ -2911,7 +2863,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i8.nxv2i8( @@ -2934,7 +2886,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i8( @@ -2957,7 +2909,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i8.nxv4i8( @@ -2980,7 +2932,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i8( @@ -3003,7 +2955,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i8.nxv8i8( @@ -3026,7 +2978,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i8( @@ -3049,7 +3001,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i8.nxv16i8( @@ -3072,7 +3024,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i8.nxv16i8( @@ -3095,7 +3047,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32i8.nxv32i8( @@ -3118,7 +3070,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32i8.nxv32i8( @@ -3140,10 +3092,8 @@ define void @intrinsic_vsuxei_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv64i8.nxv64i8( @@ -3165,10 +3115,8 @@ define void @intrinsic_vsuxei_mask_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv64i8.nxv64i8( @@ -3191,7 +3139,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i16.nxv1i8( @@ -3214,7 +3162,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i8( @@ -3237,7 +3185,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i16.nxv2i8( @@ -3260,7 +3208,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i8( @@ -3283,7 +3231,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i16.nxv4i8( @@ -3306,7 +3254,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i8( @@ -3329,7 +3277,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i16.nxv8i8( @@ -3352,7 +3300,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i8( @@ -3375,7 +3323,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i16.nxv16i8( @@ -3398,7 +3346,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i16.nxv16i8( @@ -3420,10 +3368,8 @@ define void @intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32i16.nxv32i8( @@ -3445,10 +3391,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32i16.nxv32i8( @@ -3471,7 +3415,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i32.nxv1i8( @@ -3494,7 +3438,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i8( @@ -3517,7 +3461,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i32.nxv2i8( @@ -3540,7 +3484,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i8( @@ -3563,7 +3507,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i32.nxv4i8( @@ -3586,7 +3530,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i8( @@ -3609,7 +3553,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i32.nxv8i8( @@ -3632,7 +3576,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i8( @@ -3654,10 +3598,8 @@ define void @intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i32.nxv16i8( @@ -3679,10 +3621,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i32.nxv16i8( @@ -3705,7 +3645,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f16.nxv1i8( @@ -3728,7 +3668,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i8( @@ -3751,7 +3691,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f16.nxv2i8( @@ -3774,7 +3714,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i8( @@ -3797,7 +3737,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f16.nxv4i8( @@ -3820,7 +3760,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i8( @@ -3843,7 +3783,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f16.nxv8i8( @@ -3866,7 +3806,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i8( @@ -3889,7 +3829,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f16.nxv16i8( @@ -3912,7 +3852,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f16.nxv16i8( @@ -3934,10 +3874,8 @@ define void @intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32f16.nxv32i8( @@ -3959,10 +3897,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32f16.nxv32i8( @@ -3985,7 +3921,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f32.nxv1i8( @@ -4008,7 +3944,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i8( @@ -4031,7 +3967,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f32.nxv2i8( @@ -4054,7 +3990,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i8( @@ -4077,7 +4013,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f32.nxv4i8( @@ -4100,7 +4036,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i8( @@ -4123,7 +4059,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f32.nxv8i8( @@ -4146,7 +4082,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i8( @@ -4168,10 +4104,8 @@ define void @intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f32.nxv16i8( @@ -4193,10 +4127,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f32.nxv16i8( @@ -4219,7 +4151,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f64.nxv1i8( @@ -4242,7 +4174,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i8( @@ -4265,7 +4197,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f64.nxv2i8( @@ -4288,7 +4220,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i8( @@ -4311,7 +4243,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f64.nxv4i8( @@ -4334,7 +4266,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i8( @@ -4356,10 +4288,8 @@ define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v25 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f64.nxv8i8( @@ -4381,10 +4311,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v25, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17 +; CHECK-NEXT: vsuxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i64( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i64( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18 +; CHECK-NEXT: vsuxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i8.nxv2i64( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i64( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20 +; CHECK-NEXT: vsuxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i8.nxv4i64( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i64( @@ -148,10 +148,8 @@ define void @intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i8.nxv8i64( @@ -173,10 +171,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i64( @@ -199,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17 +; CHECK-NEXT: vsuxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i16.nxv1i64( @@ -222,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i64( @@ -245,7 +241,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18 +; CHECK-NEXT: vsuxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i16.nxv2i64( @@ -268,7 +264,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i64( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20 +; CHECK-NEXT: vsuxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i16.nxv4i64( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i64( @@ -336,10 +332,8 @@ define void @intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i16.nxv8i64( @@ -361,10 +355,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i64( @@ -387,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17 +; CHECK-NEXT: vsuxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i32.nxv1i64( @@ -410,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i64( @@ -433,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18 +; CHECK-NEXT: vsuxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i32.nxv2i64( @@ -456,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i64( @@ -479,7 +471,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20 +; CHECK-NEXT: vsuxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i32.nxv4i64( @@ -502,7 +494,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i64( @@ -524,10 +516,8 @@ define void @intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i32.nxv8i64( @@ -549,10 +539,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i64( @@ -575,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17 +; CHECK-NEXT: vsuxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i64.nxv1i64( @@ -598,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i64( @@ -621,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18 +; CHECK-NEXT: vsuxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i64.nxv2i64( @@ -644,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i64.nxv2i64( @@ -667,7 +655,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20 +; CHECK-NEXT: vsuxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i64.nxv4i64( @@ -690,7 +678,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i64.nxv4i64( @@ -712,10 +700,8 @@ define void @intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i64.nxv8i64( @@ -737,10 +723,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i64.nxv8i64( @@ -763,7 +747,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17 +; CHECK-NEXT: vsuxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f16.nxv1i64( @@ -786,7 +770,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i64( @@ -809,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18 +; CHECK-NEXT: vsuxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f16.nxv2i64( @@ -832,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i64( @@ -855,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20 +; CHECK-NEXT: vsuxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f16.nxv4i64( @@ -878,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i64( @@ -900,10 +884,8 @@ define void @intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f16.nxv8i64( @@ -925,10 +907,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i64( @@ -951,7 +931,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17 +; CHECK-NEXT: vsuxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f32.nxv1i64( @@ -974,7 +954,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i64( @@ -997,7 +977,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18 +; CHECK-NEXT: vsuxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f32.nxv2i64( @@ -1020,7 +1000,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i64( @@ -1043,7 +1023,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20 +; CHECK-NEXT: vsuxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f32.nxv4i64( @@ -1066,7 +1046,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i64( @@ -1088,10 +1068,8 @@ define void @intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f32.nxv8i64( @@ -1113,10 +1091,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i64( @@ -1139,7 +1115,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17 +; CHECK-NEXT: vsuxei64.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f64.nxv1i64( @@ -1162,7 +1138,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i64( @@ -1185,7 +1161,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18 +; CHECK-NEXT: vsuxei64.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f64.nxv2i64( @@ -1208,7 +1184,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i64( @@ -1231,7 +1207,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20 +; CHECK-NEXT: vsuxei64.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f64.nxv4i64( @@ -1254,7 +1230,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei64.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i64( @@ -1276,10 +1252,8 @@ define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i64( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f64.nxv8i64( @@ -1301,10 +1275,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i64( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei64.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei64.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i64( @@ -1327,7 +1299,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i32( @@ -1350,7 +1322,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i32( @@ -1373,7 +1345,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i8.nxv2i32( @@ -1396,7 +1368,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i32( @@ -1419,7 +1391,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i8.nxv4i32( @@ -1442,7 +1414,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i32( @@ -1465,7 +1437,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i8.nxv8i32( @@ -1488,7 +1460,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i32( @@ -1510,10 +1482,8 @@ define void @intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i8.nxv16i32( @@ -1535,10 +1505,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i8.nxv16i32( @@ -1561,7 +1529,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i16.nxv1i32( @@ -1584,7 +1552,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i32( @@ -1607,7 +1575,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i16.nxv2i32( @@ -1630,7 +1598,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i32( @@ -1653,7 +1621,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i16.nxv4i32( @@ -1676,7 +1644,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i32( @@ -1699,7 +1667,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i16.nxv8i32( @@ -1722,7 +1690,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i32( @@ -1744,10 +1712,8 @@ define void @intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i16.nxv16i32( @@ -1769,10 +1735,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i16.nxv16i32( @@ -1795,7 +1759,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i32.nxv1i32( @@ -1818,7 +1782,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i32( @@ -1841,7 +1805,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i32.nxv2i32( @@ -1864,7 +1828,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i32( @@ -1887,7 +1851,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i32.nxv4i32( @@ -1910,7 +1874,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i32( @@ -1933,7 +1897,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i32.nxv8i32( @@ -1956,7 +1920,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i32( @@ -1978,10 +1942,8 @@ define void @intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i32.nxv16i32( @@ -2003,10 +1965,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i32.nxv16i32( @@ -2029,7 +1989,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i64.nxv1i32( @@ -2052,7 +2012,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i32( @@ -2075,7 +2035,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i64.nxv2i32( @@ -2098,7 +2058,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i64.nxv2i32( @@ -2121,7 +2081,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i64.nxv4i32( @@ -2144,7 +2104,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i64.nxv4i32( @@ -2166,10 +2126,8 @@ define void @intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i64.nxv8i32( @@ -2191,10 +2149,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i64.nxv8i32( @@ -2217,7 +2173,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f16.nxv1i32( @@ -2240,7 +2196,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i32( @@ -2263,7 +2219,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f16.nxv2i32( @@ -2286,7 +2242,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i32( @@ -2309,7 +2265,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f16.nxv4i32( @@ -2332,7 +2288,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i32( @@ -2355,7 +2311,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f16.nxv8i32( @@ -2378,7 +2334,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i32( @@ -2400,10 +2356,8 @@ define void @intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f16.nxv16i32( @@ -2425,10 +2379,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f16.nxv16i32( @@ -2451,7 +2403,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f32.nxv1i32( @@ -2474,7 +2426,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i32( @@ -2497,7 +2449,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f32.nxv2i32( @@ -2520,7 +2472,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i32( @@ -2543,7 +2495,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f32.nxv4i32( @@ -2566,7 +2518,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i32( @@ -2589,7 +2541,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f32.nxv8i32( @@ -2612,7 +2564,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i32( @@ -2634,10 +2586,8 @@ define void @intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f32.nxv16i32( @@ -2659,10 +2609,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f32.nxv16i32( @@ -2685,7 +2633,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17 +; CHECK-NEXT: vsuxei32.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f64.nxv1i32( @@ -2708,7 +2656,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i32( @@ -2731,7 +2679,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18 +; CHECK-NEXT: vsuxei32.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f64.nxv2i32( @@ -2754,7 +2702,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i32( @@ -2777,7 +2725,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20 +; CHECK-NEXT: vsuxei32.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f64.nxv4i32( @@ -2800,7 +2748,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i32( @@ -2822,10 +2770,8 @@ define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f64.nxv8i32( @@ -2847,10 +2793,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i32( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei32.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i32( @@ -2873,7 +2817,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i16( @@ -2896,7 +2840,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i16( @@ -2919,7 +2863,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i8.nxv2i16( @@ -2942,7 +2886,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i16( @@ -2965,7 +2909,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i8.nxv4i16( @@ -2988,7 +2932,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i16( @@ -3011,7 +2955,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i8.nxv8i16( @@ -3034,7 +2978,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i16( @@ -3057,7 +3001,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i8.nxv16i16( @@ -3080,7 +3024,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i8.nxv16i16( @@ -3102,10 +3046,8 @@ define void @intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32i8.nxv32i16( @@ -3127,10 +3069,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32i8.nxv32i16( @@ -3153,7 +3093,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i16.nxv1i16( @@ -3176,7 +3116,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i16( @@ -3199,7 +3139,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i16.nxv2i16( @@ -3222,7 +3162,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i16( @@ -3245,7 +3185,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i16.nxv4i16( @@ -3268,7 +3208,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i16( @@ -3291,7 +3231,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i16.nxv8i16( @@ -3314,7 +3254,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i16( @@ -3337,7 +3277,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i16.nxv16i16( @@ -3360,7 +3300,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i16.nxv16i16( @@ -3382,10 +3322,8 @@ define void @intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32i16.nxv32i16( @@ -3407,10 +3345,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32i16.nxv32i16( @@ -3433,7 +3369,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i32.nxv1i16( @@ -3456,7 +3392,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16( @@ -3479,7 +3415,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i32.nxv2i16( @@ -3502,7 +3438,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i16( @@ -3525,7 +3461,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i32.nxv4i16( @@ -3548,7 +3484,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i16( @@ -3571,7 +3507,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i32.nxv8i16( @@ -3594,7 +3530,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i16( @@ -3616,10 +3552,8 @@ define void @intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i32.nxv16i16( @@ -3641,10 +3575,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i32.nxv16i16( @@ -3667,7 +3599,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i64.nxv1i16( @@ -3690,7 +3622,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i16( @@ -3713,7 +3645,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i64.nxv2i16( @@ -3736,7 +3668,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i64.nxv2i16( @@ -3759,7 +3691,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i64.nxv4i16( @@ -3782,7 +3714,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i64.nxv4i16( @@ -3804,10 +3736,8 @@ define void @intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i64.nxv8i16( @@ -3829,10 +3759,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i64.nxv8i16( @@ -3855,7 +3783,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f16.nxv1i16( @@ -3878,7 +3806,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i16( @@ -3901,7 +3829,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f16.nxv2i16( @@ -3924,7 +3852,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i16( @@ -3947,7 +3875,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f16.nxv4i16( @@ -3970,7 +3898,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i16( @@ -3993,7 +3921,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f16.nxv8i16( @@ -4016,7 +3944,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i16( @@ -4039,7 +3967,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f16.nxv16i16( @@ -4062,7 +3990,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f16.nxv16i16( @@ -4084,10 +4012,8 @@ define void @intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32f16.nxv32i16( @@ -4109,10 +4035,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32f16.nxv32i16( @@ -4135,7 +4059,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f32.nxv1i16( @@ -4158,7 +4082,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i16( @@ -4181,7 +4105,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f32.nxv2i16( @@ -4204,7 +4128,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i16( @@ -4227,7 +4151,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f32.nxv4i16( @@ -4250,7 +4174,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i16( @@ -4273,7 +4197,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f32.nxv8i16( @@ -4296,7 +4220,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i16( @@ -4318,10 +4242,8 @@ define void @intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f32.nxv16i16( @@ -4343,10 +4265,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f32.nxv16i16( @@ -4369,7 +4289,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17 +; CHECK-NEXT: vsuxei16.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f64.nxv1i16( @@ -4392,7 +4312,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i16( @@ -4415,7 +4335,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18 +; CHECK-NEXT: vsuxei16.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f64.nxv2i16( @@ -4438,7 +4358,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i16( @@ -4461,7 +4381,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20 +; CHECK-NEXT: vsuxei16.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f64.nxv4i16( @@ -4484,7 +4404,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i16( @@ -4506,10 +4426,8 @@ define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f64.nxv8i16( @@ -4531,10 +4449,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i16( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei16.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i16( @@ -4557,7 +4473,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i8.nxv1i8( @@ -4580,7 +4496,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i8( @@ -4603,7 +4519,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i8.nxv2i8( @@ -4626,7 +4542,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i8( @@ -4649,7 +4565,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i8.nxv4i8( @@ -4672,7 +4588,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i8( @@ -4695,7 +4611,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i8.nxv8i8( @@ -4718,7 +4634,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i8( @@ -4741,7 +4657,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i8.nxv16i8( @@ -4764,7 +4680,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i8.nxv16i8( @@ -4787,7 +4703,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32i8.nxv32i8( @@ -4810,7 +4726,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32i8.nxv32i8( @@ -4832,10 +4748,8 @@ define void @intrinsic_vsuxei_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v8 +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv64i8.nxv64i8( @@ -4857,10 +4771,8 @@ define void @intrinsic_vsuxei_mask_v_nxv64i8_nxv64i8_nxv64i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v8, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv64i8.nxv64i8( @@ -4883,7 +4795,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i16.nxv1i8( @@ -4906,7 +4818,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i8( @@ -4929,7 +4841,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i16.nxv2i8( @@ -4952,7 +4864,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i8( @@ -4975,7 +4887,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i16.nxv4i8( @@ -4998,7 +4910,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i8( @@ -5021,7 +4933,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i16.nxv8i8( @@ -5044,7 +4956,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i8( @@ -5067,7 +4979,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i16.nxv16i8( @@ -5090,7 +5002,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i16.nxv16i8( @@ -5112,10 +5024,8 @@ define void @intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32i16.nxv32i8( @@ -5137,10 +5047,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32i16.nxv32i8( @@ -5163,7 +5071,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i32.nxv1i8( @@ -5186,7 +5094,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i8( @@ -5209,7 +5117,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i32.nxv2i8( @@ -5232,7 +5140,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i8( @@ -5255,7 +5163,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i32.nxv4i8( @@ -5278,7 +5186,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i8( @@ -5301,7 +5209,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i32.nxv8i8( @@ -5324,7 +5232,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i8( @@ -5346,10 +5254,8 @@ define void @intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16i32.nxv16i8( @@ -5371,10 +5277,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16i32.nxv16i8( @@ -5397,7 +5301,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1i64.nxv1i8( @@ -5420,7 +5324,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i8( @@ -5443,7 +5347,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2i64.nxv2i8( @@ -5466,7 +5370,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2i64.nxv2i8( @@ -5489,7 +5393,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4i64.nxv4i8( @@ -5512,7 +5416,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4i64.nxv4i8( @@ -5534,10 +5438,8 @@ define void @intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v25 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8i64.nxv8i8( @@ -5559,10 +5461,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v25, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8i64.nxv8i8( @@ -5585,7 +5485,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f16.nxv1i8( @@ -5608,7 +5508,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i8( @@ -5631,7 +5531,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f16.nxv2i8( @@ -5654,7 +5554,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i8( @@ -5677,7 +5577,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f16.nxv4i8( @@ -5700,7 +5600,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i8( @@ -5723,7 +5623,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f16.nxv8i8( @@ -5746,7 +5646,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i8( @@ -5769,7 +5669,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f16.nxv16i8( @@ -5792,7 +5692,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f16.nxv16i8( @@ -5814,10 +5714,8 @@ define void @intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv32f16.nxv32i8( @@ -5839,10 +5737,8 @@ define void @intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv32f16.nxv32i8( @@ -5865,7 +5761,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f32.nxv1i8( @@ -5888,7 +5784,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i8( @@ -5911,7 +5807,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f32.nxv2i8( @@ -5934,7 +5830,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i8( @@ -5957,7 +5853,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f32.nxv4i8( @@ -5980,7 +5876,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i8( @@ -6003,7 +5899,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f32.nxv8i8( @@ -6026,7 +5922,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i8( @@ -6048,10 +5944,8 @@ define void @intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v26 +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv16f32.nxv16i8( @@ -6073,10 +5967,8 @@ define void @intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v26, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv16f32.nxv16i8( @@ -6099,7 +5991,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17 +; CHECK-NEXT: vsuxei8.v v8, (a0), v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv1f64.nxv1i8( @@ -6122,7 +6014,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v17, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i8( @@ -6145,7 +6037,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18 +; CHECK-NEXT: vsuxei8.v v8, (a0), v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv2f64.nxv2i8( @@ -6168,7 +6060,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v18, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i8( @@ -6191,7 +6083,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20 +; CHECK-NEXT: vsuxei8.v v8, (a0), v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv4f64.nxv4i8( @@ -6214,7 +6106,7 @@ ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v20, v0.t +; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i8( @@ -6236,10 +6128,8 @@ define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v25 +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.nxv8f64.nxv8i8( @@ -6261,10 +6151,8 @@ define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i8( %0, * %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a1) -; CHECK-NEXT: vsetvli a1, a2, e64,m8,ta,mu -; CHECK-NEXT: vsuxei8.v v16, (a0), v25, v0.t +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll @@ -5,8 +5,8 @@ ; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -16,8 +16,8 @@ ; CHECK-LABEL: vtrunc_nxv2i16_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -27,8 +27,8 @@ ; CHECK-LABEL: vtrunc_nxv4i16_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -38,8 +38,8 @@ ; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -49,8 +49,8 @@ ; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -60,9 +60,9 @@ ; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -72,8 +72,8 @@ ; CHECK-LABEL: vtrunc_nxv1i32_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -83,9 +83,9 @@ ; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -95,8 +95,8 @@ ; CHECK-LABEL: vtrunc_nxv2i32_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -106,9 +106,9 @@ ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -118,8 +118,8 @@ ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -129,9 +129,9 @@ ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -141,8 +141,8 @@ ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -152,9 +152,9 @@ ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v28, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -164,8 +164,8 @@ ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -175,11 +175,11 @@ ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vnsrl.wi v26, v25, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -189,9 +189,9 @@ ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -201,8 +201,8 @@ ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -212,11 +212,11 @@ ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vnsrl.wi v26, v25, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -226,9 +226,9 @@ ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -238,8 +238,8 @@ ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -249,11 +249,11 @@ ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vnsrl.wi v25, v26, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -263,9 +263,9 @@ ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -275,8 +275,8 @@ ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -286,11 +286,11 @@ ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vnsrl.wi v26, v28, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -300,9 +300,9 @@ ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v28, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -312,8 +312,8 @@ ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec diff --git a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll @@ -5,8 +5,8 @@ ; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -16,8 +16,8 @@ ; CHECK-LABEL: vtrunc_nxv2i16_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -27,8 +27,8 @@ ; CHECK-LABEL: vtrunc_nxv4i16_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -38,8 +38,8 @@ ; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -49,8 +49,8 @@ ; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -60,9 +60,9 @@ ; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -72,8 +72,8 @@ ; CHECK-LABEL: vtrunc_nxv1i32_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -83,9 +83,9 @@ ; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -95,8 +95,8 @@ ; CHECK-LABEL: vtrunc_nxv2i32_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -106,9 +106,9 @@ ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -118,8 +118,8 @@ ; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -129,9 +129,9 @@ ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -141,8 +141,8 @@ ; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -152,9 +152,9 @@ ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v28, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -164,8 +164,8 @@ ; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -175,11 +175,11 @@ ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vnsrl.wi v26, v25, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -189,9 +189,9 @@ ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -201,8 +201,8 @@ ; CHECK-LABEL: vtrunc_nxv1i64_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -212,11 +212,11 @@ ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vnsrl.wi v26, v25, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -226,9 +226,9 @@ ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -238,8 +238,8 @@ ; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v25, v16, 0 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vnsrl.wi v25, v8, 0 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -249,11 +249,11 @@ ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vnsrl.wi v25, v26, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v25, 0 +; CHECK-NEXT: vnsrl.wi v8, v25, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -263,9 +263,9 @@ ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -275,8 +275,8 @@ ; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v26, v16, 0 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vnsrl.wi v26, v8, 0 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -286,11 +286,11 @@ ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vnsrl.wi v26, v28, 0 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v26, 0 +; CHECK-NEXT: vnsrl.wi v8, v26, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -300,9 +300,9 @@ ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vnsrl.wi v16, v28, 0 +; CHECK-NEXT: vnsrl.wi v8, v28, 0 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec @@ -312,8 +312,8 @@ ; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vnsrl.wi v28, v16, 0 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vnsrl.wi v28, v8, 0 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: ret %tvec = trunc %va to ret %tvec diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwadd_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vwadd_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vwadd_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwadd.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwadd.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vwadd_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwadd.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwadd.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwadd.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vwadd_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwadd.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vwadd_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv16i32.nxv16i16.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwadd_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vwadd_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwadd.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwadd.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwadd.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwadd.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwadd.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vwadd_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwadd.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vwadd_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwadd.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwadd.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwadd.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vwadd_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwadd.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwadd.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwadd.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vwadd_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwadd.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv16i32.nxv16i16.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwadd.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv1i64.nxv1i32.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwadd.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv2i64.nxv2i32.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwadd.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv2i64.nxv2i32.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwadd.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv4i64.nxv4i32.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwadd.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv4i64.nxv4i32.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vwadd_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwadd.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.nxv8i64.nxv8i32.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vwadd_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwadd.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd_mask_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.mask.nxv8i64.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwadd.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwadd.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwadd.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,14 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu +; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +279,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +302,12 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +324,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +347,12 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +369,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwadd.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +392,12 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +414,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwadd.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +437,12 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +459,13 @@ i32); define @intrinsic_vwadd.w_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwadd.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +482,14 @@ i32); define @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +506,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i16.i8( %0, i8 %1, @@ -466,10 +529,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv1i16_nxv1i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i16.i8( %0, %1, @@ -486,10 +551,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i16.i8( %0, i8 %1, @@ -506,10 +574,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv2i16_nxv2i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i16.i8( %0, %1, @@ -526,10 +596,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i16.i8( %0, i8 %1, @@ -546,10 +619,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv4i16_nxv4i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i16.i8( %0, %1, @@ -566,10 +641,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwadd.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i16.i8( %0, i8 %1, @@ -586,10 +664,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv8i16_nxv8i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwadd.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i16.i8( %0, %1, @@ -606,10 +686,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwadd.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv16i16.i8( %0, i8 %1, @@ -626,10 +709,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv16i16_nxv16i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv16i16.i8( %0, %1, @@ -646,10 +731,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwadd.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv32i16.i8( %0, i8 %1, @@ -666,10 +754,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv32i16_nxv32i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwadd.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv32i16.i8( %0, %1, @@ -686,10 +776,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i32.i16( %0, i16 %1, @@ -706,10 +799,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv1i32_nxv1i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i32.i16( %0, %1, @@ -726,10 +821,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i32.i16( %0, i16 %1, @@ -746,10 +844,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv2i32_nxv2i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i32.i16( %0, %1, @@ -766,10 +866,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwadd.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i32.i16( %0, i16 %1, @@ -786,10 +889,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv4i32_nxv4i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwadd.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i32.i16( %0, %1, @@ -806,10 +911,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwadd.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i32.i16( %0, i16 %1, @@ -826,10 +934,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv8i32_nxv8i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i32.i16( %0, %1, @@ -846,10 +956,13 @@ i32); define @intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwadd.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv16i32.i16( %0, i16 %1, @@ -866,10 +979,12 @@ i32); define @intrinsic_vwadd.w_mask_wx_nxv16i32_nxv16i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwadd.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv16i32.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwadd.w.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwadd.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwadd.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwadd.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,14 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu +; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +279,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +302,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +324,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +347,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +369,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwadd.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +392,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +414,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwadd.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +437,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +459,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwadd.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +482,14 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +506,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwadd.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i64_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i64.nxv1i32( %0, %1, @@ -466,10 +529,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i64_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i64.nxv1i32( %0, %1, @@ -486,10 +551,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwadd.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i64_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i64.nxv2i32( %0, %1, @@ -506,10 +574,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwadd.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i64_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i64.nxv2i32( %0, %1, @@ -526,10 +596,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwadd.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i64_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i64.nxv4i32( %0, %1, @@ -546,10 +619,12 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwadd.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i64_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i64.nxv4i32( %0, %1, @@ -566,10 +641,13 @@ i64); define @intrinsic_vwadd.w_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwadd.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i64_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i64.nxv8i32( %0, %1, @@ -586,10 +664,14 @@ i64); define @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vwadd.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwadd.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32( %0, %1, @@ -606,10 +688,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i16.i8( %0, i8 %1, @@ -626,10 +711,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv1i16_nxv1i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i16.i8( %0, %1, @@ -646,10 +733,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i16.i8( %0, i8 %1, @@ -666,10 +756,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv2i16_nxv2i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i16.i8( %0, %1, @@ -686,10 +778,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i16.i8( %0, i8 %1, @@ -706,10 +801,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv4i16_nxv4i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i16.i8( %0, %1, @@ -726,10 +823,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwadd.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i16.i8( %0, i8 %1, @@ -746,10 +846,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv8i16_nxv8i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwadd.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i16.i8( %0, %1, @@ -766,10 +868,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwadd.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv16i16.i8( %0, i8 %1, @@ -786,10 +891,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv16i16_nxv16i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv16i16.i8( %0, %1, @@ -806,10 +913,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwadd.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv32i16.i8( %0, i8 %1, @@ -826,10 +936,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv32i16_nxv32i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwadd.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv32i16.i8( %0, %1, @@ -846,10 +958,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i32.i16( %0, i16 %1, @@ -866,10 +981,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv1i32_nxv1i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i32.i16( %0, %1, @@ -886,10 +1003,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i32.i16( %0, i16 %1, @@ -906,10 +1026,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv2i32_nxv2i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i32.i16( %0, %1, @@ -926,10 +1048,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwadd.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i32.i16( %0, i16 %1, @@ -946,10 +1071,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv4i32_nxv4i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwadd.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i32.i16( %0, %1, @@ -966,10 +1093,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwadd.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i32.i16( %0, i16 %1, @@ -986,10 +1116,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv8i32_nxv8i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i32.i16( %0, %1, @@ -1006,10 +1138,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwadd.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv16i32.i16( %0, i16 %1, @@ -1026,10 +1161,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv16i32_nxv16i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwadd.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv16i32.i16( %0, %1, @@ -1046,10 +1183,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwadd.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv1i64.i32( %0, i32 %1, @@ -1066,10 +1206,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv1i64_nxv1i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i64_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv1i64.i32( %0, %1, @@ -1086,10 +1228,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwadd.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv2i64.i32( %0, i32 %1, @@ -1106,10 +1251,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv2i64_nxv2i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwadd.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i64_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv2i64.i32( %0, %1, @@ -1126,10 +1273,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwadd.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv4i64.i32( %0, i32 %1, @@ -1146,10 +1296,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv4i64_nxv4i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwadd.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i64_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv4i64.i32( %0, %1, @@ -1166,10 +1318,13 @@ i64); define @intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwadd.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwadd.w.nxv8i64.i32( %0, i32 %1, @@ -1186,10 +1341,12 @@ i64); define @intrinsic_vwadd.w_mask_wx_nxv8i64_nxv8i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwadd.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i64_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwadd.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwadd.w.mask.nxv8i64.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwaddu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwaddu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwaddu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwaddu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwaddu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwaddu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vwaddu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwaddu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vwaddu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwaddu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwaddu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vwaddu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwaddu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwaddu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwaddu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vwaddu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwaddu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vwaddu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwaddu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwaddu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwaddu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwaddu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwaddu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwaddu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vwaddu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwaddu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwaddu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwaddu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwaddu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vwaddu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwaddu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vwaddu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwaddu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwaddu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwaddu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwaddu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vwaddu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwaddu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwaddu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwaddu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vwaddu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwaddu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv16i32.nxv16i16.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwaddu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwaddu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv2i64.nxv2i32.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv2i64.nxv2i32.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwaddu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv4i64.nxv4i32.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv4i64.nxv4i32.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vwaddu_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwaddu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.nxv8i64.nxv8i32.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vwaddu_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwaddu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu_mask_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwaddu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.mask.nxv8i64.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwaddu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwaddu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwaddu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,14 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +279,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +302,12 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +324,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +347,12 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +369,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwaddu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +392,12 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +414,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwaddu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +437,12 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +459,13 @@ i32); define @intrinsic_vwaddu.w_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwaddu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +482,14 @@ i32); define @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +506,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i16.i8( %0, i8 %1, @@ -466,10 +529,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv1i16_nxv1i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i16.i8( %0, %1, @@ -486,10 +551,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i16.i8( %0, i8 %1, @@ -506,10 +574,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv2i16_nxv2i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i16.i8( %0, %1, @@ -526,10 +596,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i16.i8( %0, i8 %1, @@ -546,10 +619,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv4i16_nxv4i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i16.i8( %0, %1, @@ -566,10 +641,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwaddu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i16.i8( %0, i8 %1, @@ -586,10 +664,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv8i16_nxv8i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i16.i8( %0, %1, @@ -606,10 +686,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwaddu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv16i16.i8( %0, i8 %1, @@ -626,10 +709,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv16i16_nxv16i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv16i16.i8( %0, %1, @@ -646,10 +731,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwaddu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv32i16.i8( %0, i8 %1, @@ -666,10 +754,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv32i16_nxv32i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv32i16.i8( %0, %1, @@ -686,10 +776,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i32.i16( %0, i16 %1, @@ -706,10 +799,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv1i32_nxv1i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i32.i16( %0, %1, @@ -726,10 +821,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i32.i16( %0, i16 %1, @@ -746,10 +844,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv2i32_nxv2i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i32.i16( %0, %1, @@ -766,10 +866,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwaddu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i32.i16( %0, i16 %1, @@ -786,10 +889,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv4i32_nxv4i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i32.i16( %0, %1, @@ -806,10 +911,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwaddu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i32.i16( %0, i16 %1, @@ -826,10 +934,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv8i32_nxv8i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i32.i16( %0, %1, @@ -846,10 +956,13 @@ i32); define @intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwaddu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv16i32.i16( %0, i16 %1, @@ -866,10 +979,12 @@ i32); define @intrinsic_vwaddu.w_mask_wx_nxv16i32_nxv16i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv16i32.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwaddu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwaddu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwaddu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,14 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +279,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +302,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +324,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +347,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +369,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwaddu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +392,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +414,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwaddu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +437,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +459,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwaddu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +482,14 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +506,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwaddu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv1i64_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i64.nxv1i32( %0, %1, @@ -466,10 +529,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i64.nxv1i32( %0, %1, @@ -486,10 +551,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwaddu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv2i64_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i64.nxv2i32( %0, %1, @@ -506,10 +574,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i64.nxv2i32( %0, %1, @@ -526,10 +596,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwaddu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv4i64_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i64.nxv4i32( %0, %1, @@ -546,10 +619,12 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i64.nxv4i32( %0, %1, @@ -566,10 +641,13 @@ i64); define @intrinsic_vwaddu.w_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwaddu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wv_nxv8i64_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i64.nxv8i32( %0, %1, @@ -586,10 +664,14 @@ i64); define @intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vwaddu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwaddu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i64.nxv8i32( %0, %1, @@ -606,10 +688,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i16.i8( %0, i8 %1, @@ -626,10 +711,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv1i16_nxv1i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i16.i8( %0, %1, @@ -646,10 +733,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i16.i8( %0, i8 %1, @@ -666,10 +756,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv2i16_nxv2i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i16.i8( %0, %1, @@ -686,10 +778,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i16.i8( %0, i8 %1, @@ -706,10 +801,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv4i16_nxv4i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i16.i8( %0, %1, @@ -726,10 +823,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwaddu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i16.i8( %0, i8 %1, @@ -746,10 +846,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv8i16_nxv8i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i16.i8( %0, %1, @@ -766,10 +868,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwaddu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv16i16.i8( %0, i8 %1, @@ -786,10 +891,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv16i16_nxv16i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv16i16.i8( %0, %1, @@ -806,10 +913,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwaddu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv32i16.i8( %0, i8 %1, @@ -826,10 +936,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv32i16_nxv32i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv32i16.i8( %0, %1, @@ -846,10 +958,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i32.i16( %0, i16 %1, @@ -866,10 +981,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv1i32_nxv1i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i32.i16( %0, %1, @@ -886,10 +1003,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i32.i16( %0, i16 %1, @@ -906,10 +1026,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv2i32_nxv2i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i32.i16( %0, %1, @@ -926,10 +1048,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwaddu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i32.i16( %0, i16 %1, @@ -946,10 +1071,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv4i32_nxv4i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i32.i16( %0, %1, @@ -966,10 +1093,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwaddu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i32.i16( %0, i16 %1, @@ -986,10 +1116,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv8i32_nxv8i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i32.i16( %0, %1, @@ -1006,10 +1138,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwaddu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv16i32.i16( %0, i16 %1, @@ -1026,10 +1161,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv16i32_nxv16i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv16i32.i16( %0, %1, @@ -1046,10 +1183,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwaddu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv1i64.i32( %0, i32 %1, @@ -1066,10 +1206,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv1i64_nxv1i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv1i64_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv1i64.i32( %0, %1, @@ -1086,10 +1228,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwaddu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv2i64.i32( %0, i32 %1, @@ -1106,10 +1251,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv2i64_nxv2i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv2i64_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv2i64.i32( %0, %1, @@ -1126,10 +1273,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwaddu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv4i64.i32( %0, i32 %1, @@ -1146,10 +1296,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv4i64_nxv4i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv4i64_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv4i64.i32( %0, %1, @@ -1166,10 +1318,13 @@ i64); define @intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwaddu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwaddu.w.nxv8i64.i32( %0, i32 %1, @@ -1186,10 +1341,12 @@ i64); define @intrinsic_vwaddu.w_mask_wx_nxv8i64_nxv8i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwaddu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwaddu.w_mask_wx_nxv8i64_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwaddu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwaddu.w.mask.nxv8i64.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19 +; CHECK-NEXT: vwmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22 +; CHECK-NEXT: vwmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv16i16.nxv16i8( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8( @@ -240,11 +240,8 @@ define @intrinsic_vwmacc_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv32i16.nxv32i8( @@ -266,11 +263,8 @@ define @intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i32.nxv1i16( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i32.nxv2i16( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16( @@ -385,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19 +; CHECK-NEXT: vwmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i32.nxv4i16( @@ -408,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16( @@ -431,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22 +; CHECK-NEXT: vwmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i32.nxv8i16( @@ -454,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16( @@ -476,11 +470,8 @@ define @intrinsic_vwmacc_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv16i32.nxv16i16( @@ -502,11 +493,8 @@ define @intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16( @@ -529,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i16.i8( @@ -552,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i16.i8( @@ -575,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i16.i8( @@ -598,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i16.i8( @@ -621,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i16.i8( @@ -644,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i16.i8( @@ -667,7 +655,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18 +; CHECK-NEXT: vwmacc.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i16.i8( @@ -690,7 +678,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i16.i8( @@ -713,7 +701,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20 +; CHECK-NEXT: vwmacc.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv16i16.i8( @@ -736,7 +724,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv16i16.i8( @@ -758,10 +746,8 @@ define @intrinsic_vwmacc_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv32i16.i8( @@ -783,10 +769,8 @@ define @intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv32i16.i8( @@ -809,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i32.i16( @@ -832,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i32.i16( @@ -855,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i32.i16( @@ -878,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i32.i16( @@ -901,7 +885,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18 +; CHECK-NEXT: vwmacc.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i32.i16( @@ -924,7 +908,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i32.i16( @@ -947,7 +931,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20 +; CHECK-NEXT: vwmacc.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i32.i16( @@ -970,7 +954,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i32.i16( @@ -992,10 +976,8 @@ define @intrinsic_vwmacc_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv16i32.i16( @@ -1017,10 +999,8 @@ define @intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv16i32.i16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i16.nxv1i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i16.nxv2i8( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i16.nxv4i8( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19 +; CHECK-NEXT: vwmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i16.nxv8i8( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22 +; CHECK-NEXT: vwmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv16i16.nxv16i8( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8( @@ -240,11 +240,8 @@ define @intrinsic_vwmacc_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv32i16.nxv32i8( @@ -266,11 +263,8 @@ define @intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i32.nxv1i16( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i32.nxv2i16( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16( @@ -385,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19 +; CHECK-NEXT: vwmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i32.nxv4i16( @@ -408,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16( @@ -431,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22 +; CHECK-NEXT: vwmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i32.nxv8i16( @@ -454,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16( @@ -476,11 +470,8 @@ define @intrinsic_vwmacc_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv16i32.nxv16i16( @@ -502,11 +493,8 @@ define @intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16( @@ -529,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18 +; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i64.nxv1i32( @@ -552,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32( @@ -575,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19 +; CHECK-NEXT: vwmacc.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i64.nxv2i32( @@ -598,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmacc.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32( @@ -621,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22 +; CHECK-NEXT: vwmacc.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i64.nxv4i32( @@ -644,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmacc.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32( @@ -666,11 +654,8 @@ define @intrinsic_vwmacc_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i64.nxv8i32( @@ -692,11 +677,8 @@ define @intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmacc.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwmacc.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32( @@ -719,7 +701,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i16.i8( @@ -742,7 +724,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i16.i8( @@ -765,7 +747,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i16.i8( @@ -788,7 +770,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i16.i8( @@ -811,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i16.i8( @@ -834,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i16.i8( @@ -857,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18 +; CHECK-NEXT: vwmacc.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i16.i8( @@ -880,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i16.i8( @@ -903,7 +885,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20 +; CHECK-NEXT: vwmacc.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv16i16.i8( @@ -926,7 +908,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv16i16.i8( @@ -948,10 +930,8 @@ define @intrinsic_vwmacc_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv32i16.i8( @@ -973,10 +953,8 @@ define @intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv32i16.i8( @@ -999,7 +977,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i32.i16( @@ -1022,7 +1000,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i32.i16( @@ -1045,7 +1023,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i32.i16( @@ -1068,7 +1046,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i32.i16( @@ -1091,7 +1069,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18 +; CHECK-NEXT: vwmacc.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i32.i16( @@ -1114,7 +1092,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i32.i16( @@ -1137,7 +1115,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20 +; CHECK-NEXT: vwmacc.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i32.i16( @@ -1160,7 +1138,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i32.i16( @@ -1182,10 +1160,8 @@ define @intrinsic_vwmacc_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv16i32.i16( @@ -1207,10 +1183,8 @@ define @intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv16i32.i16( @@ -1233,7 +1207,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17 +; CHECK-NEXT: vwmacc.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv1i64.i32( @@ -1256,7 +1230,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv1i64.i32( @@ -1279,7 +1253,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18 +; CHECK-NEXT: vwmacc.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv2i64.i32( @@ -1302,7 +1276,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv2i64.i32( @@ -1325,7 +1299,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20 +; CHECK-NEXT: vwmacc.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv4i64.i32( @@ -1348,7 +1322,7 @@ ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmacc.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv4i64.i32( @@ -1370,10 +1344,8 @@ define @intrinsic_vwmacc_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.nxv8i64.i32( @@ -1395,10 +1367,8 @@ define @intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmacc.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmacc.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmacc.mask.nxv8i64.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8( @@ -240,11 +240,8 @@ define @intrinsic_vwmaccsu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8( @@ -266,11 +263,8 @@ define @intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16( @@ -385,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16( @@ -408,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16( @@ -431,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16( @@ -454,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16( @@ -476,11 +470,8 @@ define @intrinsic_vwmaccsu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16( @@ -502,11 +493,8 @@ define @intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16( @@ -529,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i16.i8( @@ -552,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i16.i8( @@ -575,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i16.i8( @@ -598,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i16.i8( @@ -621,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i16.i8( @@ -644,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i16.i8( @@ -667,7 +655,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i16.i8( @@ -690,7 +678,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i16.i8( @@ -713,7 +701,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv16i16.i8( @@ -736,7 +724,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv16i16.i8( @@ -758,10 +746,8 @@ define @intrinsic_vwmaccsu_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv32i16.i8( @@ -783,10 +769,8 @@ define @intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv32i16.i8( @@ -809,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i32.i16( @@ -832,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i32.i16( @@ -855,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i32.i16( @@ -878,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i32.i16( @@ -901,7 +885,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i32.i16( @@ -924,7 +908,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i32.i16( @@ -947,7 +931,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i32.i16( @@ -970,7 +954,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i32.i16( @@ -992,10 +976,8 @@ define @intrinsic_vwmaccsu_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv16i32.i16( @@ -1017,10 +999,8 @@ define @intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv16i32.i16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8( @@ -240,11 +240,8 @@ define @intrinsic_vwmaccsu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8( @@ -266,11 +263,8 @@ define @intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16( @@ -385,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16( @@ -408,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16( @@ -431,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16( @@ -454,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16( @@ -476,11 +470,8 @@ define @intrinsic_vwmaccsu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16( @@ -502,11 +493,8 @@ define @intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16( @@ -529,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i64.nxv1i32( @@ -552,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32( @@ -575,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i64.nxv2i32( @@ -598,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32( @@ -621,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i64.nxv4i32( @@ -644,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccsu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32( @@ -666,11 +654,8 @@ define @intrinsic_vwmaccsu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i64.nxv8i32( @@ -692,11 +677,8 @@ define @intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32( @@ -719,7 +701,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i16.i8( @@ -742,7 +724,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i16.i8( @@ -765,7 +747,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i16.i8( @@ -788,7 +770,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i16.i8( @@ -811,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i16.i8( @@ -834,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i16.i8( @@ -857,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i16.i8( @@ -880,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i16.i8( @@ -903,7 +885,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv16i16.i8( @@ -926,7 +908,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv16i16.i8( @@ -948,10 +930,8 @@ define @intrinsic_vwmaccsu_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv32i16.i8( @@ -973,10 +953,8 @@ define @intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv32i16.i8( @@ -999,7 +977,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i32.i16( @@ -1022,7 +1000,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i32.i16( @@ -1045,7 +1023,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i32.i16( @@ -1068,7 +1046,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i32.i16( @@ -1091,7 +1069,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i32.i16( @@ -1114,7 +1092,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i32.i16( @@ -1137,7 +1115,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i32.i16( @@ -1160,7 +1138,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i32.i16( @@ -1182,10 +1160,8 @@ define @intrinsic_vwmaccsu_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv16i32.i16( @@ -1207,10 +1183,8 @@ define @intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv16i32.i16( @@ -1233,7 +1207,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv1i64.i32( @@ -1256,7 +1230,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv1i64.i32( @@ -1279,7 +1253,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv2i64.i32( @@ -1302,7 +1276,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv2i64.i32( @@ -1325,7 +1299,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv4i64.i32( @@ -1348,7 +1322,7 @@ ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccsu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv4i64.i32( @@ -1370,10 +1344,8 @@ define @intrinsic_vwmaccsu_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.nxv8i64.i32( @@ -1395,10 +1367,8 @@ define @intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccsu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmaccsu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccsu.mask.nxv8i64.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv16i16.nxv16i8( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8( @@ -240,11 +240,8 @@ define @intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv32i16.nxv32i8( @@ -266,11 +263,8 @@ define @intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i32.nxv1i16( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i32.nxv2i16( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16( @@ -385,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i32.nxv4i16( @@ -408,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16( @@ -431,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i32.nxv8i16( @@ -454,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16( @@ -476,11 +470,8 @@ define @intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv16i32.nxv16i16( @@ -502,11 +493,8 @@ define @intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16( @@ -529,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i16.i8( @@ -552,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i16.i8( @@ -575,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i16.i8( @@ -598,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i16.i8( @@ -621,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i16.i8( @@ -644,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i16.i8( @@ -667,7 +655,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i16.i8( @@ -690,7 +678,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i16.i8( @@ -713,7 +701,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv16i16.i8( @@ -736,7 +724,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i16.i8( @@ -758,10 +746,8 @@ define @intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv32i16.i8( @@ -783,10 +769,8 @@ define @intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv32i16.i8( @@ -809,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i32.i16( @@ -832,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i32.i16( @@ -855,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i32.i16( @@ -878,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i32.i16( @@ -901,7 +885,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i32.i16( @@ -924,7 +908,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i32.i16( @@ -947,7 +931,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i32.i16( @@ -970,7 +954,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i32.i16( @@ -992,10 +976,8 @@ define @intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv16i32.i16( @@ -1017,10 +999,8 @@ define @intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i32.i16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i16.nxv1i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i16.nxv2i8( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i16.nxv4i8( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i16.nxv8i8( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv16i16.nxv16i8( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8( @@ -240,11 +240,8 @@ define @intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv32i16.nxv32i8( @@ -266,11 +263,8 @@ define @intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8( @@ -293,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i32.nxv1i16( @@ -316,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16( @@ -339,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i32.nxv2i16( @@ -362,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16( @@ -385,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i32.nxv4i16( @@ -408,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16( @@ -431,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i32.nxv8i16( @@ -454,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16( @@ -476,11 +470,8 @@ define @intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv16i32.nxv16i16( @@ -502,11 +493,8 @@ define @intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16( @@ -529,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18 +; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i64.nxv1i32( @@ -552,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v17, v18, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v9, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32( @@ -575,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19 +; CHECK-NEXT: vwmaccu.vv v8, v10, v11 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i64.nxv2i32( @@ -598,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v18, v19, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v10, v11, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32( @@ -621,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22 +; CHECK-NEXT: vwmaccu.vv v8, v12, v14 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i64.nxv4i32( @@ -644,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v20, v22, v0.t +; CHECK-NEXT: vwmaccu.vv v8, v12, v14, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32( @@ -666,11 +654,8 @@ define @intrinsic_vwmaccu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28 +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i64.nxv8i32( @@ -692,11 +677,8 @@ define @intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetvli a0, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccu.vv v16, v8, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwmaccu.vv v8, v16, v20, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32( @@ -719,7 +701,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i16.i8( @@ -742,7 +724,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i16.i8( @@ -765,7 +747,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i16.i8( @@ -788,7 +770,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i16.i8( @@ -811,7 +793,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i16.i8( @@ -834,7 +816,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i16.i8( @@ -857,7 +839,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i16.i8( @@ -880,7 +862,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i16.i8( @@ -903,7 +885,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv16i16.i8( @@ -926,7 +908,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i16.i8( @@ -948,10 +930,8 @@ define @intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv32i16.i8( @@ -973,10 +953,8 @@ define @intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv32i16.i8( @@ -999,7 +977,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i32.i16( @@ -1022,7 +1000,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i32.i16( @@ -1045,7 +1023,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i32.i16( @@ -1068,7 +1046,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i32.i16( @@ -1091,7 +1069,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i32.i16( @@ -1114,7 +1092,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i32.i16( @@ -1137,7 +1115,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i32.i16( @@ -1160,7 +1138,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i32.i16( @@ -1182,10 +1160,8 @@ define @intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv16i32.i16( @@ -1207,10 +1183,8 @@ define @intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv16i32.i16( @@ -1233,7 +1207,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17 +; CHECK-NEXT: vwmaccu.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv1i64.i32( @@ -1256,7 +1230,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv1i64.i32( @@ -1279,7 +1253,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18 +; CHECK-NEXT: vwmaccu.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv2i64.i32( @@ -1302,7 +1276,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv2i64.i32( @@ -1325,7 +1299,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20 +; CHECK-NEXT: vwmaccu.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv4i64.i32( @@ -1348,7 +1322,7 @@ ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccu.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv4i64.i32( @@ -1370,10 +1344,8 @@ define @intrinsic_vwmaccu_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.nxv8i64.i32( @@ -1395,10 +1367,8 @@ define @intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccu.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmaccu.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccu.mask.nxv8i64.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv1i16.i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv1i16.i8( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv2i16.i8( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv2i16.i8( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv4i16.i8( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv4i16.i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18 +; CHECK-NEXT: vwmaccus.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv8i16.i8( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv8i16.i8( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20 +; CHECK-NEXT: vwmaccus.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv16i16.i8( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv16i16.i8( @@ -240,10 +240,8 @@ define @intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv32i16.i8( @@ -265,10 +263,8 @@ define @intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv32i16.i8( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv1i32.i16( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv1i32.i16( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv2i32.i16( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv2i32.i16( @@ -383,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18 +; CHECK-NEXT: vwmaccus.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv4i32.i16( @@ -406,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv4i32.i16( @@ -429,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20 +; CHECK-NEXT: vwmaccus.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv8i32.i16( @@ -452,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv8i32.i16( @@ -474,10 +470,8 @@ define @intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv16i32.i16( @@ -499,10 +493,8 @@ define @intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv16i32.i16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll @@ -11,7 +11,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv1i16.i8( @@ -34,7 +34,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv1i16.i8( @@ -57,7 +57,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv2i16.i8( @@ -80,7 +80,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv2i16.i8( @@ -103,7 +103,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv4i16.i8( @@ -126,7 +126,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv4i16.i8( @@ -149,7 +149,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18 +; CHECK-NEXT: vwmaccus.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv8i16.i8( @@ -172,7 +172,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv8i16.i8( @@ -195,7 +195,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20 +; CHECK-NEXT: vwmaccus.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv16i16.i8( @@ -218,7 +218,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv16i16.i8( @@ -240,10 +240,8 @@ define @intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv32i16.i8( @@ -265,10 +263,8 @@ define @intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8( %0, i8 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e8,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv32i16.i8( @@ -291,7 +287,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv1i32.i16( @@ -314,7 +310,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv1i32.i16( @@ -337,7 +333,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv2i32.i16( @@ -360,7 +356,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv2i32.i16( @@ -383,7 +379,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18 +; CHECK-NEXT: vwmaccus.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv4i32.i16( @@ -406,7 +402,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv4i32.i16( @@ -429,7 +425,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20 +; CHECK-NEXT: vwmaccus.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv8i32.i16( @@ -452,7 +448,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv8i32.i16( @@ -474,10 +470,8 @@ define @intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv16i32.i16( @@ -499,10 +493,8 @@ define @intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16( %0, i16 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e16,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv16i32.i16( @@ -525,7 +517,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17 +; CHECK-NEXT: vwmaccus.vx v8, a0, v9 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv1i64.i32( @@ -548,7 +540,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v17, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv1i64.i32( @@ -571,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18 +; CHECK-NEXT: vwmaccus.vx v8, a0, v10 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv2i64.i32( @@ -594,7 +586,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v18, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv2i64.i32( @@ -617,7 +609,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20 +; CHECK-NEXT: vwmaccus.vx v8, a0, v12 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv4i64.i32( @@ -640,7 +632,7 @@ ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v20, v0.t +; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv4i64.i32( @@ -662,10 +654,8 @@ define @intrinsic_vwmaccus_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28 +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.nxv8i64.i32( @@ -687,10 +677,8 @@ define @intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32( %0, i32 %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a1) -; CHECK-NEXT: vsetvli a1, a2, e32,m4,tu,mu -; CHECK-NEXT: vwmaccus.vx v16, a0, v28, v0.t +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vwmaccus.mask.nxv8i64.i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwmul.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwmul.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwmul.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwmul.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwmul.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwmul.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwmul.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwmul.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwmul.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwmul.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwmul.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwmul.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwmul.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwmul.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwmul.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwmul.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwmul.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwmul.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwmul.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwmul.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwmul.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwmul.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vwmul_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwmul.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwmul.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwmul.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwmul.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwmul.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwmul.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwmul.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwmul.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwmul.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwmul.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwmul.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmul.nxv8i64.nxv8i32.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vwmul_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwmul.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwmulsu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwmulsu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwmulsu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwmulsu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwmulsu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vwmulsu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwmulsu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vwmulsu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwmulsu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwmulsu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwmulsu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwmulsu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwmulsu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vwmulsu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwmulsu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vwmulsu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv16i32.nxv16i16.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwmulsu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwmulsu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwmulsu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwmulsu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwmulsu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwmulsu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwmulsu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwmulsu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vwmulsu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwmulsu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vwmulsu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwmulsu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwmulsu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwmulsu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwmulsu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwmulsu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwmulsu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwmulsu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwmulsu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv16i32.nxv16i16.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwmulsu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv1i64.nxv1i32.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv1i64.nxv1i32.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwmulsu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv2i64.nxv2i32.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv2i64.nxv2i32.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwmulsu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv4i64.nxv4i32.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv4i64.nxv4i32.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vwmulsu_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwmulsu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulsu.nxv8i64.nxv8i32.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vwmulsu_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmulsu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulsu_mask_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwmulsu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulsu.mask.nxv8i64.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwmulu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwmulu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwmulu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwmulu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwmulu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwmulu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vwmulu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwmulu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vwmulu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwmulu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwmulu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vwmulu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwmulu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwmulu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwmulu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vwmulu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwmulu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vwmulu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv16i32.nxv16i16.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwmulu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwmulu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwmulu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwmulu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwmulu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwmulu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vwmulu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwmulu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vwmulu_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwmulu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vwmulu_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwmulu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vwmulu_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwmulu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vwmulu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwmulu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vwmulu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwmulu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwmulu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwmulu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwmulu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vwmulu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwmulu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwmulu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwmulu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vwmulu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwmulu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv16i32.nxv16i16.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vwmulu_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwmulu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv1i64.nxv1i32.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv1i64.nxv1i32.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vwmulu_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwmulu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv2i64.nxv2i32.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv2i64.nxv2i32.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vwmulu_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwmulu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv4i64.nxv4i32.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv4i64.nxv4i32.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vwmulu_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwmulu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwmulu.nxv8i64.nxv8i32.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vwmulu_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwmulu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwmulu_mask_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwmulu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwmulu.mask.nxv8i64.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv4i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv8i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv16i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv32i16( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwredsum.nxv4i16.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv4i16.nxv64i8( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv1i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv2i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv4i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv8i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv16i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv2i32.nxv32i16( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv1i64.nxv1i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.nxv1i64( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv1i64.nxv2i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.nxv1i64( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv1i64.nxv4i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.nxv1i64( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv1i64.nxv8i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.nxv1i64( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsum.nxv1i64.nxv16i32( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.nxv1i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( @@ -7,10 +8,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16( %0, %1, @@ -49,10 +54,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16( %0, %1, @@ -91,10 +100,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16( %0, %1, @@ -133,10 +146,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16( %0, %1, @@ -175,10 +192,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16( %0, %1, @@ -217,10 +238,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16( %0, %1, @@ -259,10 +284,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8( %0, %1, @@ -280,10 +307,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16( %0, %1, @@ -301,10 +330,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16( %0, %1, @@ -322,10 +353,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32( %0, %1, @@ -343,10 +376,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16( %0, %1, @@ -364,10 +399,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32( %0, %1, @@ -385,10 +422,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv4i16( %0, %1, @@ -406,10 +445,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32( %0, %1, @@ -427,10 +468,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv8i16( %0, %1, @@ -448,10 +491,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32( %0, %1, @@ -469,10 +514,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv16i16( %0, %1, @@ -490,10 +537,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32( %0, %1, @@ -511,10 +560,12 @@ i32); define @intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv32i16( %0, %1, @@ -532,10 +583,12 @@ i32); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( @@ -7,10 +8,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( %0, %1, @@ -28,10 +31,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16( %0, %1, @@ -49,10 +54,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv2i8( %0, %1, @@ -70,10 +77,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16( %0, %1, @@ -91,10 +100,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv4i8( %0, %1, @@ -112,10 +123,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16( %0, %1, @@ -133,10 +146,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv8i8( %0, %1, @@ -154,10 +169,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16( %0, %1, @@ -175,10 +192,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv16i8( %0, %1, @@ -196,10 +215,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16( %0, %1, @@ -217,10 +238,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv32i8( %0, %1, @@ -238,10 +261,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16( %0, %1, @@ -259,10 +284,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv4i16.nxv64i8( %0, %1, @@ -280,10 +307,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16( %0, %1, @@ -301,10 +330,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv1i16( %0, %1, @@ -322,10 +353,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32( %0, %1, @@ -343,10 +376,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv2i16( %0, %1, @@ -364,10 +399,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32( %0, %1, @@ -385,10 +422,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv4i16( %0, %1, @@ -406,10 +445,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32( %0, %1, @@ -427,10 +468,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv8i16( %0, %1, @@ -448,10 +491,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32( %0, %1, @@ -469,10 +514,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv16i16( %0, %1, @@ -490,10 +537,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32( %0, %1, @@ -511,10 +560,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv2i32.nxv32i16( %0, %1, @@ -532,10 +583,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32( %0, %1, @@ -553,10 +606,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv1i64.nxv1i32( %0, %1, @@ -574,10 +629,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.nxv1i64( %0, %1, @@ -595,10 +652,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv1i64.nxv2i32( %0, %1, @@ -616,10 +675,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.nxv1i64( %0, %1, @@ -637,10 +698,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv1i64.nxv4i32( %0, %1, @@ -658,10 +721,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.nxv1i64( %0, %1, @@ -679,10 +744,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv1i64.nxv8i32( %0, %1, @@ -700,10 +767,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.nxv1i64( %0, %1, @@ -721,10 +790,12 @@ i64); define @intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwredsumu.nxv1i64.nxv16i32( %0, %1, @@ -742,10 +813,12 @@ i64); define @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vwredsumu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.nxv1i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwsub_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vwsub_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vwsub_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwsub.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwsub.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vwsub_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwsub.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwsub.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwsub.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vwsub_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwsub.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vwsub_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv16i32.nxv16i16.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwsub_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vwsub_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwsub.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwsub.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwsub.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwsub.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwsub.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vwsub_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwsub.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vwsub_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwsub.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwsub.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwsub.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vwsub_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwsub.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwsub.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwsub.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vwsub_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwsub.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv16i32.nxv16i16.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwsub.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv1i64.nxv1i32.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv1i64.nxv1i32.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwsub.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv2i64.nxv2i32.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwsub.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv2i64.nxv2i32.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwsub.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv4i64.nxv4i32.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwsub.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv4i64.nxv4i32.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vwsub_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwsub.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.nxv8i64.nxv8i32.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vwsub_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsub.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub_mask_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwsub.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.mask.nxv8i64.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwsub.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwsub.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwsub.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,14 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +279,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +302,12 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +324,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +347,12 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +369,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwsub.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +392,12 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +414,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwsub.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +437,12 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +459,13 @@ i32); define @intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwsub.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +482,14 @@ i32); define @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +506,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i16.i8( %0, i8 %1, @@ -466,10 +529,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv1i16_nxv1i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i16.i8( %0, %1, @@ -486,10 +551,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i16.i8( %0, i8 %1, @@ -506,10 +574,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv2i16_nxv2i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i16.i8( %0, %1, @@ -526,10 +596,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i16.i8( %0, i8 %1, @@ -546,10 +619,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv4i16_nxv4i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i16.i8( %0, %1, @@ -566,10 +641,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwsub.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i16.i8( %0, i8 %1, @@ -586,10 +664,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv8i16_nxv8i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwsub.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i16.i8( %0, %1, @@ -606,10 +686,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwsub.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv16i16.i8( %0, i8 %1, @@ -626,10 +709,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv16i16_nxv16i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv16i16.i8( %0, %1, @@ -646,10 +731,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwsub.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv32i16.i8( %0, i8 %1, @@ -666,10 +754,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv32i16_nxv32i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsub.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv32i16.i8( %0, %1, @@ -686,10 +776,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i32.i16( %0, i16 %1, @@ -706,10 +799,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv1i32_nxv1i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i32.i16( %0, %1, @@ -726,10 +821,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i32.i16( %0, i16 %1, @@ -746,10 +844,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv2i32_nxv2i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i32.i16( %0, %1, @@ -766,10 +866,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwsub.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i32.i16( %0, i16 %1, @@ -786,10 +889,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv4i32_nxv4i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwsub.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i32.i16( %0, %1, @@ -806,10 +911,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwsub.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i32.i16( %0, i16 %1, @@ -826,10 +934,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv8i32_nxv8i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i32.i16( %0, %1, @@ -846,10 +956,13 @@ i32); define @intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwsub.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv16i32.i16( %0, i16 %1, @@ -866,10 +979,12 @@ i32); define @intrinsic_vwsub.w_mask_wx_nxv16i32_nxv16i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsub.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv16i32.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwsub.w.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwsub.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwsub.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwsub.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,14 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +279,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +302,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +324,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +347,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +369,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwsub.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +392,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +414,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwsub.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +437,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +459,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwsub.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +482,14 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +506,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwsub.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i64_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i64.nxv1i32( %0, %1, @@ -466,10 +529,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv1i64_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i64.nxv1i32( %0, %1, @@ -486,10 +551,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwsub.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i64_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i64.nxv2i32( %0, %1, @@ -506,10 +574,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwsub.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv2i64_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i64.nxv2i32( %0, %1, @@ -526,10 +596,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwsub.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i64_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i64.nxv4i32( %0, %1, @@ -546,10 +619,12 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwsub.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv4i64_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i64.nxv4i32( %0, %1, @@ -566,10 +641,13 @@ i64); define @intrinsic_vwsub.w_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwsub.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i64_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i64.nxv8i32( %0, %1, @@ -586,10 +664,14 @@ i64); define @intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsub.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wv_nxv8i64_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwsub.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i64.nxv8i32( %0, %1, @@ -606,10 +688,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i16.i8( %0, i8 %1, @@ -626,10 +711,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv1i16_nxv1i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i16.i8( %0, %1, @@ -646,10 +733,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i16.i8( %0, i8 %1, @@ -666,10 +756,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv2i16_nxv2i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i16.i8( %0, %1, @@ -686,10 +778,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i16.i8( %0, i8 %1, @@ -706,10 +801,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv4i16_nxv4i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i16.i8( %0, %1, @@ -726,10 +823,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwsub.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i16.i8( %0, i8 %1, @@ -746,10 +846,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv8i16_nxv8i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwsub.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i16.i8( %0, %1, @@ -766,10 +868,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwsub.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv16i16.i8( %0, i8 %1, @@ -786,10 +891,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv16i16_nxv16i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv16i16.i8( %0, %1, @@ -806,10 +913,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwsub.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv32i16.i8( %0, i8 %1, @@ -826,10 +936,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv32i16_nxv32i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsub.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv32i16.i8( %0, %1, @@ -846,10 +958,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i32.i16( %0, i16 %1, @@ -866,10 +981,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv1i32_nxv1i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i32.i16( %0, %1, @@ -886,10 +1003,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i32.i16( %0, i16 %1, @@ -906,10 +1026,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv2i32_nxv2i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i32.i16( %0, %1, @@ -926,10 +1048,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwsub.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i32.i16( %0, i16 %1, @@ -946,10 +1071,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv4i32_nxv4i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwsub.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i32.i16( %0, %1, @@ -966,10 +1093,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwsub.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i32.i16( %0, i16 %1, @@ -986,10 +1116,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv8i32_nxv8i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i32.i16( %0, %1, @@ -1006,10 +1138,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwsub.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv16i32.i16( %0, i16 %1, @@ -1026,10 +1161,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv16i32_nxv16i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsub.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv16i32.i16( %0, %1, @@ -1046,10 +1183,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwsub.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv1i64.i32( %0, i32 %1, @@ -1066,10 +1206,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv1i64_nxv1i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv1i64_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv1i64.i32( %0, %1, @@ -1086,10 +1228,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwsub.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv2i64.i32( %0, i32 %1, @@ -1106,10 +1251,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv2i64_nxv2i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwsub.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv2i64_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv2i64.i32( %0, %1, @@ -1126,10 +1273,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwsub.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv4i64.i32( %0, i32 %1, @@ -1146,10 +1296,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv4i64_nxv4i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwsub.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv4i64_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv4i64.i32( %0, %1, @@ -1166,10 +1318,13 @@ i64); define @intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwsub.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsub.w.nxv8i64.i32( %0, i32 %1, @@ -1186,10 +1341,12 @@ i64); define @intrinsic_vwsub.w_mask_wx_nxv8i64_nxv8i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsub.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsub.w_mask_wx_nxv8i64_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwsub.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsub.w.mask.nxv8i64.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwsubu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwsubu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwsubu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwsubu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i32); define @intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i32); define @intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i32); define @intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwsubu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i32); define @intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwsubu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i32); define @intrinsic_vwsubu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwsubu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i32); define @intrinsic_vwsubu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i32); define @intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -466,10 +525,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -486,10 +547,13 @@ i32); define @intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -506,10 +570,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -526,10 +592,13 @@ i32); define @intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -546,10 +615,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -566,10 +637,13 @@ i32); define @intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwsubu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -586,10 +660,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -606,10 +682,13 @@ i32); define @intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwsubu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -646,10 +727,13 @@ i32); define @intrinsic_vwsubu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwsubu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -686,10 +772,13 @@ i32); define @intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -706,10 +795,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -726,10 +817,13 @@ i32); define @intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -746,10 +840,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -766,10 +862,13 @@ i32); define @intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwsubu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -786,10 +885,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -806,10 +907,13 @@ i32); define @intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwsubu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -826,10 +930,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -846,10 +952,13 @@ i32); define @intrinsic_vwsubu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwsubu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i32); define @intrinsic_vwsubu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv16i32.nxv16i16.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv1i16_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i16_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i16_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i16.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv2i16_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i16_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i16_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i16.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv4i16_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i16_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i16_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i16.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwsubu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv8i16_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i16_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i16_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i16.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwsubu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv16i16_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i16_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i16_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv16i16.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwsubu_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwsubu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +255,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv32i16_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv32i16_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv32i16_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv32i16.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +277,13 @@ i64); define @intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -266,10 +300,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv1i32_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i32_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i32_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i32.nxv1i16.nxv1i16( %0, %1, @@ -286,10 +322,13 @@ i64); define @intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -306,10 +345,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv2i32_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i32_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i32.nxv2i16.nxv2i16( %0, %1, @@ -326,10 +367,13 @@ i64); define @intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwsubu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -346,10 +390,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv4i32_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i32_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i32_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i32.nxv4i16.nxv4i16( %0, %1, @@ -366,10 +412,13 @@ i64); define @intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwsubu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -386,10 +435,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv8i32_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i32_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i32_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i32.nxv8i16.nxv8i16( %0, %1, @@ -406,10 +457,13 @@ i64); define @intrinsic_vwsubu_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwsubu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -426,10 +480,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv16i32_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i32_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv16i32_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv16i32.nxv16i16.nxv16i16( %0, %1, @@ -446,10 +502,13 @@ i64); define @intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwsubu.vv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -466,10 +525,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv1i64_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i64_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv1i64_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i64.nxv1i32.nxv1i32( %0, %1, @@ -486,10 +547,13 @@ i64); define @intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwsubu.vv v26, v8, v9 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -506,10 +570,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv2i64_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i64_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v10, v11, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv2i64_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i64.nxv2i32.nxv2i32( %0, %1, @@ -526,10 +592,13 @@ i64); define @intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwsubu.vv v28, v8, v10 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -546,10 +615,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv4i64_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i64_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v12, v14, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv4i64_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i64.nxv4i32.nxv4i32( %0, %1, @@ -566,10 +637,13 @@ i64); define @intrinsic_vwsubu_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwsubu.vv v16, v8, v12 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -586,10 +660,12 @@ i64); define @intrinsic_vwsubu_mask_vv_nxv8i64_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i64_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vwsubu.vv v8, v16, v20, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vv_nxv8i64_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwsubu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i64.nxv8i32.nxv8i32( %0, %1, @@ -606,10 +682,13 @@ i64); define @intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i16.nxv1i8.i8( %0, i8 %1, @@ -626,10 +705,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv1i16_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i16_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i16_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i16.nxv1i8.i8( %0, %1, @@ -646,10 +727,13 @@ i64); define @intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i16.nxv2i8.i8( %0, i8 %1, @@ -666,10 +750,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv2i16_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i16_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i16_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i16.nxv2i8.i8( %0, %1, @@ -686,10 +772,13 @@ i64); define @intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i16.nxv4i8.i8( %0, i8 %1, @@ -706,10 +795,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv4i16_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i16_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i16_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i16.nxv4i8.i8( %0, %1, @@ -726,10 +817,13 @@ i64); define @intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwsubu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i16.nxv8i8.i8( %0, i8 %1, @@ -746,10 +840,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv8i16_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i16_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i16_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i16.nxv8i8.i8( %0, %1, @@ -766,10 +862,13 @@ i64); define @intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwsubu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv16i16.nxv16i8.i8( %0, i8 %1, @@ -786,10 +885,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv16i16_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i16_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i16_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv16i16.nxv16i8.i8( %0, %1, @@ -806,10 +907,13 @@ i64); define @intrinsic_vwsubu_vx_nxv32i16_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwsubu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv32i16.nxv32i8.i8( %0, i8 %1, @@ -826,10 +930,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv32i16_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv32i16_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv32i16_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv32i16.nxv32i8.i8( %0, %1, @@ -846,10 +952,13 @@ i64); define @intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i32.nxv1i16.i16( %0, i16 %1, @@ -866,10 +975,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv1i32_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i32_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i32_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i32.nxv1i16.i16( %0, %1, @@ -886,10 +997,13 @@ i64); define @intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i32.nxv2i16.i16( %0, i16 %1, @@ -906,10 +1020,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv2i32_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i32_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i32_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i32.nxv2i16.i16( %0, %1, @@ -926,10 +1042,13 @@ i64); define @intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwsubu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i32.nxv4i16.i16( %0, i16 %1, @@ -946,10 +1065,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv4i32_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i32_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i32_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i32.nxv4i16.i16( %0, %1, @@ -966,10 +1087,13 @@ i64); define @intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwsubu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i32.nxv8i16.i16( %0, i16 %1, @@ -986,10 +1110,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv8i32_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i32_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i32_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i32.nxv8i16.i16( %0, %1, @@ -1006,10 +1132,13 @@ i64); define @intrinsic_vwsubu_vx_nxv16i32_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwsubu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv16i32.nxv16i16.i16( %0, i16 %1, @@ -1026,10 +1155,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv16i32_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i32_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv16i32_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv16i32.nxv16i16.i16( %0, %1, @@ -1046,10 +1177,13 @@ i64); define @intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwsubu.vx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv1i64.nxv1i32.i32( %0, i32 %1, @@ -1066,10 +1200,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv1i64_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i64_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv1i64_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv1i64.nxv1i32.i32( %0, %1, @@ -1086,10 +1222,13 @@ i64); define @intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwsubu.vx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv2i64.nxv2i32.i32( %0, i32 %1, @@ -1106,10 +1245,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv2i64_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i64_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv2i64_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv2i64.nxv2i32.i32( %0, %1, @@ -1126,10 +1267,13 @@ i64); define @intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwsubu.vx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv4i64.nxv4i32.i32( %0, i32 %1, @@ -1146,10 +1290,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv4i64_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i64_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv4i64_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv4i64.nxv4i32.i32( %0, %1, @@ -1166,10 +1312,13 @@ i64); define @intrinsic_vwsubu_vx_nxv8i64_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwsubu.vx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.nxv8i64.nxv8i32.i32( %0, i32 %1, @@ -1186,10 +1335,12 @@ i64); define @intrinsic_vwsubu_mask_vx_nxv8i64_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i64_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsubu.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu_mask_vx_nxv8i64_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwsubu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.mask.nxv8i64.nxv8i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwsubu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwsubu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwsubu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,14 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +279,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +302,12 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +324,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +347,12 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +369,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwsubu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +392,12 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +414,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwsubu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +437,12 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +459,13 @@ i32); define @intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwsubu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +482,14 @@ i32); define @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +506,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i16.i8( %0, i8 %1, @@ -466,10 +529,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv1i16_nxv1i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i16.i8( %0, %1, @@ -486,10 +551,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i16.i8( %0, i8 %1, @@ -506,10 +574,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv2i16_nxv2i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i16.i8( %0, %1, @@ -526,10 +596,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i16.i8( %0, i8 %1, @@ -546,10 +619,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv4i16_nxv4i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i16.i8( %0, %1, @@ -566,10 +641,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwsubu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i16.i8( %0, i8 %1, @@ -586,10 +664,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv8i16_nxv8i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i16.i8( %0, %1, @@ -606,10 +686,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwsubu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv16i16.i8( %0, i8 %1, @@ -626,10 +709,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv16i16_nxv16i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv16i16.i8( %0, %1, @@ -646,10 +731,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwsubu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv32i16.i8( %0, i8 %1, @@ -666,10 +754,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv32i16_nxv32i16_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv32i16.i8( %0, %1, @@ -686,10 +776,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i32.i16( %0, i16 %1, @@ -706,10 +799,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv1i32_nxv1i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i32.i16( %0, %1, @@ -726,10 +821,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i32.i16( %0, i16 %1, @@ -746,10 +844,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv2i32_nxv2i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i32.i16( %0, %1, @@ -766,10 +866,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwsubu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i32.i16( %0, i16 %1, @@ -786,10 +889,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv4i32_nxv4i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i32.i16( %0, %1, @@ -806,10 +911,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwsubu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i32.i16( %0, i16 %1, @@ -826,10 +934,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv8i32_nxv8i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i32.i16( %0, %1, @@ -846,10 +956,13 @@ i32); define @intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwsubu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv16i32.i16( %0, i16 %1, @@ -866,10 +979,12 @@ i32); define @intrinsic_vwsubu.w_mask_wx_nxv16i32_nxv16i32_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv16i32.i16( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8( @@ -6,10 +7,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8( %0, %1, @@ -26,10 +30,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i16.nxv1i8( %0, %1, @@ -46,10 +52,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8( %0, %1, @@ -66,10 +75,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i16.nxv2i8( %0, %1, @@ -86,10 +97,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8( %0, %1, @@ -106,10 +120,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i16.nxv4i8( %0, %1, @@ -126,10 +142,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vwsubu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8( %0, %1, @@ -146,10 +165,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i16.nxv8i8( %0, %1, @@ -166,10 +187,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vwsubu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8( %0, %1, @@ -186,10 +210,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv16i16.nxv16i8( %0, %1, @@ -206,10 +232,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vwsubu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv32i16.nxv32i8( %0, %1, @@ -226,10 +255,14 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu +; CHECK-NEXT: vle8.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8( %0, %1, @@ -246,10 +279,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16( %0, %1, @@ -266,10 +302,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i32.nxv1i16( %0, %1, @@ -286,10 +324,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16( %0, %1, @@ -306,10 +347,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i32.nxv2i16( %0, %1, @@ -326,10 +369,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vwsubu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16( %0, %1, @@ -346,10 +392,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i32.nxv4i16( %0, %1, @@ -366,10 +414,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vwsubu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16( %0, %1, @@ -386,10 +437,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i32.nxv8i16( %0, %1, @@ -406,10 +459,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vwsubu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv16i32.nxv16i16( %0, %1, @@ -426,10 +482,14 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu +; CHECK-NEXT: vle16.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16( %0, %1, @@ -446,10 +506,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vwsubu.wv v25, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32( %0, %1, @@ -466,10 +529,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i64.nxv1i32( %0, %1, @@ -486,10 +551,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vwsubu.wv v26, v8, v10 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32( %0, %1, @@ -506,10 +574,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i64.nxv2i32( %0, %1, @@ -526,10 +596,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vwsubu.wv v28, v8, v12 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32( %0, %1, @@ -546,10 +619,12 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i64.nxv4i32( %0, %1, @@ -566,10 +641,13 @@ i64); define @intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vwsubu.wv v24, v8, v16 +; CHECK-NEXT: vmv8r.v v8, v24 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i64.nxv8i32( %0, %1, @@ -586,10 +664,14 @@ i64); define @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu +; CHECK-NEXT: vle32.v v28, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsubu.wv v8, v16, v28, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwsubu.wv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32( %0, %1, @@ -606,10 +688,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i16.i8( %0, i8 %1, @@ -626,10 +711,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv1i16_nxv1i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i16_nxv1i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i16_nxv1i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i16.i8( %0, %1, @@ -646,10 +733,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i16.i8( %0, i8 %1, @@ -666,10 +756,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv2i16_nxv2i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i16_nxv2i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i16_nxv2i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i16.i8( %0, %1, @@ -686,10 +778,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i16.i8( %0, i8 %1, @@ -706,10 +801,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv4i16_nxv4i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i16_nxv4i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i16_nxv4i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i16.i8( %0, %1, @@ -726,10 +823,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vwsubu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i16.i8( %0, i8 %1, @@ -746,10 +846,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv8i16_nxv8i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i16_nxv8i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i16_nxv8i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i16.i8( %0, %1, @@ -766,10 +868,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vwsubu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv16i16.i8( %0, i8 %1, @@ -786,10 +891,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv16i16_nxv16i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i16_nxv16i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i16_nxv16i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv16i16.i8( %0, %1, @@ -806,10 +913,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vwsubu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv32i16.i8( %0, i8 %1, @@ -826,10 +936,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv32i16_nxv32i16_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv32i16_nxv32i16_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv32i16_nxv32i16_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv32i16.i8( %0, %1, @@ -846,10 +958,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i32.i16( %0, i16 %1, @@ -866,10 +981,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv1i32_nxv1i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i32_nxv1i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i32_nxv1i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i32.i16( %0, %1, @@ -886,10 +1003,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i32.i16( %0, i16 %1, @@ -906,10 +1026,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv2i32_nxv2i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i32_nxv2i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i32_nxv2i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i32.i16( %0, %1, @@ -926,10 +1048,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vwsubu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i32.i16( %0, i16 %1, @@ -946,10 +1071,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv4i32_nxv4i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i32_nxv4i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i32_nxv4i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i32.i16( %0, %1, @@ -966,10 +1093,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vwsubu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i32.i16( %0, i16 %1, @@ -986,10 +1116,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv8i32_nxv8i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i32_nxv8i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i32_nxv8i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i32.i16( %0, %1, @@ -1006,10 +1138,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vwsubu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv16i32.i16( %0, i16 %1, @@ -1026,10 +1161,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv16i32_nxv16i32_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i32_nxv16i32_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i32_nxv16i32_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv16i32.i16( %0, %1, @@ -1046,10 +1183,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vwsubu.wx v25, v8, a0 +; CHECK-NEXT: vmv1r.v v8, v25 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv1i64.i32( %0, i32 %1, @@ -1066,10 +1206,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv1i64_nxv1i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i64_nxv1i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i64_nxv1i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv1i64.i32( %0, %1, @@ -1086,10 +1228,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vwsubu.wx v26, v8, a0 +; CHECK-NEXT: vmv2r.v v8, v26 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv2i64.i32( %0, i32 %1, @@ -1106,10 +1251,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv2i64_nxv2i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i64_nxv2i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i64_nxv2i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv2i64.i32( %0, %1, @@ -1126,10 +1273,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vwsubu.wx v28, v8, a0 +; CHECK-NEXT: vmv4r.v v8, v28 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv4i64.i32( %0, i32 %1, @@ -1146,10 +1296,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv4i64_nxv4i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i64_nxv4i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i64_nxv4i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv4i64.i32( %0, %1, @@ -1166,10 +1318,13 @@ i64); define @intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vwsubu.wx v16, v8, a0 +; CHECK-NEXT: vmv8r.v v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vwsubu.w.nxv8i64.i32( %0, i32 %1, @@ -1186,10 +1341,12 @@ i64); define @intrinsic_vwsubu.w_mask_wx_nxv8i64_nxv8i64_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i64_nxv8i64_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vwsubu.wx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i64_nxv8i64_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vwsubu.wx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vwsubu.w.mask.nxv8i64.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vxor.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i32); define @intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i32); define @intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i32); define @intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i32); define @intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i32); define @intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i32); define @intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i32); define @intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i32); define @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i32); define @intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i32); define @intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i32); define @intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i32); define @intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i32); define @intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i32); define @intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i32); define @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i32); define @intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i32); define @intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i32); define @intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i32); define @intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i32); define @intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i32); define @intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i32); define @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i32); define @intrinsic_vxor_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i8.i8( %0, i8 %1, @@ -746,10 +827,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i8.i8( %0, %1, @@ -766,10 +849,12 @@ i32); define @intrinsic_vxor_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i8.i8( %0, i8 %1, @@ -786,10 +871,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i8.i8( %0, %1, @@ -806,10 +893,12 @@ i32); define @intrinsic_vxor_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i8.i8( %0, i8 %1, @@ -826,10 +915,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i8.i8( %0, %1, @@ -846,10 +937,12 @@ i32); define @intrinsic_vxor_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i8.i8( %0, i8 %1, @@ -866,10 +959,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i8.i8( %0, %1, @@ -886,10 +981,12 @@ i32); define @intrinsic_vxor_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i8.i8( %0, i8 %1, @@ -906,10 +1003,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vxor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i8.i8( %0, %1, @@ -926,10 +1025,12 @@ i32); define @intrinsic_vxor_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv32i8.i8( %0, i8 %1, @@ -946,10 +1047,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vxor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i8.i8( %0, %1, @@ -966,10 +1069,12 @@ i32); define @intrinsic_vxor_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv64i8.i8( %0, i8 %1, @@ -986,10 +1091,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vxor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv64i8.i8( %0, %1, @@ -1006,10 +1113,12 @@ i32); define @intrinsic_vxor_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i16.i16( %0, i16 %1, @@ -1026,10 +1135,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i16.i16( %0, %1, @@ -1046,10 +1157,12 @@ i32); define @intrinsic_vxor_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i16.i16( %0, i16 %1, @@ -1066,10 +1179,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i16.i16( %0, %1, @@ -1086,10 +1201,12 @@ i32); define @intrinsic_vxor_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i16.i16( %0, i16 %1, @@ -1106,10 +1223,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i16.i16( %0, %1, @@ -1126,10 +1245,12 @@ i32); define @intrinsic_vxor_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i16.i16( %0, i16 %1, @@ -1146,10 +1267,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vxor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i16.i16( %0, %1, @@ -1166,10 +1289,12 @@ i32); define @intrinsic_vxor_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i16.i16( %0, i16 %1, @@ -1186,10 +1311,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vxor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i16.i16( %0, %1, @@ -1206,10 +1333,12 @@ i32); define @intrinsic_vxor_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv32i16.i16( %0, i16 %1, @@ -1226,10 +1355,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vxor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i16.i16( %0, %1, @@ -1246,10 +1377,12 @@ i32); define @intrinsic_vxor_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i32.i32( %0, i32 %1, @@ -1266,10 +1399,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i32.i32( %0, %1, @@ -1286,10 +1421,12 @@ i32); define @intrinsic_vxor_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i32.i32( %0, i32 %1, @@ -1306,10 +1443,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i32.i32( %0, %1, @@ -1326,10 +1465,12 @@ i32); define @intrinsic_vxor_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i32.i32( %0, i32 %1, @@ -1346,10 +1487,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vxor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i32.i32( %0, %1, @@ -1366,10 +1509,12 @@ i32); define @intrinsic_vxor_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i32.i32( %0, i32 %1, @@ -1386,10 +1531,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vxor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i32.i32( %0, %1, @@ -1406,10 +1553,12 @@ i32); define @intrinsic_vxor_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i32.i32( %0, i32 %1, @@ -1426,10 +1575,12 @@ i32); define @intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vxor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i32.i32( %0, %1, @@ -1441,10 +1592,12 @@ } define @intrinsic_vxor_vi_nxv1i8_nxv1i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv1i8.i8( %0, i8 9, @@ -1454,10 +1607,12 @@ } define @intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i8.i8( %0, %1, @@ -1469,10 +1624,12 @@ } define @intrinsic_vxor_vi_nxv2i8_nxv2i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv2i8.i8( %0, i8 9, @@ -1482,10 +1639,12 @@ } define @intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i8.i8( %0, %1, @@ -1497,10 +1656,12 @@ } define @intrinsic_vxor_vi_nxv4i8_nxv4i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv4i8.i8( %0, i8 9, @@ -1510,10 +1671,12 @@ } define @intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i8.i8( %0, %1, @@ -1525,10 +1688,12 @@ } define @intrinsic_vxor_vi_nxv8i8_nxv8i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv8i8.i8( %0, i8 9, @@ -1538,10 +1703,12 @@ } define @intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i8.i8( %0, %1, @@ -1553,10 +1720,12 @@ } define @intrinsic_vxor_vi_nxv16i8_nxv16i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv16i8.i8( %0, i8 9, @@ -1566,10 +1735,12 @@ } define @intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vxor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i8.i8( %0, %1, @@ -1581,10 +1752,12 @@ } define @intrinsic_vxor_vi_nxv32i8_nxv32i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv32i8.i8( %0, i8 9, @@ -1594,10 +1767,12 @@ } define @intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vxor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i8.i8( %0, %1, @@ -1609,10 +1784,12 @@ } define @intrinsic_vxor_vi_nxv64i8_nxv64i8_i8( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv64i8.i8( %0, i8 9, @@ -1622,10 +1799,12 @@ } define @intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vxor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv64i8.i8( %0, %1, @@ -1637,10 +1816,12 @@ } define @intrinsic_vxor_vi_nxv1i16_nxv1i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv1i16.i16( %0, i16 9, @@ -1650,10 +1831,12 @@ } define @intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i16.i16( %0, %1, @@ -1665,10 +1848,12 @@ } define @intrinsic_vxor_vi_nxv2i16_nxv2i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv2i16.i16( %0, i16 9, @@ -1678,10 +1863,12 @@ } define @intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i16.i16( %0, %1, @@ -1693,10 +1880,12 @@ } define @intrinsic_vxor_vi_nxv4i16_nxv4i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv4i16.i16( %0, i16 9, @@ -1706,10 +1895,12 @@ } define @intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i16.i16( %0, %1, @@ -1721,10 +1912,12 @@ } define @intrinsic_vxor_vi_nxv8i16_nxv8i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv8i16.i16( %0, i16 9, @@ -1734,10 +1927,12 @@ } define @intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vxor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i16.i16( %0, %1, @@ -1749,10 +1944,12 @@ } define @intrinsic_vxor_vi_nxv16i16_nxv16i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv16i16.i16( %0, i16 9, @@ -1762,10 +1959,12 @@ } define @intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vxor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i16.i16( %0, %1, @@ -1777,10 +1976,12 @@ } define @intrinsic_vxor_vi_nxv32i16_nxv32i16_i16( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv32i16.i16( %0, i16 9, @@ -1790,10 +1991,12 @@ } define @intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vxor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i16.i16( %0, %1, @@ -1805,10 +2008,12 @@ } define @intrinsic_vxor_vi_nxv1i32_nxv1i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv1i32.i32( %0, i32 9, @@ -1818,10 +2023,12 @@ } define @intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i32.i32( %0, %1, @@ -1833,10 +2040,12 @@ } define @intrinsic_vxor_vi_nxv2i32_nxv2i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv2i32.i32( %0, i32 9, @@ -1846,10 +2055,12 @@ } define @intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i32.i32( %0, %1, @@ -1861,10 +2072,12 @@ } define @intrinsic_vxor_vi_nxv4i32_nxv4i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv4i32.i32( %0, i32 9, @@ -1874,10 +2087,12 @@ } define @intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vxor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i32.i32( %0, %1, @@ -1889,10 +2104,12 @@ } define @intrinsic_vxor_vi_nxv8i32_nxv8i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv8i32.i32( %0, i32 9, @@ -1902,10 +2119,12 @@ } define @intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vxor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i32.i32( %0, %1, @@ -1917,10 +2136,12 @@ } define @intrinsic_vxor_vi_nxv16i32_nxv16i32_i32( %0, i32 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv16i32.i32( %0, i32 9, @@ -1930,10 +2151,12 @@ } define @intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i32 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vxor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i32.i32( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \ ; RUN: --riscv-no-aliases < %s | FileCheck %s declare @llvm.riscv.vxor.nxv1i8.nxv1i8( @@ -6,10 +7,12 @@ i64); define @intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i8.nxv1i8( %0, %1, @@ -26,10 +29,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i8.nxv1i8( %0, %1, @@ -46,10 +51,12 @@ i64); define @intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i8.nxv2i8( %0, %1, @@ -66,10 +73,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i8.nxv2i8( %0, %1, @@ -86,10 +95,12 @@ i64); define @intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i8.nxv4i8( %0, %1, @@ -106,10 +117,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i8.nxv4i8( %0, %1, @@ -126,10 +139,12 @@ i64); define @intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i8.nxv8i8( %0, %1, @@ -146,10 +161,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i8.nxv8i8( %0, %1, @@ -166,10 +183,12 @@ i64); define @intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i8.nxv16i8( %0, %1, @@ -186,10 +205,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i8.nxv16i8( %0, %1, @@ -206,10 +227,12 @@ i64); define @intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv32i8.nxv32i8( %0, %1, @@ -226,10 +249,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i8.nxv32i8( %0, %1, @@ -246,10 +271,12 @@ i64); define @intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv64i8.nxv64i8( %0, %1, @@ -266,10 +293,14 @@ i64); define @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e8,m8,ta,mu +; CHECK-NEXT: vle8.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e8,m8,tu,mu +; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv64i8.nxv64i8( %0, %1, @@ -286,10 +317,12 @@ i64); define @intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i16.nxv1i16( %0, %1, @@ -306,10 +339,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i16.nxv1i16( %0, %1, @@ -326,10 +361,12 @@ i64); define @intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i16.nxv2i16( %0, %1, @@ -346,10 +383,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i16.nxv2i16( %0, %1, @@ -366,10 +405,12 @@ i64); define @intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i16.nxv4i16( %0, %1, @@ -386,10 +427,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i16.nxv4i16( %0, %1, @@ -406,10 +449,12 @@ i64); define @intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i16.nxv8i16( %0, %1, @@ -426,10 +471,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i16.nxv8i16( %0, %1, @@ -446,10 +493,12 @@ i64); define @intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i16.nxv16i16( %0, %1, @@ -466,10 +515,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i16.nxv16i16( %0, %1, @@ -486,10 +537,12 @@ i64); define @intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv32i16.nxv32i16( %0, %1, @@ -506,10 +559,14 @@ i64); define @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e16,m8,ta,mu +; CHECK-NEXT: vle16.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu +; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i16.nxv32i16( %0, %1, @@ -526,10 +583,12 @@ i64); define @intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i32.nxv1i32( %0, %1, @@ -546,10 +605,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i32.nxv1i32( %0, %1, @@ -566,10 +627,12 @@ i64); define @intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i32.nxv2i32( %0, %1, @@ -586,10 +649,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i32.nxv2i32( %0, %1, @@ -606,10 +671,12 @@ i64); define @intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i32.nxv4i32( %0, %1, @@ -626,10 +693,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i32.nxv4i32( %0, %1, @@ -646,10 +715,12 @@ i64); define @intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i32.nxv8i32( %0, %1, @@ -666,10 +737,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i32.nxv8i32( %0, %1, @@ -686,10 +759,12 @@ i64); define @intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i32.nxv16i32( %0, %1, @@ -706,10 +781,14 @@ i64); define @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e32,m8,ta,mu +; CHECK-NEXT: vle32.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu +; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i32.nxv16i32( %0, %1, @@ -726,10 +805,12 @@ i64); define @intrinsic_vxor_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i64.nxv1i64( %0, %1, @@ -746,10 +827,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i64_nxv1i64_nxv1i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vxor.vv v8, v9, v10, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i64_nxv1i64_nxv1i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i64.nxv1i64( %0, %1, @@ -766,10 +849,12 @@ i64); define @intrinsic_vxor_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v10 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i64.nxv2i64( %0, %1, @@ -786,10 +871,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i64_nxv2i64_nxv2i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vxor.vv v8, v10, v12, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i64_nxv2i64_nxv2i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i64.nxv2i64( %0, %1, @@ -806,10 +893,12 @@ i64); define @intrinsic_vxor_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v12 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i64.nxv4i64( %0, %1, @@ -826,10 +915,12 @@ i64); define @intrinsic_vxor_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i64_nxv4i64_nxv4i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vxor.vv v8, v12, v16, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i64_nxv4i64_nxv4i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i64.nxv4i64( %0, %1, @@ -846,10 +937,12 @@ i64); define @intrinsic_vxor_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i64.nxv8i64( %0, %1, @@ -866,10 +959,14 @@ i64); define @intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu +; CHECK-NEXT: vle64.v v24, (a0) +; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu +; CHECK-NEXT: vxor.vv v8, v16, v24, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i64.nxv8i64( %0, %1, @@ -886,10 +983,12 @@ i64); define @intrinsic_vxor_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i8.i8( %0, i8 %1, @@ -906,10 +1005,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i8.i8( %0, %1, @@ -926,10 +1027,12 @@ i64); define @intrinsic_vxor_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i8.i8( %0, i8 %1, @@ -946,10 +1049,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i8.i8( %0, %1, @@ -966,10 +1071,12 @@ i64); define @intrinsic_vxor_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i8.i8( %0, i8 %1, @@ -986,10 +1093,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i8.i8( %0, %1, @@ -1006,10 +1115,12 @@ i64); define @intrinsic_vxor_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i8.i8( %0, i8 %1, @@ -1026,10 +1137,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i8.i8( %0, %1, @@ -1046,10 +1159,12 @@ i64); define @intrinsic_vxor_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i8.i8( %0, i8 %1, @@ -1066,10 +1181,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu +; CHECK-NEXT: vxor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i8.i8( %0, %1, @@ -1086,10 +1203,12 @@ i64); define @intrinsic_vxor_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv32i8.i8( %0, i8 %1, @@ -1106,10 +1225,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu +; CHECK-NEXT: vxor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i8.i8( %0, %1, @@ -1126,10 +1247,12 @@ i64); define @intrinsic_vxor_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv64i8.i8( %0, i8 %1, @@ -1146,10 +1269,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e8,m8,tu,mu +; CHECK-NEXT: vxor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv64i8.i8( %0, %1, @@ -1166,10 +1291,12 @@ i64); define @intrinsic_vxor_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i16.i16( %0, i16 %1, @@ -1186,10 +1313,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i16.i16( %0, %1, @@ -1206,10 +1335,12 @@ i64); define @intrinsic_vxor_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i16.i16( %0, i16 %1, @@ -1226,10 +1357,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i16.i16( %0, %1, @@ -1246,10 +1379,12 @@ i64); define @intrinsic_vxor_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i16.i16( %0, i16 %1, @@ -1266,10 +1401,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i16.i16( %0, %1, @@ -1286,10 +1423,12 @@ i64); define @intrinsic_vxor_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i16.i16( %0, i16 %1, @@ -1306,10 +1445,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu +; CHECK-NEXT: vxor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i16.i16( %0, %1, @@ -1326,10 +1467,12 @@ i64); define @intrinsic_vxor_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i16.i16( %0, i16 %1, @@ -1346,10 +1489,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu +; CHECK-NEXT: vxor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i16.i16( %0, %1, @@ -1366,10 +1511,12 @@ i64); define @intrinsic_vxor_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv32i16.i16( %0, i16 %1, @@ -1386,10 +1533,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e16,m8,tu,mu +; CHECK-NEXT: vxor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i16.i16( %0, %1, @@ -1406,10 +1555,12 @@ i64); define @intrinsic_vxor_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i32.i32( %0, i32 %1, @@ -1426,10 +1577,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i32.i32( %0, %1, @@ -1446,10 +1599,12 @@ i64); define @intrinsic_vxor_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i32.i32( %0, i32 %1, @@ -1466,10 +1621,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i32.i32( %0, %1, @@ -1486,10 +1643,12 @@ i64); define @intrinsic_vxor_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i32.i32( %0, i32 %1, @@ -1506,10 +1665,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu +; CHECK-NEXT: vxor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i32.i32( %0, %1, @@ -1526,10 +1687,12 @@ i64); define @intrinsic_vxor_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i32.i32( %0, i32 %1, @@ -1546,10 +1709,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu +; CHECK-NEXT: vxor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i32.i32( %0, %1, @@ -1566,10 +1731,12 @@ i64); define @intrinsic_vxor_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv16i32.i32( %0, i32 %1, @@ -1586,10 +1753,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e32,m8,tu,mu +; CHECK-NEXT: vxor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i32.i32( %0, %1, @@ -1606,10 +1775,12 @@ i64); define @intrinsic_vxor_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv1i64.i64( %0, i64 %1, @@ -1626,10 +1797,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu +; CHECK-NEXT: vxor.vx v8, v9, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i64.i64( %0, %1, @@ -1646,10 +1819,12 @@ i64); define @intrinsic_vxor_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv2i64.i64( %0, i64 %1, @@ -1666,10 +1841,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu +; CHECK-NEXT: vxor.vx v8, v10, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i64.i64( %0, %1, @@ -1686,10 +1863,12 @@ i64); define @intrinsic_vxor_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv4i64.i64( %0, i64 %1, @@ -1706,10 +1885,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu +; CHECK-NEXT: vxor.vx v8, v12, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i64.i64( %0, %1, @@ -1726,10 +1907,12 @@ i64); define @intrinsic_vxor_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { +; CHECK-LABEL: intrinsic_vxor_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,ta,mu +; CHECK-NEXT: vxor.vx v8, v8, a0 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}} %a = call @llvm.riscv.vxor.nxv8i64.i64( %0, i64 %1, @@ -1746,10 +1929,12 @@ i64); define @intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a1, a1, e64,m8,tu,mu +; CHECK-NEXT: vxor.vx v8, v16, a0, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i64.i64( %0, %1, @@ -1761,10 +1946,12 @@ } define @intrinsic_vxor_vi_nxv1i8_nxv1i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv1i8.i8( %0, i8 9, @@ -1774,10 +1961,12 @@ } define @intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i8.i8( %0, %1, @@ -1789,10 +1978,12 @@ } define @intrinsic_vxor_vi_nxv2i8_nxv2i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv2i8.i8( %0, i8 9, @@ -1802,10 +1993,12 @@ } define @intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i8.i8( %0, %1, @@ -1817,10 +2010,12 @@ } define @intrinsic_vxor_vi_nxv4i8_nxv4i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv4i8.i8( %0, i8 9, @@ -1830,10 +2025,12 @@ } define @intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i8.i8( %0, %1, @@ -1845,10 +2042,12 @@ } define @intrinsic_vxor_vi_nxv8i8_nxv8i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv8i8.i8( %0, i8 9, @@ -1858,10 +2057,12 @@ } define @intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i8.i8( %0, %1, @@ -1873,10 +2074,12 @@ } define @intrinsic_vxor_vi_nxv16i8_nxv16i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv16i8.i8( %0, i8 9, @@ -1886,10 +2089,12 @@ } define @intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu +; CHECK-NEXT: vxor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i8.i8( %0, %1, @@ -1901,10 +2106,12 @@ } define @intrinsic_vxor_vi_nxv32i8_nxv32i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv32i8.i8( %0, i8 9, @@ -1914,10 +2121,12 @@ } define @intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu +; CHECK-NEXT: vxor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i8.i8( %0, %1, @@ -1929,10 +2138,12 @@ } define @intrinsic_vxor_vi_nxv64i8_nxv64i8_i8( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv64i8.i8( %0, i8 9, @@ -1942,10 +2153,12 @@ } define @intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu +; CHECK-NEXT: vxor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv64i8.i8( %0, %1, @@ -1957,10 +2170,12 @@ } define @intrinsic_vxor_vi_nxv1i16_nxv1i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv1i16.i16( %0, i16 9, @@ -1970,10 +2185,12 @@ } define @intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i16.i16( %0, %1, @@ -1985,10 +2202,12 @@ } define @intrinsic_vxor_vi_nxv2i16_nxv2i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv2i16.i16( %0, i16 9, @@ -1998,10 +2217,12 @@ } define @intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i16.i16( %0, %1, @@ -2013,10 +2234,12 @@ } define @intrinsic_vxor_vi_nxv4i16_nxv4i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv4i16.i16( %0, i16 9, @@ -2026,10 +2249,12 @@ } define @intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i16.i16( %0, %1, @@ -2041,10 +2266,12 @@ } define @intrinsic_vxor_vi_nxv8i16_nxv8i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv8i16.i16( %0, i16 9, @@ -2054,10 +2281,12 @@ } define @intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu +; CHECK-NEXT: vxor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i16.i16( %0, %1, @@ -2069,10 +2298,12 @@ } define @intrinsic_vxor_vi_nxv16i16_nxv16i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv16i16.i16( %0, i16 9, @@ -2082,10 +2313,12 @@ } define @intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu +; CHECK-NEXT: vxor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i16.i16( %0, %1, @@ -2097,10 +2330,12 @@ } define @intrinsic_vxor_vi_nxv32i16_nxv32i16_i16( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv32i16.i16( %0, i16 9, @@ -2110,10 +2345,12 @@ } define @intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vxor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv32i16.i16( %0, %1, @@ -2125,10 +2362,12 @@ } define @intrinsic_vxor_vi_nxv1i32_nxv1i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv1i32.i32( %0, i32 9, @@ -2138,10 +2377,12 @@ } define @intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i32.i32( %0, %1, @@ -2153,10 +2394,12 @@ } define @intrinsic_vxor_vi_nxv2i32_nxv2i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv2i32.i32( %0, i32 9, @@ -2166,10 +2409,12 @@ } define @intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i32.i32( %0, %1, @@ -2181,10 +2426,12 @@ } define @intrinsic_vxor_vi_nxv4i32_nxv4i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv4i32.i32( %0, i32 9, @@ -2194,10 +2441,12 @@ } define @intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu +; CHECK-NEXT: vxor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i32.i32( %0, %1, @@ -2209,10 +2458,12 @@ } define @intrinsic_vxor_vi_nxv8i32_nxv8i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv8i32.i32( %0, i32 9, @@ -2222,10 +2473,12 @@ } define @intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu +; CHECK-NEXT: vxor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i32.i32( %0, %1, @@ -2237,10 +2490,12 @@ } define @intrinsic_vxor_vi_nxv16i32_nxv16i32_i32( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv16i32.i32( %0, i32 9, @@ -2250,10 +2505,12 @@ } define @intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vxor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv16i32.i32( %0, %1, @@ -2265,10 +2522,12 @@ } define @intrinsic_vxor_vi_nxv1i64_nxv1i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv1i64.i64( %0, i64 9, @@ -2278,10 +2537,12 @@ } define @intrinsic_vxor_mask_vi_nxv1i64_nxv1i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i64_nxv1i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu +; CHECK-NEXT: vxor.vi v8, v9, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i64_nxv1i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv1i64.i64( %0, %1, @@ -2293,10 +2554,12 @@ } define @intrinsic_vxor_vi_nxv2i64_nxv2i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv2i64.i64( %0, i64 9, @@ -2306,10 +2569,12 @@ } define @intrinsic_vxor_mask_vi_nxv2i64_nxv2i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i64_nxv2i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu +; CHECK-NEXT: vxor.vi v8, v10, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i64_nxv2i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv2i64.i64( %0, %1, @@ -2321,10 +2586,12 @@ } define @intrinsic_vxor_vi_nxv4i64_nxv4i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv4i64.i64( %0, i64 9, @@ -2334,10 +2601,12 @@ } define @intrinsic_vxor_mask_vi_nxv4i64_nxv4i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i64_nxv4i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu +; CHECK-NEXT: vxor.vi v8, v12, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i64_nxv4i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv4i64.i64( %0, %1, @@ -2349,10 +2618,12 @@ } define @intrinsic_vxor_vi_nxv8i64_nxv8i64_i64( %0, i64 %1) nounwind { +; CHECK-LABEL: intrinsic_vxor_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu +; CHECK-NEXT: vxor.vi v8, v8, 9 +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9 %a = call @llvm.riscv.vxor.nxv8i64.i64( %0, i64 9, @@ -2362,10 +2633,12 @@ } define @intrinsic_vxor_mask_vi_nxv8i64_nxv8i64_i64( %0, %1, %2, i64 %3) nounwind { +; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i64_nxv8i64_i64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vxor.vi v8, v16, 9, v0.t +; CHECK-NEXT: jalr zero, 0(ra) entry: -; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i64_nxv8i64_i64 -; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,tu,mu -; CHECK: vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t %a = call @llvm.riscv.vxor.mask.nxv8i64.i64( %0, %1, diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vxor_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vxor_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -27,7 +27,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -39,7 +39,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -64,7 +64,7 @@ ; CHECK-LABEL: vxor_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -74,7 +74,7 @@ ; CHECK-LABEL: vxor_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -86,7 +86,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -123,7 +123,7 @@ ; CHECK-LABEL: vxor_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -133,7 +133,7 @@ ; CHECK-LABEL: vxor_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -170,7 +170,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK-LABEL: vxor_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -192,7 +192,7 @@ ; CHECK-LABEL: vxor_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -204,7 +204,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -216,7 +216,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -229,7 +229,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -241,7 +241,7 @@ ; CHECK-LABEL: vxor_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v18 +; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -251,7 +251,7 @@ ; CHECK-LABEL: vxor_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -263,7 +263,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -275,7 +275,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -288,7 +288,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +300,7 @@ ; CHECK-LABEL: vxor_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v20 +; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -310,7 +310,7 @@ ; CHECK-LABEL: vxor_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -322,7 +322,7 @@ ; CHECK-LABEL: vxor_vi_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,7 +334,7 @@ ; CHECK-LABEL: vxor_vi_nxv32i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -347,7 +347,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -358,9 +358,8 @@ define @vxor_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vxor_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vxor.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -370,7 +369,7 @@ ; CHECK-LABEL: vxor_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -382,7 +381,7 @@ ; CHECK-LABEL: vxor_vi_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -394,7 +393,7 @@ ; CHECK-LABEL: vxor_vi_nxv64i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -407,7 +406,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -419,7 +418,7 @@ ; CHECK-LABEL: vxor_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -429,7 +428,7 @@ ; CHECK-LABEL: vxor_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -441,7 +440,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -453,7 +452,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -466,7 +465,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -478,7 +477,7 @@ ; CHECK-LABEL: vxor_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -488,7 +487,7 @@ ; CHECK-LABEL: vxor_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -500,7 +499,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -512,7 +511,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -525,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -537,7 +536,7 @@ ; CHECK-LABEL: vxor_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -547,7 +546,7 @@ ; CHECK-LABEL: vxor_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -559,7 +558,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -571,7 +570,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -584,7 +583,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -596,7 +595,7 @@ ; CHECK-LABEL: vxor_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v18 +; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -606,7 +605,7 @@ ; CHECK-LABEL: vxor_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -618,7 +617,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -630,7 +629,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -643,7 +642,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -655,7 +654,7 @@ ; CHECK-LABEL: vxor_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v20 +; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -665,7 +664,7 @@ ; CHECK-LABEL: vxor_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -677,7 +676,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -689,7 +688,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -702,7 +701,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -713,9 +712,8 @@ define @vxor_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vxor_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vxor.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -725,7 +723,7 @@ ; CHECK-LABEL: vxor_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -737,7 +735,7 @@ ; CHECK-LABEL: vxor_vi_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -749,7 +747,7 @@ ; CHECK-LABEL: vxor_vi_nxv32i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -762,7 +760,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -774,7 +772,7 @@ ; CHECK-LABEL: vxor_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -784,7 +782,7 @@ ; CHECK-LABEL: vxor_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -796,7 +794,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -808,7 +806,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -821,7 +819,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -833,7 +831,7 @@ ; CHECK-LABEL: vxor_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -843,7 +841,7 @@ ; CHECK-LABEL: vxor_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -855,7 +853,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -867,7 +865,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -880,7 +878,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -892,7 +890,7 @@ ; CHECK-LABEL: vxor_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v18 +; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -902,7 +900,7 @@ ; CHECK-LABEL: vxor_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -914,7 +912,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -926,7 +924,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -939,7 +937,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -951,7 +949,7 @@ ; CHECK-LABEL: vxor_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v20 +; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -961,7 +959,7 @@ ; CHECK-LABEL: vxor_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -973,7 +971,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -985,7 +983,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -998,7 +996,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1009,9 +1007,8 @@ define @vxor_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vxor_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vxor.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1021,7 +1018,7 @@ ; CHECK-LABEL: vxor_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1033,7 +1030,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1045,7 +1042,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1058,7 +1055,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1070,7 +1067,7 @@ ; CHECK-LABEL: vxor_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1087,7 +1084,7 @@ ; CHECK-NEXT: vsll.vx v26, v26, a1 ; CHECK-NEXT: vsrl.vx v26, v26, a1 ; CHECK-NEXT: vor.vv v25, v26, v25 -; CHECK-NEXT: vxor.vv v16, v16, v25 +; CHECK-NEXT: vxor.vv v8, v8, v25 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1099,7 +1096,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1111,7 +1108,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1124,7 +1121,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1136,7 +1133,7 @@ ; CHECK-LABEL: vxor_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v18 +; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1153,7 +1150,7 @@ ; CHECK-NEXT: vsll.vx v28, v28, a1 ; CHECK-NEXT: vsrl.vx v28, v28, a1 ; CHECK-NEXT: vor.vv v26, v28, v26 -; CHECK-NEXT: vxor.vv v16, v16, v26 +; CHECK-NEXT: vxor.vv v8, v8, v26 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1165,7 +1162,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1177,7 +1174,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1190,7 +1187,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1202,7 +1199,7 @@ ; CHECK-LABEL: vxor_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v20 +; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1215,11 +1212,11 @@ ; CHECK-NEXT: vmv.v.x v28, a1 ; CHECK-NEXT: addi a1, zero, 32 ; CHECK-NEXT: vsll.vx v28, v28, a1 -; CHECK-NEXT: vmv.v.x v8, a0 -; CHECK-NEXT: vsll.vx v8, v8, a1 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: vor.vv v28, v8, v28 -; CHECK-NEXT: vxor.vv v16, v16, v28 +; CHECK-NEXT: vmv.v.x v12, a0 +; CHECK-NEXT: vsll.vx v12, v12, a1 +; CHECK-NEXT: vsrl.vx v12, v12, a1 +; CHECK-NEXT: vor.vv v28, v12, v28 +; CHECK-NEXT: vxor.vv v8, v8, v28 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1231,7 +1228,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1243,7 +1240,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1256,7 +1253,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1267,9 +1264,8 @@ define @vxor_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vxor_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vxor.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1279,14 +1275,14 @@ ; CHECK-LABEL: vxor_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64,m8,ta,mu -; CHECK-NEXT: vmv.v.x v8, a1 +; CHECK-NEXT: vmv.v.x v16, a1 ; CHECK-NEXT: addi a1, zero, 32 -; CHECK-NEXT: vsll.vx v8, v8, a1 +; CHECK-NEXT: vsll.vx v16, v16, a1 ; CHECK-NEXT: vmv.v.x v24, a0 ; CHECK-NEXT: vsll.vx v24, v24, a1 ; CHECK-NEXT: vsrl.vx v24, v24, a1 -; CHECK-NEXT: vor.vv v8, v24, v8 -; CHECK-NEXT: vxor.vv v16, v16, v8 +; CHECK-NEXT: vor.vv v16, v24, v16 +; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1298,7 +1294,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1310,7 +1306,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1323,7 +1319,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv64.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: vxor_vv_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -15,7 +15,7 @@ ; CHECK-LABEL: vxor_vx_nxv1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -27,7 +27,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -39,7 +39,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -52,7 +52,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -64,7 +64,7 @@ ; CHECK-LABEL: vxor_vv_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -74,7 +74,7 @@ ; CHECK-LABEL: vxor_vx_nxv2i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -86,7 +86,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -98,7 +98,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -111,7 +111,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -123,7 +123,7 @@ ; CHECK-LABEL: vxor_vv_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -133,7 +133,7 @@ ; CHECK-LABEL: vxor_vx_nxv4i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -145,7 +145,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -157,7 +157,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -170,7 +170,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -182,7 +182,7 @@ ; CHECK-LABEL: vxor_vv_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -192,7 +192,7 @@ ; CHECK-LABEL: vxor_vx_nxv8i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -204,7 +204,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -216,7 +216,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -229,7 +229,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -241,7 +241,7 @@ ; CHECK-LABEL: vxor_vv_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v18 +; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -251,7 +251,7 @@ ; CHECK-LABEL: vxor_vx_nxv16i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -263,7 +263,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -275,7 +275,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -288,7 +288,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -300,7 +300,7 @@ ; CHECK-LABEL: vxor_vv_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v20 +; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -310,7 +310,7 @@ ; CHECK-LABEL: vxor_vx_nxv32i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -322,7 +322,7 @@ ; CHECK-LABEL: vxor_vi_nxv32i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -334,7 +334,7 @@ ; CHECK-LABEL: vxor_vi_nxv32i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -347,7 +347,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -358,9 +358,8 @@ define @vxor_vv_nxv64i8( %va, %vb) { ; CHECK-LABEL: vxor_vv_nxv64i8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vxor.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -370,7 +369,7 @@ ; CHECK-LABEL: vxor_vx_nxv64i8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -382,7 +381,7 @@ ; CHECK-LABEL: vxor_vi_nxv64i8_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i8 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -394,7 +393,7 @@ ; CHECK-LABEL: vxor_vi_nxv64i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i8 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -407,7 +406,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i8 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -419,7 +418,7 @@ ; CHECK-LABEL: vxor_vv_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -429,7 +428,7 @@ ; CHECK-LABEL: vxor_vx_nxv1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -441,7 +440,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -453,7 +452,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -466,7 +465,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -478,7 +477,7 @@ ; CHECK-LABEL: vxor_vv_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -488,7 +487,7 @@ ; CHECK-LABEL: vxor_vx_nxv2i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -500,7 +499,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -512,7 +511,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -525,7 +524,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -537,7 +536,7 @@ ; CHECK-LABEL: vxor_vv_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -547,7 +546,7 @@ ; CHECK-LABEL: vxor_vx_nxv4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -559,7 +558,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -571,7 +570,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -584,7 +583,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -596,7 +595,7 @@ ; CHECK-LABEL: vxor_vv_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v18 +; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -606,7 +605,7 @@ ; CHECK-LABEL: vxor_vx_nxv8i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -618,7 +617,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -630,7 +629,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -643,7 +642,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -655,7 +654,7 @@ ; CHECK-LABEL: vxor_vv_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v20 +; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -665,7 +664,7 @@ ; CHECK-LABEL: vxor_vx_nxv16i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -677,7 +676,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -689,7 +688,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -702,7 +701,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -713,9 +712,8 @@ define @vxor_vv_nxv32i16( %va, %vb) { ; CHECK-LABEL: vxor_vv_nxv32i16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vxor.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -725,7 +723,7 @@ ; CHECK-LABEL: vxor_vx_nxv32i16: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -737,7 +735,7 @@ ; CHECK-LABEL: vxor_vi_nxv32i16_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i16 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -749,7 +747,7 @@ ; CHECK-LABEL: vxor_vi_nxv32i16_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i16 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -762,7 +760,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i16 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -774,7 +772,7 @@ ; CHECK-LABEL: vxor_vv_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -784,7 +782,7 @@ ; CHECK-LABEL: vxor_vx_nxv1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -796,7 +794,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -808,7 +806,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -821,7 +819,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -833,7 +831,7 @@ ; CHECK-LABEL: vxor_vv_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -843,7 +841,7 @@ ; CHECK-LABEL: vxor_vx_nxv2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -855,7 +853,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -867,7 +865,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -880,7 +878,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -892,7 +890,7 @@ ; CHECK-LABEL: vxor_vv_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v18 +; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -902,7 +900,7 @@ ; CHECK-LABEL: vxor_vx_nxv4i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -914,7 +912,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -926,7 +924,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -939,7 +937,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -951,7 +949,7 @@ ; CHECK-LABEL: vxor_vv_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v20 +; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -961,7 +959,7 @@ ; CHECK-LABEL: vxor_vx_nxv8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -973,7 +971,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -985,7 +983,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -998,7 +996,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1009,9 +1007,8 @@ define @vxor_vv_nxv16i32( %va, %vb) { ; CHECK-LABEL: vxor_vv_nxv16i32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vxor.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1021,7 +1018,7 @@ ; CHECK-LABEL: vxor_vx_nxv16i32: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1033,7 +1030,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i32_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i32 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1045,7 +1042,7 @@ ; CHECK-LABEL: vxor_vi_nxv16i32_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i32 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1058,7 +1055,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i32 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1070,7 +1067,7 @@ ; CHECK-LABEL: vxor_vv_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v17 +; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1080,7 +1077,7 @@ ; CHECK-LABEL: vxor_vx_nxv1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1092,7 +1089,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1104,7 +1101,7 @@ ; CHECK-LABEL: vxor_vi_nxv1i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1117,7 +1114,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1129,7 +1126,7 @@ ; CHECK-LABEL: vxor_vv_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v18 +; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1139,7 +1136,7 @@ ; CHECK-LABEL: vxor_vx_nxv2i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1151,7 +1148,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1163,7 +1160,7 @@ ; CHECK-LABEL: vxor_vi_nxv2i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1176,7 +1173,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1188,7 +1185,7 @@ ; CHECK-LABEL: vxor_vv_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vxor.vv v16, v16, v20 +; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1198,7 +1195,7 @@ ; CHECK-LABEL: vxor_vx_nxv4i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1210,7 +1207,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1222,7 +1219,7 @@ ; CHECK-LABEL: vxor_vi_nxv4i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1235,7 +1232,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1246,9 +1243,8 @@ define @vxor_vv_nxv8i64( %va, %vb) { ; CHECK-LABEL: vxor_vv_nxv8i64: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vxor.vv v16, v16, v8 +; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu +; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret %vc = xor %va, %vb ret %vc @@ -1258,7 +1254,7 @@ ; CHECK-LABEL: vxor_vx_nxv8i64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 %b, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1270,7 +1266,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i64_0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, -1 +; CHECK-NEXT: vxor.vi v8, v8, -1 ; CHECK-NEXT: ret %head = insertelement undef, i64 -1, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1282,7 +1278,7 @@ ; CHECK-LABEL: vxor_vi_nxv8i64_1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu -; CHECK-NEXT: vxor.vi v16, v16, 8 +; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret %head = insertelement undef, i64 8, i32 0 %splat = shufflevector %head, undef, zeroinitializer @@ -1295,7 +1291,7 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu -; CHECK-NEXT: vxor.vx v16, v16, a0 +; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret %head = insertelement undef, i64 16, i32 0 %splat = shufflevector %head, undef, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll --- a/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll @@ -9,8 +9,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv1i32.nxv1i8( @@ -30,7 +30,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v17, v0.t +; CHECK-NEXT: vzext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8( @@ -50,8 +50,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv2i32.nxv2i8( @@ -71,7 +71,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v17, v0.t +; CHECK-NEXT: vzext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8( @@ -91,8 +91,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vzext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv4i32.nxv4i8( @@ -112,7 +112,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v18, v0.t +; CHECK-NEXT: vzext.vf4 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv4i32.nxv4i8( @@ -132,8 +132,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vzext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv8i32.nxv8i8( @@ -153,7 +153,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v20, v0.t +; CHECK-NEXT: vzext.vf4 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv8i32.nxv8i8( @@ -173,8 +173,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vzext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv16i32.nxv16i8( @@ -193,10 +193,8 @@ define @intrinsic_vzext_mask_vf4_nxv16i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v26, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vzext.vf4 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv16i32.nxv16i8( @@ -216,8 +214,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv1i32.nxv1i16( @@ -237,7 +235,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i16( @@ -257,8 +255,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv2i32.nxv2i16( @@ -278,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i16( @@ -298,8 +296,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv4i32.nxv4i16( @@ -319,7 +317,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v18, v0.t +; CHECK-NEXT: vzext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv4i32.nxv4i16( @@ -339,8 +337,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv8i32.nxv8i16( @@ -360,7 +358,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v20, v0.t +; CHECK-NEXT: vzext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv8i32.nxv8i16( @@ -380,8 +378,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv16i32.nxv16i16( @@ -400,10 +398,8 @@ define @intrinsic_vzext_mask_vf2_nxv16i32( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vzext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv16i32.nxv16i16( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv1i16.nxv1i8( @@ -444,7 +440,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv1i16.nxv1i8( @@ -464,8 +460,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv2i16.nxv2i8( @@ -485,7 +481,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv2i16.nxv2i8( @@ -505,8 +501,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv4i16.nxv4i8( @@ -526,7 +522,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv4i16.nxv4i8( @@ -546,8 +542,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv8i16.nxv8i8( @@ -567,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v18, v0.t +; CHECK-NEXT: vzext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv8i16.nxv8i8( @@ -587,8 +583,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv16i16.nxv16i8( @@ -608,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v20, v0.t +; CHECK-NEXT: vzext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv16i16.nxv16i8( @@ -628,8 +624,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv32i16.nxv32i8( @@ -648,10 +644,8 @@ define @intrinsic_vzext_mask_vf2_nxv32i16( %0, %1, %2, i32 %3) nounwind { ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vzext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv32i16.nxv32i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll @@ -9,8 +9,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vzext.vf8 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf8 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv1i64.nxv1i8( @@ -30,7 +30,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf8_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vzext.vf8 v16, v17, v0.t +; CHECK-NEXT: vzext.vf8 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i8( @@ -50,8 +50,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vzext.vf8 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf8 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv2i64.nxv2i8( @@ -71,7 +71,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf8_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vzext.vf8 v16, v18, v0.t +; CHECK-NEXT: vzext.vf8 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i8( @@ -91,8 +91,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vzext.vf8 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf8 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv4i64.nxv4i8( @@ -112,7 +112,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf8_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vzext.vf8 v16, v20, v0.t +; CHECK-NEXT: vzext.vf8 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i8( @@ -132,8 +132,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf8_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vzext.vf8 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf8 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv8i64.nxv8i8( @@ -152,10 +152,8 @@ define @intrinsic_vzext_mask_vf8_nxv8i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vzext_mask_vf8_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m1,ta,mu -; CHECK-NEXT: vle8.v v25, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vzext.vf8 v16, v25, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vzext.vf8 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i8( @@ -175,8 +173,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv1i64.nxv1i16( @@ -196,7 +194,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v17, v0.t +; CHECK-NEXT: vzext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i16( @@ -216,8 +214,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vzext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv2i64.nxv2i16( @@ -237,7 +235,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v18, v0.t +; CHECK-NEXT: vzext.vf4 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i16( @@ -257,8 +255,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vzext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv4i64.nxv4i16( @@ -278,7 +276,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v20, v0.t +; CHECK-NEXT: vzext.vf4 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i16( @@ -298,8 +296,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vzext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv8i64.nxv8i16( @@ -318,10 +316,8 @@ define @intrinsic_vzext_mask_vf4_nxv8i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m2,ta,mu -; CHECK-NEXT: vle16.v v26, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v26, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vzext.vf4 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i16( @@ -341,8 +337,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv1i32.nxv1i8( @@ -362,7 +358,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v17, v0.t +; CHECK-NEXT: vzext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i8( @@ -382,8 +378,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vzext.vf4 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf4 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv2i32.nxv2i8( @@ -403,7 +399,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v17, v0.t +; CHECK-NEXT: vzext.vf4 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i8( @@ -423,8 +419,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vzext.vf4 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf4 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv4i32.nxv4i8( @@ -444,7 +440,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v18, v0.t +; CHECK-NEXT: vzext.vf4 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv4i32.nxv4i8( @@ -464,8 +460,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vzext.vf4 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf4 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv8i32.nxv8i8( @@ -485,7 +481,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v20, v0.t +; CHECK-NEXT: vzext.vf4 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv8i32.nxv8i8( @@ -505,8 +501,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf4_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vzext.vf4 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf4 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv16i32.nxv16i8( @@ -525,10 +521,8 @@ define @intrinsic_vzext_mask_vf4_nxv16i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vzext_mask_vf4_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m2,ta,mu -; CHECK-NEXT: vle8.v v26, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vzext.vf4 v16, v26, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vzext.vf4 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv16i32.nxv16i8( @@ -548,8 +542,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv1i64.nxv1i32( @@ -569,7 +563,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv1i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv1i64.nxv1i32( @@ -589,8 +583,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv2i64.nxv2i32( @@ -610,7 +604,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv2i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v18, v0.t +; CHECK-NEXT: vzext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv2i64.nxv2i32( @@ -630,8 +624,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv4i64.nxv4i32( @@ -651,7 +645,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv4i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v20, v0.t +; CHECK-NEXT: vzext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv4i64.nxv4i32( @@ -671,8 +665,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv8i64.nxv8i32( @@ -691,10 +685,8 @@ define @intrinsic_vzext_mask_vf2_nxv8i64( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e32,m4,ta,mu -; CHECK-NEXT: vle32.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e64,m8,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu +; CHECK-NEXT: vzext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv8i64.nxv8i32( @@ -714,8 +706,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv1i32.nxv1i16( @@ -735,7 +727,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv1i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv1i32.nxv1i16( @@ -755,8 +747,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv2i32.nxv2i16( @@ -776,7 +768,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv2i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv2i32.nxv2i16( @@ -796,8 +788,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv4i32.nxv4i16( @@ -817,7 +809,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv4i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v18, v0.t +; CHECK-NEXT: vzext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv4i32.nxv4i16( @@ -837,8 +829,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv8i32.nxv8i16( @@ -858,7 +850,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv8i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v20, v0.t +; CHECK-NEXT: vzext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv8i32.nxv8i16( @@ -878,8 +870,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv16i32.nxv16i16( @@ -898,10 +890,8 @@ define @intrinsic_vzext_mask_vf2_nxv16i32( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e16,m4,ta,mu -; CHECK-NEXT: vle16.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e32,m8,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu +; CHECK-NEXT: vzext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv16i32.nxv16i16( @@ -921,8 +911,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv1i16.nxv1i8( @@ -942,7 +932,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv1i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv1i16.nxv1i8( @@ -962,8 +952,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv2i16.nxv2i8( @@ -983,7 +973,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv2i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv2i16.nxv2i8( @@ -1003,8 +993,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu -; CHECK-NEXT: vzext.vf2 v25, v16 -; CHECK-NEXT: vmv1r.v v16, v25 +; CHECK-NEXT: vzext.vf2 v25, v8 +; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv4i16.nxv4i8( @@ -1024,7 +1014,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv4i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v17, v0.t +; CHECK-NEXT: vzext.vf2 v8, v9, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv4i16.nxv4i8( @@ -1044,8 +1034,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu -; CHECK-NEXT: vzext.vf2 v26, v16 -; CHECK-NEXT: vmv2r.v v16, v26 +; CHECK-NEXT: vzext.vf2 v26, v8 +; CHECK-NEXT: vmv2r.v v8, v26 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv8i16.nxv8i8( @@ -1065,7 +1055,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv8i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v18, v0.t +; CHECK-NEXT: vzext.vf2 v8, v10, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv8i16.nxv8i8( @@ -1085,8 +1075,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu -; CHECK-NEXT: vzext.vf2 v28, v16 -; CHECK-NEXT: vmv4r.v v16, v28 +; CHECK-NEXT: vzext.vf2 v28, v8 +; CHECK-NEXT: vmv4r.v v8, v28 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv16i16.nxv16i8( @@ -1106,7 +1096,7 @@ ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv16i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v20, v0.t +; CHECK-NEXT: vzext.vf2 v8, v12, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv16i16.nxv16i8( @@ -1126,8 +1116,8 @@ ; CHECK-LABEL: intrinsic_vzext_vf2_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu -; CHECK-NEXT: vzext.vf2 v8, v16 -; CHECK-NEXT: vmv8r.v v16, v8 +; CHECK-NEXT: vzext.vf2 v16, v8 +; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.nxv32i16.nxv32i8( @@ -1146,10 +1136,8 @@ define @intrinsic_vzext_mask_vf2_nxv32i16( %0, %1, %2, i64 %3) nounwind { ; CHECK-LABEL: intrinsic_vzext_mask_vf2_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli a2, zero, e8,m4,ta,mu -; CHECK-NEXT: vle8.v v28, (a0) -; CHECK-NEXT: vsetvli a0, a1, e16,m8,tu,mu -; CHECK-NEXT: vzext.vf2 v16, v28, v0.t +; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu +; CHECK-NEXT: vzext.vf2 v8, v16, v0.t ; CHECK-NEXT: jalr zero, 0(ra) entry: %a = call @llvm.riscv.vzext.mask.nxv32i16.nxv32i8( diff --git a/llvm/test/CodeGen/RISCV/scalable-vector-struct.ll b/llvm/test/CodeGen/RISCV/scalable-vector-struct.ll --- a/llvm/test/CodeGen/RISCV/scalable-vector-struct.ll +++ b/llvm/test/CodeGen/RISCV/scalable-vector-struct.ll @@ -8,8 +8,8 @@ ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a3, zero, e32,m1,ta,mu -; CHECK-NEXT: vse32.v v16, (a1) -; CHECK-NEXT: vse32.v v17, (a2) +; CHECK-NEXT: vse32.v v8, (a1) +; CHECK-NEXT: vse32.v v9, (a2) ; CHECK-NEXT: ret entry: br label %return